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65883b78bc
Aligning address to page boundary allows flush_tlb_kernel_range() to know it's a single page flush and use tlbie instead of tlbia. On 603 we now have the following code in first leg of change_page_attr(): 2c: 55 29 00 3c rlwinm r9,r9,0,0,30 30: 91 23 00 00 stw r9,0(r3) 34: 7c 00 22 64 tlbie r4,r0 38: 7c 00 04 ac hwsync 3c: 38 60 00 00 li r3,0 40: 4e 80 00 20 blr Before we had: 28: 55 29 00 3c rlwinm r9,r9,0,0,30 2c: 91 23 00 00 stw r9,0(r3) 30: 54 89 00 26 rlwinm r9,r4,0,0,19 34: 38 84 10 00 addi r4,r4,4096 38: 7c 89 20 50 subf r4,r9,r4 3c: 28 04 10 00 cmplwi r4,4096 40: 41 81 00 30 bgt 70 <change_page_attr+0x70> 44: 7c 00 4a 64 tlbie r9,r0 48: 7c 00 04 ac hwsync 4c: 38 60 00 00 li r3,0 50: 4e 80 00 20 blr ... 70: 94 21 ff f0 stwu r1,-16(r1) 74: 7c 08 02 a6 mflr r0 78: 90 01 00 14 stw r0,20(r1) 7c: 48 00 00 01 bl 7c <change_page_attr+0x7c> 7c: R_PPC_REL24 _tlbia 80: 80 01 00 14 lwz r0,20(r1) 84: 38 60 00 00 li r3,0 88: 7c 08 03 a6 mtlr r0 8c: 38 21 00 10 addi r1,r1,16 90: 4e 80 00 20 blr Signed-off-by: Christophe Leroy <christophe.leroy@csgroup.eu> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/6bb118fb2ee89fa3c1f9cf90ed19f88220002cb0.1647877467.git.christophe.leroy@csgroup.eu
99 lines
2.5 KiB
C
99 lines
2.5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* MMU-generic set_memory implementation for powerpc
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*
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* Copyright 2019-2021, IBM Corporation.
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*/
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#include <linux/mm.h>
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#include <linux/vmalloc.h>
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#include <linux/set_memory.h>
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#include <asm/mmu.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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static pte_basic_t pte_update_delta(pte_t *ptep, unsigned long addr,
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unsigned long old, unsigned long new)
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{
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return pte_update(&init_mm, addr, ptep, old & ~new, new & ~old, 0);
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}
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/*
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* Updates the attributes of a page atomically.
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*
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* This sequence is safe against concurrent updates, and also allows updating the
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* attributes of a page currently being executed or accessed.
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*/
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static int change_page_attr(pte_t *ptep, unsigned long addr, void *data)
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{
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long action = (long)data;
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addr &= PAGE_MASK;
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/* modify the PTE bits as desired */
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switch (action) {
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case SET_MEMORY_RO:
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/* Don't clear DIRTY bit */
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pte_update_delta(ptep, addr, _PAGE_KERNEL_RW & ~_PAGE_DIRTY, _PAGE_KERNEL_RO);
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break;
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case SET_MEMORY_RW:
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pte_update_delta(ptep, addr, _PAGE_KERNEL_RO, _PAGE_KERNEL_RW);
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break;
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case SET_MEMORY_NX:
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pte_update_delta(ptep, addr, _PAGE_KERNEL_ROX, _PAGE_KERNEL_RO);
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break;
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case SET_MEMORY_X:
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pte_update_delta(ptep, addr, _PAGE_KERNEL_RO, _PAGE_KERNEL_ROX);
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break;
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case SET_MEMORY_NP:
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pte_update(&init_mm, addr, ptep, _PAGE_PRESENT, 0, 0);
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break;
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case SET_MEMORY_P:
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pte_update(&init_mm, addr, ptep, 0, _PAGE_PRESENT, 0);
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break;
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default:
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WARN_ON_ONCE(1);
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break;
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}
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/* See ptesync comment in radix__set_pte_at() */
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if (radix_enabled())
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asm volatile("ptesync": : :"memory");
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flush_tlb_kernel_range(addr, addr + PAGE_SIZE);
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return 0;
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}
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int change_memory_attr(unsigned long addr, int numpages, long action)
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{
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unsigned long start = ALIGN_DOWN(addr, PAGE_SIZE);
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unsigned long size = numpages * PAGE_SIZE;
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if (!numpages)
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return 0;
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if (WARN_ON_ONCE(is_vmalloc_or_module_addr((void *)addr) &&
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is_vm_area_hugepages((void *)addr)))
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return -EINVAL;
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#ifdef CONFIG_PPC_BOOK3S_64
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/*
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* On hash, the linear mapping is not in the Linux page table so
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* apply_to_existing_page_range() will have no effect. If in the future
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* the set_memory_* functions are used on the linear map this will need
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* to be updated.
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*/
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if (!radix_enabled()) {
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int region = get_region_id(addr);
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if (WARN_ON_ONCE(region != VMALLOC_REGION_ID && region != IO_REGION_ID))
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return -EINVAL;
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}
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#endif
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return apply_to_existing_page_range(&init_mm, start, size,
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change_page_attr, (void *)action);
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}
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