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![Jeremy Kerr](/assets/img/avatar_default.png)
For slaves that are behind a software-clocked master, we want FSI CFAMs to run asynchronously to the FSI clock, so set up our slaves to be in async mode. Signed-off-by: Jeremy Kerr <jk@ozlabs.org> Signed-off-by: Christopher Bostic <cbostic@linux.vnet.ibm.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
604 lines
14 KiB
C
604 lines
14 KiB
C
/*
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* A FSI master controller, using a simple GPIO bit-banging interface
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*/
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#include <linux/crc4.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/fsi.h>
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#include <linux/gpio/consumer.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spinlock.h>
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#include "fsi-master.h"
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#define FSI_GPIO_STD_DLY 1 /* Standard pin delay in nS */
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#define FSI_ECHO_DELAY_CLOCKS 16 /* Number clocks for echo delay */
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#define FSI_PRE_BREAK_CLOCKS 50 /* Number clocks to prep for break */
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#define FSI_BREAK_CLOCKS 256 /* Number of clocks to issue break */
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#define FSI_POST_BREAK_CLOCKS 16000 /* Number clocks to set up cfam */
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#define FSI_INIT_CLOCKS 5000 /* Clock out any old data */
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#define FSI_GPIO_STD_DELAY 10 /* Standard GPIO delay in nS */
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/* todo: adjust down as low as */
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/* possible or eliminate */
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#define FSI_GPIO_CMD_DPOLL 0x2
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#define FSI_GPIO_CMD_TERM 0x3f
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#define FSI_GPIO_CMD_ABS_AR 0x4
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#define FSI_GPIO_DPOLL_CLOCKS 100 /* < 21 will cause slave to hang */
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/* Bus errors */
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#define FSI_GPIO_ERR_BUSY 1 /* Slave stuck in busy state */
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#define FSI_GPIO_RESP_ERRA 2 /* Any (misc) Error */
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#define FSI_GPIO_RESP_ERRC 3 /* Slave reports master CRC error */
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#define FSI_GPIO_MTOE 4 /* Master time out error */
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#define FSI_GPIO_CRC_INVAL 5 /* Master reports slave CRC error */
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/* Normal slave responses */
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#define FSI_GPIO_RESP_BUSY 1
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#define FSI_GPIO_RESP_ACK 0
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#define FSI_GPIO_RESP_ACKD 4
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#define FSI_GPIO_MAX_BUSY 100
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#define FSI_GPIO_MTOE_COUNT 1000
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#define FSI_GPIO_DRAIN_BITS 20
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#define FSI_GPIO_CRC_SIZE 4
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#define FSI_GPIO_MSG_ID_SIZE 2
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#define FSI_GPIO_MSG_RESPID_SIZE 2
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#define FSI_GPIO_PRIME_SLAVE_CLOCKS 100
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struct fsi_master_gpio {
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struct fsi_master master;
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struct device *dev;
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spinlock_t cmd_lock; /* Lock for commands */
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struct gpio_desc *gpio_clk;
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struct gpio_desc *gpio_data;
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struct gpio_desc *gpio_trans; /* Voltage translator */
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struct gpio_desc *gpio_enable; /* FSI enable */
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struct gpio_desc *gpio_mux; /* Mux control */
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};
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#define CREATE_TRACE_POINTS
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#include <trace/events/fsi_master_gpio.h>
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#define to_fsi_master_gpio(m) container_of(m, struct fsi_master_gpio, master)
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struct fsi_gpio_msg {
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uint64_t msg;
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uint8_t bits;
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};
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static void clock_toggle(struct fsi_master_gpio *master, int count)
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{
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int i;
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for (i = 0; i < count; i++) {
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ndelay(FSI_GPIO_STD_DLY);
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gpiod_set_value(master->gpio_clk, 0);
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ndelay(FSI_GPIO_STD_DLY);
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gpiod_set_value(master->gpio_clk, 1);
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}
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}
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static int sda_in(struct fsi_master_gpio *master)
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{
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int in;
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ndelay(FSI_GPIO_STD_DLY);
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in = gpiod_get_value(master->gpio_data);
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return in ? 1 : 0;
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}
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static void sda_out(struct fsi_master_gpio *master, int value)
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{
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gpiod_set_value(master->gpio_data, value);
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}
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static void set_sda_input(struct fsi_master_gpio *master)
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{
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gpiod_direction_input(master->gpio_data);
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gpiod_set_value(master->gpio_trans, 0);
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}
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static void set_sda_output(struct fsi_master_gpio *master, int value)
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{
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gpiod_set_value(master->gpio_trans, 1);
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gpiod_direction_output(master->gpio_data, value);
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}
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static void clock_zeros(struct fsi_master_gpio *master, int count)
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{
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set_sda_output(master, 1);
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clock_toggle(master, count);
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}
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static void serial_in(struct fsi_master_gpio *master, struct fsi_gpio_msg *msg,
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uint8_t num_bits)
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{
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uint8_t bit, in_bit;
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set_sda_input(master);
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for (bit = 0; bit < num_bits; bit++) {
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clock_toggle(master, 1);
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in_bit = sda_in(master);
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msg->msg <<= 1;
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msg->msg |= ~in_bit & 0x1; /* Data is active low */
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}
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msg->bits += num_bits;
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trace_fsi_master_gpio_in(master, num_bits, msg->msg);
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}
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static void serial_out(struct fsi_master_gpio *master,
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const struct fsi_gpio_msg *cmd)
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{
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uint8_t bit;
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uint64_t msg = ~cmd->msg; /* Data is active low */
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uint64_t sda_mask = 0x1ULL << (cmd->bits - 1);
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uint64_t last_bit = ~0;
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int next_bit;
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trace_fsi_master_gpio_out(master, cmd->bits, cmd->msg);
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if (!cmd->bits) {
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dev_warn(master->dev, "trying to output 0 bits\n");
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return;
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}
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set_sda_output(master, 0);
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/* Send the start bit */
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sda_out(master, 0);
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clock_toggle(master, 1);
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/* Send the message */
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for (bit = 0; bit < cmd->bits; bit++) {
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next_bit = (msg & sda_mask) >> (cmd->bits - 1);
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if (last_bit ^ next_bit) {
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sda_out(master, next_bit);
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last_bit = next_bit;
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}
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clock_toggle(master, 1);
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msg <<= 1;
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}
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}
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static void msg_push_bits(struct fsi_gpio_msg *msg, uint64_t data, int bits)
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{
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msg->msg <<= bits;
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msg->msg |= data & ((1ull << bits) - 1);
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msg->bits += bits;
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}
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static void msg_push_crc(struct fsi_gpio_msg *msg)
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{
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uint8_t crc;
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int top;
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top = msg->bits & 0x3;
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/* start bit, and any non-aligned top bits */
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crc = crc4(0, 1 << top | msg->msg >> (msg->bits - top), top + 1);
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/* aligned bits */
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crc = crc4(crc, msg->msg, msg->bits - top);
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msg_push_bits(msg, crc, 4);
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}
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/*
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* Encode an Absolute Address command
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*/
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static void build_abs_ar_command(struct fsi_gpio_msg *cmd,
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uint8_t id, uint32_t addr, size_t size, const void *data)
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{
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bool write = !!data;
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uint8_t ds;
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int i;
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cmd->bits = 0;
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cmd->msg = 0;
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msg_push_bits(cmd, id, 2);
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msg_push_bits(cmd, FSI_GPIO_CMD_ABS_AR, 3);
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msg_push_bits(cmd, write ? 0 : 1, 1);
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/*
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* The read/write size is encoded in the lower bits of the address
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* (as it must be naturally-aligned), and the following ds bit.
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*
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* size addr:1 addr:0 ds
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* 1 x x 0
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* 2 x 0 1
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* 4 0 1 1
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*
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*/
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ds = size > 1 ? 1 : 0;
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addr &= ~(size - 1);
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if (size == 4)
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addr |= 1;
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msg_push_bits(cmd, addr & ((1 << 21) - 1), 21);
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msg_push_bits(cmd, ds, 1);
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for (i = 0; write && i < size; i++)
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msg_push_bits(cmd, ((uint8_t *)data)[i], 8);
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msg_push_crc(cmd);
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}
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static void build_dpoll_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
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{
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cmd->bits = 0;
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cmd->msg = 0;
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msg_push_bits(cmd, slave_id, 2);
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msg_push_bits(cmd, FSI_GPIO_CMD_DPOLL, 3);
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msg_push_crc(cmd);
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}
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static void echo_delay(struct fsi_master_gpio *master)
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{
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set_sda_output(master, 1);
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clock_toggle(master, FSI_ECHO_DELAY_CLOCKS);
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}
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static void build_term_command(struct fsi_gpio_msg *cmd, uint8_t slave_id)
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{
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cmd->bits = 0;
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cmd->msg = 0;
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msg_push_bits(cmd, slave_id, 2);
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msg_push_bits(cmd, FSI_GPIO_CMD_TERM, 6);
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msg_push_crc(cmd);
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}
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/*
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* Store information on master errors so handler can detect and clean
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* up the bus
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*/
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static void fsi_master_gpio_error(struct fsi_master_gpio *master, int error)
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{
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}
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static int read_one_response(struct fsi_master_gpio *master,
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uint8_t data_size, struct fsi_gpio_msg *msgp, uint8_t *tagp)
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{
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struct fsi_gpio_msg msg;
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uint8_t id, tag;
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uint32_t crc;
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int i;
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/* wait for the start bit */
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for (i = 0; i < FSI_GPIO_MTOE_COUNT; i++) {
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msg.bits = 0;
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msg.msg = 0;
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serial_in(master, &msg, 1);
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if (msg.msg)
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break;
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}
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if (i == FSI_GPIO_MTOE_COUNT) {
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dev_dbg(master->dev,
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"Master time out waiting for response\n");
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fsi_master_gpio_error(master, FSI_GPIO_MTOE);
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return -EIO;
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}
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msg.bits = 0;
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msg.msg = 0;
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/* Read slave ID & response tag */
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serial_in(master, &msg, 4);
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id = (msg.msg >> FSI_GPIO_MSG_RESPID_SIZE) & 0x3;
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tag = msg.msg & 0x3;
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/* If we have an ACK and we're expecting data, clock the data in too */
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if (tag == FSI_GPIO_RESP_ACK && data_size)
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serial_in(master, &msg, data_size * 8);
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/* read CRC */
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serial_in(master, &msg, FSI_GPIO_CRC_SIZE);
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/* we have a whole message now; check CRC */
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crc = crc4(0, 1, 1);
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crc = crc4(crc, msg.msg, msg.bits);
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if (crc) {
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dev_dbg(master->dev, "ERR response CRC\n");
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fsi_master_gpio_error(master, FSI_GPIO_CRC_INVAL);
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return -EIO;
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}
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if (msgp)
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*msgp = msg;
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if (tagp)
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*tagp = tag;
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return 0;
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}
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static int issue_term(struct fsi_master_gpio *master, uint8_t slave)
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{
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struct fsi_gpio_msg cmd;
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uint8_t tag;
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int rc;
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build_term_command(&cmd, slave);
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serial_out(master, &cmd);
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echo_delay(master);
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rc = read_one_response(master, 0, NULL, &tag);
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if (rc < 0) {
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dev_err(master->dev,
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"TERM failed; lost communication with slave\n");
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return -EIO;
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} else if (tag != FSI_GPIO_RESP_ACK) {
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dev_err(master->dev, "TERM failed; response %d\n", tag);
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return -EIO;
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}
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return 0;
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}
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static int poll_for_response(struct fsi_master_gpio *master,
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uint8_t slave, uint8_t size, void *data)
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{
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struct fsi_gpio_msg response, cmd;
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int busy_count = 0, rc, i;
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uint8_t tag;
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uint8_t *data_byte = data;
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retry:
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rc = read_one_response(master, size, &response, &tag);
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if (rc)
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return rc;
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switch (tag) {
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case FSI_GPIO_RESP_ACK:
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if (size && data) {
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uint64_t val = response.msg;
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/* clear crc & mask */
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val >>= 4;
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val &= (1ull << (size * 8)) - 1;
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for (i = 0; i < size; i++) {
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data_byte[size-i-1] = val;
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val >>= 8;
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}
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}
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break;
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case FSI_GPIO_RESP_BUSY:
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/*
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* Its necessary to clock slave before issuing
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* d-poll, not indicated in the hardware protocol
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* spec. < 20 clocks causes slave to hang, 21 ok.
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*/
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clock_zeros(master, FSI_GPIO_DPOLL_CLOCKS);
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if (busy_count++ < FSI_GPIO_MAX_BUSY) {
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build_dpoll_command(&cmd, slave);
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serial_out(master, &cmd);
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echo_delay(master);
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goto retry;
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}
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dev_warn(master->dev,
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"ERR slave is stuck in busy state, issuing TERM\n");
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issue_term(master, slave);
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rc = -EIO;
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break;
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case FSI_GPIO_RESP_ERRA:
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case FSI_GPIO_RESP_ERRC:
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dev_dbg(master->dev, "ERR%c received: 0x%x\n",
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tag == FSI_GPIO_RESP_ERRA ? 'A' : 'C',
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(int)response.msg);
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fsi_master_gpio_error(master, response.msg);
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rc = -EIO;
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break;
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}
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/* Clock the slave enough to be ready for next operation */
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clock_zeros(master, FSI_GPIO_PRIME_SLAVE_CLOCKS);
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return rc;
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}
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static int fsi_master_gpio_xfer(struct fsi_master_gpio *master, uint8_t slave,
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struct fsi_gpio_msg *cmd, size_t resp_len, void *resp)
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{
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unsigned long flags;
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int rc;
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spin_lock_irqsave(&master->cmd_lock, flags);
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serial_out(master, cmd);
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echo_delay(master);
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rc = poll_for_response(master, slave, resp_len, resp);
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spin_unlock_irqrestore(&master->cmd_lock, flags);
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return rc;
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}
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static int fsi_master_gpio_read(struct fsi_master *_master, int link,
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uint8_t id, uint32_t addr, void *val, size_t size)
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{
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struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
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struct fsi_gpio_msg cmd;
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if (link != 0)
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return -ENODEV;
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build_abs_ar_command(&cmd, id, addr, size, NULL);
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return fsi_master_gpio_xfer(master, id, &cmd, size, val);
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}
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static int fsi_master_gpio_write(struct fsi_master *_master, int link,
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uint8_t id, uint32_t addr, const void *val, size_t size)
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{
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struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
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struct fsi_gpio_msg cmd;
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if (link != 0)
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return -ENODEV;
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build_abs_ar_command(&cmd, id, addr, size, val);
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return fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
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}
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static int fsi_master_gpio_term(struct fsi_master *_master,
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int link, uint8_t id)
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{
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struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
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struct fsi_gpio_msg cmd;
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if (link != 0)
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return -ENODEV;
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build_term_command(&cmd, id);
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return fsi_master_gpio_xfer(master, id, &cmd, 0, NULL);
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}
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static int fsi_master_gpio_break(struct fsi_master *_master, int link)
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{
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struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
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if (link != 0)
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return -ENODEV;
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trace_fsi_master_gpio_break(master);
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set_sda_output(master, 1);
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sda_out(master, 1);
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clock_toggle(master, FSI_PRE_BREAK_CLOCKS);
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sda_out(master, 0);
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clock_toggle(master, FSI_BREAK_CLOCKS);
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echo_delay(master);
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sda_out(master, 1);
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clock_toggle(master, FSI_POST_BREAK_CLOCKS);
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/* Wait for logic reset to take effect */
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udelay(200);
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return 0;
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}
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static void fsi_master_gpio_init(struct fsi_master_gpio *master)
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{
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gpiod_direction_output(master->gpio_mux, 1);
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gpiod_direction_output(master->gpio_trans, 1);
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gpiod_direction_output(master->gpio_enable, 1);
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gpiod_direction_output(master->gpio_clk, 1);
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gpiod_direction_output(master->gpio_data, 1);
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/* todo: evaluate if clocks can be reduced */
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clock_zeros(master, FSI_INIT_CLOCKS);
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}
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static int fsi_master_gpio_link_enable(struct fsi_master *_master, int link)
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{
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struct fsi_master_gpio *master = to_fsi_master_gpio(_master);
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if (link != 0)
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return -ENODEV;
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|
gpiod_set_value(master->gpio_enable, 1);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int fsi_master_gpio_probe(struct platform_device *pdev)
|
|
{
|
|
struct fsi_master_gpio *master;
|
|
struct gpio_desc *gpio;
|
|
|
|
master = devm_kzalloc(&pdev->dev, sizeof(*master), GFP_KERNEL);
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
master->dev = &pdev->dev;
|
|
master->master.dev.parent = master->dev;
|
|
|
|
gpio = devm_gpiod_get(&pdev->dev, "clock", 0);
|
|
if (IS_ERR(gpio)) {
|
|
dev_err(&pdev->dev, "failed to get clock gpio\n");
|
|
return PTR_ERR(gpio);
|
|
}
|
|
master->gpio_clk = gpio;
|
|
|
|
gpio = devm_gpiod_get(&pdev->dev, "data", 0);
|
|
if (IS_ERR(gpio)) {
|
|
dev_err(&pdev->dev, "failed to get data gpio\n");
|
|
return PTR_ERR(gpio);
|
|
}
|
|
master->gpio_data = gpio;
|
|
|
|
/* Optional GPIOs */
|
|
gpio = devm_gpiod_get_optional(&pdev->dev, "trans", 0);
|
|
if (IS_ERR(gpio)) {
|
|
dev_err(&pdev->dev, "failed to get trans gpio\n");
|
|
return PTR_ERR(gpio);
|
|
}
|
|
master->gpio_trans = gpio;
|
|
|
|
gpio = devm_gpiod_get_optional(&pdev->dev, "enable", 0);
|
|
if (IS_ERR(gpio)) {
|
|
dev_err(&pdev->dev, "failed to get enable gpio\n");
|
|
return PTR_ERR(gpio);
|
|
}
|
|
master->gpio_enable = gpio;
|
|
|
|
gpio = devm_gpiod_get_optional(&pdev->dev, "mux", 0);
|
|
if (IS_ERR(gpio)) {
|
|
dev_err(&pdev->dev, "failed to get mux gpio\n");
|
|
return PTR_ERR(gpio);
|
|
}
|
|
master->gpio_mux = gpio;
|
|
|
|
master->master.n_links = 1;
|
|
master->master.flags = FSI_MASTER_FLAG_SWCLOCK;
|
|
master->master.read = fsi_master_gpio_read;
|
|
master->master.write = fsi_master_gpio_write;
|
|
master->master.term = fsi_master_gpio_term;
|
|
master->master.send_break = fsi_master_gpio_break;
|
|
master->master.link_enable = fsi_master_gpio_link_enable;
|
|
platform_set_drvdata(pdev, master);
|
|
spin_lock_init(&master->cmd_lock);
|
|
|
|
fsi_master_gpio_init(master);
|
|
|
|
return fsi_master_register(&master->master);
|
|
}
|
|
|
|
|
|
static int fsi_master_gpio_remove(struct platform_device *pdev)
|
|
{
|
|
struct fsi_master_gpio *master = platform_get_drvdata(pdev);
|
|
|
|
devm_gpiod_put(&pdev->dev, master->gpio_clk);
|
|
devm_gpiod_put(&pdev->dev, master->gpio_data);
|
|
if (master->gpio_trans)
|
|
devm_gpiod_put(&pdev->dev, master->gpio_trans);
|
|
if (master->gpio_enable)
|
|
devm_gpiod_put(&pdev->dev, master->gpio_enable);
|
|
if (master->gpio_mux)
|
|
devm_gpiod_put(&pdev->dev, master->gpio_mux);
|
|
fsi_master_unregister(&master->master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct of_device_id fsi_master_gpio_match[] = {
|
|
{ .compatible = "fsi-master-gpio" },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver fsi_master_gpio_driver = {
|
|
.driver = {
|
|
.name = "fsi-master-gpio",
|
|
.of_match_table = fsi_master_gpio_match,
|
|
},
|
|
.probe = fsi_master_gpio_probe,
|
|
.remove = fsi_master_gpio_remove,
|
|
};
|
|
|
|
module_platform_driver(fsi_master_gpio_driver);
|
|
MODULE_LICENSE("GPL");
|