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a0e7df335a
On some devices (TH 2.x devices at the moment), the internal time counter is initially not synchronized to the global crystal clock, so the time stamps it produces will not be useful. In this case, the driver needs to force the time counter resync. This applies the workaround to relevant devices. Signed-off-by: Alexander Shishkin <alexander.shishkin@linux.intel.com>
68 lines
2.2 KiB
C
68 lines
2.2 KiB
C
/*
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* Intel(R) Trace Hub Global Trace Hub (GTH) data structures
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*
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* Copyright (C) 2014-2015 Intel Corporation.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*/
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#ifndef __INTEL_TH_GTH_H__
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#define __INTEL_TH_GTH_H__
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/* Map output port parameter bits to symbolic names */
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#define TH_OUTPUT_PARM(name) \
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TH_OUTPUT_ ## name
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enum intel_th_output_parm {
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/* output port type */
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TH_OUTPUT_PARM(port),
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/* generate NULL packet */
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TH_OUTPUT_PARM(null),
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/* packet drop */
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TH_OUTPUT_PARM(drop),
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/* port in reset state */
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TH_OUTPUT_PARM(reset),
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/* flush out data */
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TH_OUTPUT_PARM(flush),
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/* mainenance packet frequency */
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TH_OUTPUT_PARM(smcfreq),
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};
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/*
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* Register offsets
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*/
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enum {
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REG_GTH_GTHOPT0 = 0x00, /* Output ports 0..3 config */
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REG_GTH_GTHOPT1 = 0x04, /* Output ports 4..7 config */
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REG_GTH_SWDEST0 = 0x08, /* Switching destination masters 0..7 */
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REG_GTH_GSWTDEST = 0x88, /* Global sw trace destination */
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REG_GTH_SMCR0 = 0x9c, /* STP mainenance for ports 0/1 */
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REG_GTH_SMCR1 = 0xa0, /* STP mainenance for ports 2/3 */
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REG_GTH_SMCR2 = 0xa4, /* STP mainenance for ports 4/5 */
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REG_GTH_SMCR3 = 0xa8, /* STP mainenance for ports 6/7 */
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REG_GTH_SCR = 0xc8, /* Source control (storeEn override) */
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REG_GTH_STAT = 0xd4, /* GTH status */
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REG_GTH_SCR2 = 0xd8, /* Source control (force storeEn off) */
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REG_GTH_DESTOVR = 0xdc, /* Destination override */
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REG_GTH_SCRPD0 = 0xe0, /* ScratchPad[0] */
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REG_GTH_SCRPD1 = 0xe4, /* ScratchPad[1] */
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REG_GTH_SCRPD2 = 0xe8, /* ScratchPad[2] */
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REG_GTH_SCRPD3 = 0xec, /* ScratchPad[3] */
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REG_TSCU_TSUCTRL = 0x2000, /* TSCU control register */
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REG_TSCU_TSCUSTAT = 0x2004, /* TSCU status register */
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};
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/* waiting for Pipeline Empty bit(s) to assert for GTH */
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#define GTH_PLE_WAITLOOP_DEPTH 10000
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#define TSUCTRL_CTCRESYNC BIT(0)
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#define TSCUSTAT_CTCSYNCING BIT(1)
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#endif /* __INTEL_TH_GTH_H__ */
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