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![Benjamin Herrenschmidt](/assets/img/avatar_default.png)
On Power8 & Power9 the early CPU inititialisation in __init_HFSCR()
turns on HFSCR[TM] (Hypervisor Facility Status and Control Register
[Transactional Memory]), but that doesn't take into account that TM
might be disabled by CPU features, or disabled by the kernel being built
with CONFIG_PPC_TRANSACTIONAL_MEM=n.
So later in boot, when we have setup the CPU features, clear HSCR[TM] if
the TM CPU feature has been disabled. We use CPU_FTR_TM_COMP to account
for the CONFIG_PPC_TRANSACTIONAL_MEM=n case.
Without this a KVM guest might try use TM, even if told not to, and
cause an oops in the host kernel. Typically the oops is seen in
__kvmppc_vcore_entry() and may or may not be fatal to the host, but is
always bad news.
In practice all shipping CPU revisions do support TM, and all host
kernels we are aware of build with TM support enabled, so no one should
actually be able to hit this in the wild.
Fixes: 2a3563b023
("powerpc: Setup in HFSCR for POWER8")
Cc: stable@vger.kernel.org # v3.10+
Signed-off-by: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Tested-by: Sam Bobroff <sam.bobroff@au1.ibm.com>
[mpe: Rewrite change log with input from Sam, add Fixes/stable]
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
736 lines
19 KiB
C
736 lines
19 KiB
C
/*
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*
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* Common boot and setup code.
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*
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* Copyright (C) 2001 PPC64 Team, IBM Corp
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#define DEBUG
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#include <linux/export.h>
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#include <linux/string.h>
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#include <linux/sched.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/reboot.h>
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#include <linux/delay.h>
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#include <linux/initrd.h>
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#include <linux/seq_file.h>
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#include <linux/ioport.h>
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#include <linux/console.h>
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#include <linux/utsname.h>
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#include <linux/tty.h>
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#include <linux/root_dev.h>
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#include <linux/notifier.h>
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#include <linux/cpu.h>
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#include <linux/unistd.h>
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#include <linux/serial.h>
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#include <linux/serial_8250.h>
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#include <linux/bootmem.h>
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#include <linux/pci.h>
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#include <linux/lockdep.h>
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#include <linux/memblock.h>
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#include <linux/memory.h>
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#include <linux/nmi.h>
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#include <asm/io.h>
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#include <asm/kdump.h>
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#include <asm/prom.h>
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#include <asm/processor.h>
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#include <asm/pgtable.h>
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#include <asm/smp.h>
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#include <asm/elf.h>
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#include <asm/machdep.h>
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#include <asm/paca.h>
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#include <asm/time.h>
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#include <asm/cputable.h>
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#include <asm/sections.h>
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#include <asm/btext.h>
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#include <asm/nvram.h>
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#include <asm/setup.h>
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#include <asm/rtas.h>
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#include <asm/iommu.h>
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#include <asm/serial.h>
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#include <asm/cache.h>
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#include <asm/page.h>
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#include <asm/mmu.h>
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#include <asm/firmware.h>
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#include <asm/xmon.h>
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#include <asm/udbg.h>
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#include <asm/kexec.h>
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#include <asm/code-patching.h>
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#include <asm/livepatch.h>
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#include <asm/opal.h>
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#include <asm/cputhreads.h>
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#ifdef DEBUG
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#define DBG(fmt...) udbg_printf(fmt)
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#else
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#define DBG(fmt...)
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#endif
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int spinning_secondaries;
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u64 ppc64_pft_size;
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struct ppc64_caches ppc64_caches = {
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.l1d = {
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.block_size = 0x40,
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.log_block_size = 6,
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},
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.l1i = {
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.block_size = 0x40,
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.log_block_size = 6
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},
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};
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EXPORT_SYMBOL_GPL(ppc64_caches);
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#if defined(CONFIG_PPC_BOOK3E) && defined(CONFIG_SMP)
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void __init setup_tlb_core_data(void)
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{
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int cpu;
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BUILD_BUG_ON(offsetof(struct tlb_core_data, lock) != 0);
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for_each_possible_cpu(cpu) {
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int first = cpu_first_thread_sibling(cpu);
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/*
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* If we boot via kdump on a non-primary thread,
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* make sure we point at the thread that actually
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* set up this TLB.
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*/
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if (cpu_first_thread_sibling(boot_cpuid) == first)
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first = boot_cpuid;
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paca[cpu].tcd_ptr = &paca[first].tcd;
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/*
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* If we have threads, we need either tlbsrx.
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* or e6500 tablewalk mode, or else TLB handlers
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* will be racy and could produce duplicate entries.
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* Should we panic instead?
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*/
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WARN_ONCE(smt_enabled_at_boot >= 2 &&
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!mmu_has_feature(MMU_FTR_USE_TLBRSRV) &&
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book3e_htw_mode != PPC_HTW_E6500,
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"%s: unsupported MMU configuration\n", __func__);
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}
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}
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#endif
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#ifdef CONFIG_SMP
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static char *smt_enabled_cmdline;
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/* Look for ibm,smt-enabled OF option */
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void __init check_smt_enabled(void)
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{
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struct device_node *dn;
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const char *smt_option;
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/* Default to enabling all threads */
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smt_enabled_at_boot = threads_per_core;
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/* Allow the command line to overrule the OF option */
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if (smt_enabled_cmdline) {
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if (!strcmp(smt_enabled_cmdline, "on"))
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smt_enabled_at_boot = threads_per_core;
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else if (!strcmp(smt_enabled_cmdline, "off"))
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smt_enabled_at_boot = 0;
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else {
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int smt;
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int rc;
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rc = kstrtoint(smt_enabled_cmdline, 10, &smt);
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if (!rc)
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smt_enabled_at_boot =
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min(threads_per_core, smt);
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}
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} else {
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dn = of_find_node_by_path("/options");
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if (dn) {
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smt_option = of_get_property(dn, "ibm,smt-enabled",
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NULL);
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if (smt_option) {
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if (!strcmp(smt_option, "on"))
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smt_enabled_at_boot = threads_per_core;
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else if (!strcmp(smt_option, "off"))
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smt_enabled_at_boot = 0;
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}
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of_node_put(dn);
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}
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}
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}
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/* Look for smt-enabled= cmdline option */
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static int __init early_smt_enabled(char *p)
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{
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smt_enabled_cmdline = p;
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return 0;
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}
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early_param("smt-enabled", early_smt_enabled);
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#endif /* CONFIG_SMP */
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/** Fix up paca fields required for the boot cpu */
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static void __init fixup_boot_paca(void)
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{
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/* The boot cpu is started */
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get_paca()->cpu_start = 1;
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/* Allow percpu accesses to work until we setup percpu data */
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get_paca()->data_offset = 0;
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}
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static void __init configure_exceptions(void)
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{
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/*
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* Setup the trampolines from the lowmem exception vectors
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* to the kdump kernel when not using a relocatable kernel.
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*/
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setup_kdump_trampoline();
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/* Under a PAPR hypervisor, we need hypercalls */
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if (firmware_has_feature(FW_FEATURE_SET_MODE)) {
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/* Enable AIL if possible */
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pseries_enable_reloc_on_exc();
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/*
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* Tell the hypervisor that we want our exceptions to
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* be taken in little endian mode.
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*
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* We don't call this for big endian as our calling convention
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* makes us always enter in BE, and the call may fail under
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* some circumstances with kdump.
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*/
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#ifdef __LITTLE_ENDIAN__
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pseries_little_endian_exceptions();
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#endif
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} else {
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/* Set endian mode using OPAL */
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if (firmware_has_feature(FW_FEATURE_OPAL))
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opal_configure_cores();
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/* AIL on native is done in cpu_ready_for_interrupts() */
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}
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}
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static void cpu_ready_for_interrupts(void)
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{
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/*
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* Enable AIL if supported, and we are in hypervisor mode. This
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* is called once for every processor.
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*
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* If we are not in hypervisor mode the job is done once for
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* the whole partition in configure_exceptions().
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*/
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if (early_cpu_has_feature(CPU_FTR_HVMODE) &&
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early_cpu_has_feature(CPU_FTR_ARCH_207S)) {
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unsigned long lpcr = mfspr(SPRN_LPCR);
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mtspr(SPRN_LPCR, lpcr | LPCR_AIL_3);
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}
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/*
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* Fixup HFSCR:TM based on CPU features. The bit is set by our
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* early asm init because at that point we haven't updated our
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* CPU features from firmware and device-tree. Here we have,
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* so let's do it.
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*/
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if (cpu_has_feature(CPU_FTR_HVMODE) && !cpu_has_feature(CPU_FTR_TM_COMP))
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mtspr(SPRN_HFSCR, mfspr(SPRN_HFSCR) & ~HFSCR_TM);
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/* Set IR and DR in PACA MSR */
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get_paca()->kernel_msr = MSR_KERNEL;
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}
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/*
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* Early initialization entry point. This is called by head.S
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* with MMU translation disabled. We rely on the "feature" of
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* the CPU that ignores the top 2 bits of the address in real
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* mode so we can access kernel globals normally provided we
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* only toy with things in the RMO region. From here, we do
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* some early parsing of the device-tree to setup out MEMBLOCK
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* data structures, and allocate & initialize the hash table
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* and segment tables so we can start running with translation
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* enabled.
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*
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* It is this function which will call the probe() callback of
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* the various platform types and copy the matching one to the
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* global ppc_md structure. Your platform can eventually do
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* some very early initializations from the probe() routine, but
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* this is not recommended, be very careful as, for example, the
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* device-tree is not accessible via normal means at this point.
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*/
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void __init early_setup(unsigned long dt_ptr)
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{
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static __initdata struct paca_struct boot_paca;
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/* -------- printk is _NOT_ safe to use here ! ------- */
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/* Identify CPU type */
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identify_cpu(0, mfspr(SPRN_PVR));
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/* Assume we're on cpu 0 for now. Don't write to the paca yet! */
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initialise_paca(&boot_paca, 0);
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setup_paca(&boot_paca);
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fixup_boot_paca();
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/* -------- printk is now safe to use ------- */
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/* Enable early debugging if any specified (see udbg.h) */
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udbg_early_init();
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DBG(" -> early_setup(), dt_ptr: 0x%lx\n", dt_ptr);
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/*
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* Do early initialization using the flattened device
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* tree, such as retrieving the physical memory map or
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* calculating/retrieving the hash table size.
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*/
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early_init_devtree(__va(dt_ptr));
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/* Now we know the logical id of our boot cpu, setup the paca. */
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setup_paca(&paca[boot_cpuid]);
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fixup_boot_paca();
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/*
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* Configure exception handlers. This include setting up trampolines
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* if needed, setting exception endian mode, etc...
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*/
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configure_exceptions();
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/* Apply all the dynamic patching */
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apply_feature_fixups();
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setup_feature_keys();
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/* Initialize the hash table or TLB handling */
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early_init_mmu();
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/*
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* At this point, we can let interrupts switch to virtual mode
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* (the MMU has been setup), so adjust the MSR in the PACA to
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* have IR and DR set and enable AIL if it exists
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*/
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cpu_ready_for_interrupts();
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DBG(" <- early_setup()\n");
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#ifdef CONFIG_PPC_EARLY_DEBUG_BOOTX
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/*
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* This needs to be done *last* (after the above DBG() even)
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*
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* Right after we return from this function, we turn on the MMU
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* which means the real-mode access trick that btext does will
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* no longer work, it needs to switch to using a real MMU
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* mapping. This call will ensure that it does
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*/
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btext_map();
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#endif /* CONFIG_PPC_EARLY_DEBUG_BOOTX */
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}
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#ifdef CONFIG_SMP
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void early_setup_secondary(void)
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{
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/* Mark interrupts disabled in PACA */
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get_paca()->soft_enabled = 0;
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/* Initialize the hash table or TLB handling */
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early_init_mmu_secondary();
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/*
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* At this point, we can let interrupts switch to virtual mode
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* (the MMU has been setup), so adjust the MSR in the PACA to
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* have IR and DR set.
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*/
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cpu_ready_for_interrupts();
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}
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#endif /* CONFIG_SMP */
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#if defined(CONFIG_SMP) || defined(CONFIG_KEXEC_CORE)
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static bool use_spinloop(void)
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{
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if (!IS_ENABLED(CONFIG_PPC_BOOK3E))
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return true;
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/*
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* When book3e boots from kexec, the ePAPR spin table does
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* not get used.
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*/
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return of_property_read_bool(of_chosen, "linux,booted-from-kexec");
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}
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void smp_release_cpus(void)
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{
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unsigned long *ptr;
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int i;
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if (!use_spinloop())
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return;
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DBG(" -> smp_release_cpus()\n");
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/* All secondary cpus are spinning on a common spinloop, release them
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* all now so they can start to spin on their individual paca
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* spinloops. For non SMP kernels, the secondary cpus never get out
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* of the common spinloop.
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*/
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ptr = (unsigned long *)((unsigned long)&__secondary_hold_spinloop
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- PHYSICAL_START);
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*ptr = ppc_function_entry(generic_secondary_smp_init);
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/* And wait a bit for them to catch up */
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for (i = 0; i < 100000; i++) {
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mb();
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HMT_low();
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if (spinning_secondaries == 0)
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break;
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udelay(1);
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}
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DBG("spinning_secondaries = %d\n", spinning_secondaries);
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DBG(" <- smp_release_cpus()\n");
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}
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#endif /* CONFIG_SMP || CONFIG_KEXEC_CORE */
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/*
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* Initialize some remaining members of the ppc64_caches and systemcfg
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* structures
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* (at least until we get rid of them completely). This is mostly some
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* cache informations about the CPU that will be used by cache flush
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* routines and/or provided to userland
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*/
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static void init_cache_info(struct ppc_cache_info *info, u32 size, u32 lsize,
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u32 bsize, u32 sets)
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{
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info->size = size;
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info->sets = sets;
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info->line_size = lsize;
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info->block_size = bsize;
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info->log_block_size = __ilog2(bsize);
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if (bsize)
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info->blocks_per_page = PAGE_SIZE / bsize;
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else
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info->blocks_per_page = 0;
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if (sets == 0)
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info->assoc = 0xffff;
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else
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info->assoc = size / (sets * lsize);
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}
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static bool __init parse_cache_info(struct device_node *np,
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bool icache,
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struct ppc_cache_info *info)
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{
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static const char *ipropnames[] __initdata = {
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"i-cache-size",
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"i-cache-sets",
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"i-cache-block-size",
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"i-cache-line-size",
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};
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static const char *dpropnames[] __initdata = {
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"d-cache-size",
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"d-cache-sets",
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"d-cache-block-size",
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"d-cache-line-size",
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};
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const char **propnames = icache ? ipropnames : dpropnames;
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const __be32 *sizep, *lsizep, *bsizep, *setsp;
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u32 size, lsize, bsize, sets;
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bool success = true;
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size = 0;
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sets = -1u;
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lsize = bsize = cur_cpu_spec->dcache_bsize;
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sizep = of_get_property(np, propnames[0], NULL);
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if (sizep != NULL)
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size = be32_to_cpu(*sizep);
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setsp = of_get_property(np, propnames[1], NULL);
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if (setsp != NULL)
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sets = be32_to_cpu(*setsp);
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bsizep = of_get_property(np, propnames[2], NULL);
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lsizep = of_get_property(np, propnames[3], NULL);
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if (bsizep == NULL)
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bsizep = lsizep;
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if (lsizep != NULL)
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lsize = be32_to_cpu(*lsizep);
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if (bsizep != NULL)
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bsize = be32_to_cpu(*bsizep);
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if (sizep == NULL || bsizep == NULL || lsizep == NULL)
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success = false;
|
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|
|
/*
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|
* OF is weird .. it represents fully associative caches
|
|
* as "1 way" which doesn't make much sense and doesn't
|
|
* leave room for direct mapped. We'll assume that 0
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* in OF means direct mapped for that reason.
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*/
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if (sets == 1)
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sets = 0;
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else if (sets == 0)
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sets = 1;
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init_cache_info(info, size, lsize, bsize, sets);
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|
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return success;
|
|
}
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|
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void __init initialize_cache_info(void)
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|
{
|
|
struct device_node *cpu = NULL, *l2, *l3 = NULL;
|
|
u32 pvr;
|
|
|
|
DBG(" -> initialize_cache_info()\n");
|
|
|
|
/*
|
|
* All shipping POWER8 machines have a firmware bug that
|
|
* puts incorrect information in the device-tree. This will
|
|
* be (hopefully) fixed for future chips but for now hard
|
|
* code the values if we are running on one of these
|
|
*/
|
|
pvr = PVR_VER(mfspr(SPRN_PVR));
|
|
if (pvr == PVR_POWER8 || pvr == PVR_POWER8E ||
|
|
pvr == PVR_POWER8NVL) {
|
|
/* size lsize blk sets */
|
|
init_cache_info(&ppc64_caches.l1i, 0x8000, 128, 128, 32);
|
|
init_cache_info(&ppc64_caches.l1d, 0x10000, 128, 128, 64);
|
|
init_cache_info(&ppc64_caches.l2, 0x80000, 128, 0, 512);
|
|
init_cache_info(&ppc64_caches.l3, 0x800000, 128, 0, 8192);
|
|
} else
|
|
cpu = of_find_node_by_type(NULL, "cpu");
|
|
|
|
/*
|
|
* We're assuming *all* of the CPUs have the same
|
|
* d-cache and i-cache sizes... -Peter
|
|
*/
|
|
if (cpu) {
|
|
if (!parse_cache_info(cpu, false, &ppc64_caches.l1d))
|
|
DBG("Argh, can't find dcache properties !\n");
|
|
|
|
if (!parse_cache_info(cpu, true, &ppc64_caches.l1i))
|
|
DBG("Argh, can't find icache properties !\n");
|
|
|
|
/*
|
|
* Try to find the L2 and L3 if any. Assume they are
|
|
* unified and use the D-side properties.
|
|
*/
|
|
l2 = of_find_next_cache_node(cpu);
|
|
of_node_put(cpu);
|
|
if (l2) {
|
|
parse_cache_info(l2, false, &ppc64_caches.l2);
|
|
l3 = of_find_next_cache_node(l2);
|
|
of_node_put(l2);
|
|
}
|
|
if (l3) {
|
|
parse_cache_info(l3, false, &ppc64_caches.l3);
|
|
of_node_put(l3);
|
|
}
|
|
}
|
|
|
|
/* For use by binfmt_elf */
|
|
dcache_bsize = ppc64_caches.l1d.block_size;
|
|
icache_bsize = ppc64_caches.l1i.block_size;
|
|
|
|
DBG(" <- initialize_cache_info()\n");
|
|
}
|
|
|
|
/* This returns the limit below which memory accesses to the linear
|
|
* mapping are guarnateed not to cause a TLB or SLB miss. This is
|
|
* used to allocate interrupt or emergency stacks for which our
|
|
* exception entry path doesn't deal with being interrupted.
|
|
*/
|
|
static __init u64 safe_stack_limit(void)
|
|
{
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
/* Freescale BookE bolts the entire linear mapping */
|
|
if (mmu_has_feature(MMU_FTR_TYPE_FSL_E))
|
|
return linear_map_top;
|
|
/* Other BookE, we assume the first GB is bolted */
|
|
return 1ul << 30;
|
|
#else
|
|
/* BookS, the first segment is bolted */
|
|
if (mmu_has_feature(MMU_FTR_1T_SEGMENT))
|
|
return 1UL << SID_SHIFT_1T;
|
|
return 1UL << SID_SHIFT;
|
|
#endif
|
|
}
|
|
|
|
void __init irqstack_early_init(void)
|
|
{
|
|
u64 limit = safe_stack_limit();
|
|
unsigned int i;
|
|
|
|
/*
|
|
* Interrupt stacks must be in the first segment since we
|
|
* cannot afford to take SLB misses on them.
|
|
*/
|
|
for_each_possible_cpu(i) {
|
|
softirq_ctx[i] = (struct thread_info *)
|
|
__va(memblock_alloc_base(THREAD_SIZE,
|
|
THREAD_SIZE, limit));
|
|
hardirq_ctx[i] = (struct thread_info *)
|
|
__va(memblock_alloc_base(THREAD_SIZE,
|
|
THREAD_SIZE, limit));
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_PPC_BOOK3E
|
|
void __init exc_lvl_early_init(void)
|
|
{
|
|
unsigned int i;
|
|
unsigned long sp;
|
|
|
|
for_each_possible_cpu(i) {
|
|
sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
|
|
critirq_ctx[i] = (struct thread_info *)__va(sp);
|
|
paca[i].crit_kstack = __va(sp + THREAD_SIZE);
|
|
|
|
sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
|
|
dbgirq_ctx[i] = (struct thread_info *)__va(sp);
|
|
paca[i].dbg_kstack = __va(sp + THREAD_SIZE);
|
|
|
|
sp = memblock_alloc(THREAD_SIZE, THREAD_SIZE);
|
|
mcheckirq_ctx[i] = (struct thread_info *)__va(sp);
|
|
paca[i].mc_kstack = __va(sp + THREAD_SIZE);
|
|
}
|
|
|
|
if (cpu_has_feature(CPU_FTR_DEBUG_LVL_EXC))
|
|
patch_exception(0x040, exc_debug_debug_book3e);
|
|
}
|
|
#endif
|
|
|
|
/*
|
|
* Stack space used when we detect a bad kernel stack pointer, and
|
|
* early in SMP boots before relocation is enabled. Exclusive emergency
|
|
* stack for machine checks.
|
|
*/
|
|
void __init emergency_stack_init(void)
|
|
{
|
|
u64 limit;
|
|
unsigned int i;
|
|
|
|
/*
|
|
* Emergency stacks must be under 256MB, we cannot afford to take
|
|
* SLB misses on them. The ABI also requires them to be 128-byte
|
|
* aligned.
|
|
*
|
|
* Since we use these as temporary stacks during secondary CPU
|
|
* bringup, we need to get at them in real mode. This means they
|
|
* must also be within the RMO region.
|
|
*/
|
|
limit = min(safe_stack_limit(), ppc64_rma_size);
|
|
|
|
for_each_possible_cpu(i) {
|
|
struct thread_info *ti;
|
|
ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
|
|
klp_init_thread_info(ti);
|
|
paca[i].emergency_sp = (void *)ti + THREAD_SIZE;
|
|
|
|
#ifdef CONFIG_PPC_BOOK3S_64
|
|
/* emergency stack for machine check exception handling. */
|
|
ti = __va(memblock_alloc_base(THREAD_SIZE, THREAD_SIZE, limit));
|
|
klp_init_thread_info(ti);
|
|
paca[i].mc_emergency_sp = (void *)ti + THREAD_SIZE;
|
|
#endif
|
|
}
|
|
}
|
|
|
|
#ifdef CONFIG_SMP
|
|
#define PCPU_DYN_SIZE ()
|
|
|
|
static void * __init pcpu_fc_alloc(unsigned int cpu, size_t size, size_t align)
|
|
{
|
|
return __alloc_bootmem_node(NODE_DATA(cpu_to_node(cpu)), size, align,
|
|
__pa(MAX_DMA_ADDRESS));
|
|
}
|
|
|
|
static void __init pcpu_fc_free(void *ptr, size_t size)
|
|
{
|
|
free_bootmem(__pa(ptr), size);
|
|
}
|
|
|
|
static int pcpu_cpu_distance(unsigned int from, unsigned int to)
|
|
{
|
|
if (cpu_to_node(from) == cpu_to_node(to))
|
|
return LOCAL_DISTANCE;
|
|
else
|
|
return REMOTE_DISTANCE;
|
|
}
|
|
|
|
unsigned long __per_cpu_offset[NR_CPUS] __read_mostly;
|
|
EXPORT_SYMBOL(__per_cpu_offset);
|
|
|
|
void __init setup_per_cpu_areas(void)
|
|
{
|
|
const size_t dyn_size = PERCPU_MODULE_RESERVE + PERCPU_DYNAMIC_RESERVE;
|
|
size_t atom_size;
|
|
unsigned long delta;
|
|
unsigned int cpu;
|
|
int rc;
|
|
|
|
/*
|
|
* Linear mapping is one of 4K, 1M and 16M. For 4K, no need
|
|
* to group units. For larger mappings, use 1M atom which
|
|
* should be large enough to contain a number of units.
|
|
*/
|
|
if (mmu_linear_psize == MMU_PAGE_4K)
|
|
atom_size = PAGE_SIZE;
|
|
else
|
|
atom_size = 1 << 20;
|
|
|
|
rc = pcpu_embed_first_chunk(0, dyn_size, atom_size, pcpu_cpu_distance,
|
|
pcpu_fc_alloc, pcpu_fc_free);
|
|
if (rc < 0)
|
|
panic("cannot initialize percpu area (err=%d)", rc);
|
|
|
|
delta = (unsigned long)pcpu_base_addr - (unsigned long)__per_cpu_start;
|
|
for_each_possible_cpu(cpu) {
|
|
__per_cpu_offset[cpu] = delta + pcpu_unit_offsets[cpu];
|
|
paca[cpu].data_offset = __per_cpu_offset[cpu];
|
|
}
|
|
}
|
|
#endif
|
|
|
|
#ifdef CONFIG_MEMORY_HOTPLUG_SPARSE
|
|
unsigned long memory_block_size_bytes(void)
|
|
{
|
|
if (ppc_md.memory_block_size)
|
|
return ppc_md.memory_block_size();
|
|
|
|
return MIN_MEMORY_BLOCK_SIZE;
|
|
}
|
|
#endif
|
|
|
|
#if defined(CONFIG_PPC_INDIRECT_PIO) || defined(CONFIG_PPC_INDIRECT_MMIO)
|
|
struct ppc_pci_io ppc_pci_io;
|
|
EXPORT_SYMBOL(ppc_pci_io);
|
|
#endif
|
|
|
|
#ifdef CONFIG_HARDLOCKUP_DETECTOR
|
|
u64 hw_nmi_get_sample_period(int watchdog_thresh)
|
|
{
|
|
return ppc_proc_freq * watchdog_thresh;
|
|
}
|
|
|
|
/*
|
|
* The hardlockup detector breaks PMU event based branches and is likely
|
|
* to get false positives in KVM guests, so disable it by default.
|
|
*/
|
|
static int __init disable_hardlockup_detector(void)
|
|
{
|
|
hardlockup_detector_disable();
|
|
|
|
return 0;
|
|
}
|
|
early_initcall(disable_hardlockup_detector);
|
|
#endif
|