mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-03 07:38:10 +00:00
ddab5aed8e
All R-Car Gen3 clock drivers now obtain the values of the mode pins from the R-Car RST driver. Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be> Acked-by: Dirk Behme <dirk.behme@de.bosch.com> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
42 lines
1.1 KiB
C
42 lines
1.1 KiB
C
/*
|
|
* R-Car Gen3 Clock Pulse Generator
|
|
*
|
|
* Copyright (C) 2015-2016 Glider bvba
|
|
*
|
|
* This program is free software; you can redistribute it and/or modify
|
|
* it under the terms of the GNU General Public License as published by
|
|
* the Free Software Foundation; version 2 of the License.
|
|
*/
|
|
|
|
#ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
|
#define __CLK_RENESAS_RCAR_GEN3_CPG_H__
|
|
|
|
enum rcar_gen3_clk_types {
|
|
CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
|
|
CLK_TYPE_GEN3_PLL0,
|
|
CLK_TYPE_GEN3_PLL1,
|
|
CLK_TYPE_GEN3_PLL2,
|
|
CLK_TYPE_GEN3_PLL3,
|
|
CLK_TYPE_GEN3_PLL4,
|
|
CLK_TYPE_GEN3_SD,
|
|
CLK_TYPE_GEN3_R,
|
|
};
|
|
|
|
#define DEF_GEN3_SD(_name, _id, _parent, _offset) \
|
|
DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
|
|
|
|
struct rcar_gen3_cpg_pll_config {
|
|
unsigned int extal_div;
|
|
unsigned int pll1_mult;
|
|
unsigned int pll3_mult;
|
|
};
|
|
|
|
#define CPG_RCKCR 0x240
|
|
|
|
struct clk *rcar_gen3_cpg_clk_register(struct device *dev,
|
|
const struct cpg_core_clk *core, const struct cpg_mssr_info *info,
|
|
struct clk **clks, void __iomem *base);
|
|
int rcar_gen3_cpg_init(const struct rcar_gen3_cpg_pll_config *config,
|
|
unsigned int clk_extalr);
|
|
|
|
#endif
|