mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-10-02 23:27:06 +00:00
31a42c2f3b
The mux clocks don't always correctly take the new parent into account when the parent is updated while the clock is disabled. Set the update bit when enabling the clock to force an update of the mux. Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com> Link: https://lore.kernel.org/r/20210125170819.26130-3-laurent.pinchart@ideasonboard.com Reviewed-by: Weiyi Lu <weiyi.lu@mediatek.com> Signed-off-by: Stephen Boyd <sboyd@kernel.org>
77 lines
1.9 KiB
C
77 lines
1.9 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
|
|
/*
|
|
* Copyright (c) 2018 MediaTek Inc.
|
|
* Author: Owen Chen <owen.chen@mediatek.com>
|
|
*/
|
|
|
|
#ifndef __DRV_CLK_MTK_MUX_H
|
|
#define __DRV_CLK_MTK_MUX_H
|
|
|
|
#include <linux/clk-provider.h>
|
|
|
|
struct mtk_clk_mux {
|
|
struct clk_hw hw;
|
|
struct regmap *regmap;
|
|
const struct mtk_mux *data;
|
|
spinlock_t *lock;
|
|
bool reparent;
|
|
};
|
|
|
|
struct mtk_mux {
|
|
int id;
|
|
const char *name;
|
|
const char * const *parent_names;
|
|
unsigned int flags;
|
|
|
|
u32 mux_ofs;
|
|
u32 set_ofs;
|
|
u32 clr_ofs;
|
|
u32 upd_ofs;
|
|
|
|
u8 mux_shift;
|
|
u8 mux_width;
|
|
u8 gate_shift;
|
|
s8 upd_shift;
|
|
|
|
signed char num_parents;
|
|
};
|
|
|
|
#define GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
|
|
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
|
|
_gate, _upd_ofs, _upd, _flags) { \
|
|
.id = _id, \
|
|
.name = _name, \
|
|
.mux_ofs = _mux_ofs, \
|
|
.set_ofs = _mux_set_ofs, \
|
|
.clr_ofs = _mux_clr_ofs, \
|
|
.upd_ofs = _upd_ofs, \
|
|
.mux_shift = _shift, \
|
|
.mux_width = _width, \
|
|
.gate_shift = _gate, \
|
|
.upd_shift = _upd, \
|
|
.parent_names = _parents, \
|
|
.num_parents = ARRAY_SIZE(_parents), \
|
|
.flags = _flags, \
|
|
}
|
|
|
|
#define MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
|
|
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
|
|
_gate, _upd_ofs, _upd, _flags) \
|
|
GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, _mux_ofs, \
|
|
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
|
|
_gate, _upd_ofs, _upd, _flags) \
|
|
|
|
#define MUX_GATE_CLR_SET_UPD(_id, _name, _parents, _mux_ofs, \
|
|
_mux_set_ofs, _mux_clr_ofs, _shift, _width, \
|
|
_gate, _upd_ofs, _upd) \
|
|
MUX_GATE_CLR_SET_UPD_FLAGS(_id, _name, _parents, \
|
|
_mux_ofs, _mux_set_ofs, _mux_clr_ofs, _shift, \
|
|
_width, _gate, _upd_ofs, _upd, \
|
|
CLK_SET_RATE_PARENT)
|
|
|
|
int mtk_clk_register_muxes(const struct mtk_mux *muxes,
|
|
int num, struct device_node *node,
|
|
spinlock_t *lock,
|
|
struct clk_onecell_data *clk_data);
|
|
|
|
#endif /* __DRV_CLK_MTK_MUX_H */
|