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cf7b61073e
Add the DDR Sub-System Driveway Performance Monitoring Unit (PMU) driver support for Alibaba T-Head Yitian 710 SoC chip. Yitian supports DDR5/4 DRAM and targets cloud computing and HPC. Each PMU is registered as a device in /sys/bus/event_source/devices, and users can select event to monitor in each sub-channel, independently. For example, ali_drw_21000 and ali_drw_21080 are two PMU devices for two sub-channels of the same channel in die 0. And the PMU device of die 1 is prefixed with ali_drw_400XXXXX, e.g. ali_drw_40021000. Due to hardware limitation, one of DDRSS Driveway PMU overflow interrupt shares the same irq number with MPAM ERR_IRQ. To register DDRSS PMU and MPAM drivers successfully, add IRQF_SHARED flag. Signed-off-by: Shuai Xue <xueshuai@linux.alibaba.com> Co-developed-by: Hongbo Yao <yaohongbo@linux.alibaba.com> Signed-off-by: Hongbo Yao <yaohongbo@linux.alibaba.com> Co-developed-by: Neng Chen <nengchen@linux.alibaba.com> Signed-off-by: Neng Chen <nengchen@linux.alibaba.com> Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Reviewed-by: Baolin Wang <baolin.wang@linux.alibaba.com> Link: https://lore.kernel.org/r/20220818031822.38415-3-xueshuai@linux.alibaba.com Signed-off-by: Will Deacon <will@kernel.org>
23 lines
1 KiB
Makefile
23 lines
1 KiB
Makefile
# SPDX-License-Identifier: GPL-2.0
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obj-$(CONFIG_ARM_CCI_PMU) += arm-cci.o
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obj-$(CONFIG_ARM_CCN) += arm-ccn.o
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obj-$(CONFIG_ARM_CMN) += arm-cmn.o
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obj-$(CONFIG_ARM_DSU_PMU) += arm_dsu_pmu.o
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obj-$(CONFIG_ARM_PMU) += arm_pmu.o arm_pmu_platform.o
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obj-$(CONFIG_ARM_PMU_ACPI) += arm_pmu_acpi.o
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obj-$(CONFIG_ARM_SMMU_V3_PMU) += arm_smmuv3_pmu.o
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obj-$(CONFIG_FSL_IMX8_DDR_PMU) += fsl_imx8_ddr_perf.o
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obj-$(CONFIG_HISI_PMU) += hisilicon/
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obj-$(CONFIG_QCOM_L2_PMU) += qcom_l2_pmu.o
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obj-$(CONFIG_QCOM_L3_PMU) += qcom_l3_pmu.o
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obj-$(CONFIG_RISCV_PMU) += riscv_pmu.o
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obj-$(CONFIG_RISCV_PMU_LEGACY) += riscv_pmu_legacy.o
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obj-$(CONFIG_RISCV_PMU_SBI) += riscv_pmu_sbi.o
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obj-$(CONFIG_THUNDERX2_PMU) += thunderx2_pmu.o
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obj-$(CONFIG_XGENE_PMU) += xgene_pmu.o
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obj-$(CONFIG_ARM_SPE_PMU) += arm_spe_pmu.o
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obj-$(CONFIG_ARM_DMC620_PMU) += arm_dmc620_pmu.o
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obj-$(CONFIG_MARVELL_CN10K_TAD_PMU) += marvell_cn10k_tad_pmu.o
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obj-$(CONFIG_MARVELL_CN10K_DDR_PMU) += marvell_cn10k_ddr_pmu.o
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obj-$(CONFIG_APPLE_M1_CPU_PMU) += apple_m1_cpu_pmu.o
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obj-$(CONFIG_ALIBABA_UNCORE_DRW_PMU) += alibaba_uncore_drw_pmu.o
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