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linux-stable/drivers/reset/Kconfig
Linus Torvalds bdc753c7fc Here's the main clk pull request for this merge window. We have some 
late breaking reports that a patch series to rework clk rate range
 support broke boot on some devices, so I've left that branch out of this
 PR. Hopefully we can get to that next week, or punt on it and let it
 bake another cycle. That means we don't really have any changes to the
 core framework this time around besides a few typo fixes. Instead this
 is all clk driver updates and fixes.
 
 The usual suspects are here (again), with Qualcomm dominating the
 diffstat. We look to have gained support for quite a few new Qualcomm
 SoCs and Dmitry worked on updating many of the existing Qualcomm drivers
 to use clk_parent_data. After that we have MediaTek drivers getting some
 much needed updates, in particular to support GPU DVFS. There are also
 quite a few Samsung clk driver patches, but that's mostly because there
 was a maintainer change and so last release we missed some of those
 patches.
 
 Overall things look normal, but I'm slowly reviewing core framework code
 nowadays and that shows given the rate range patches had to be yanked
 last minute. Let's hope this situation changes soon.
 
 New Drivers:
  - Support for Renesas VersaClock7 clock generator family
  - Add Spreadtrum UMS512 SoC clk support
  - New clock drivers for MediaTek Helio X10 MT6795
  - Display clks for Qualcomm SM6115, SM8450
  - GPU clks for Qualcomm SC8280XP
  - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers
 
 Deleted Drivers:
  - Remove DaVinci DM644x and DM646x clk driver support
 
 Updates:
  - Convert Baikal-T1 CCU driver to platform driver
  - Split reset support out of primary Baikal-T1 CCU driver
  - Add some missing clks required for RPiVid Video Decoder on RaspberryPi
  - Mark PLLC critical on bcm2835
  - More devm helpers for fixed rate registration
  - Various PXA168 clk driver fixes
  - Add resets for MediaTek MT8195 PCIe and USB
  - Miscellaneous of_node_put() fixes
  - Nuke dt-bindings/clk path (again) by moving headers to dt-bindings/clock
  - Convert gpio-clk-gate binding to YAML
  - Various fixes to AMD/Xilinx Zynqmp clk driver
  - Graduate AMD/Xilinx "clocking wizard" driver from staging
  - Add missing DPI1_HDMI clock in MT8195 VDOSYS1
  - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
    - Fix GPU clock topology on MT8195
    - Propogate rate changes from GPU clock gate up the tree
    - Clock mux notifiers for GPU-related PLLs
  - Conversion of more "simple" drivers to mtk_clk_simple_probe()
  - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
  - Fixes to previous |struct clk| to |struct clk_hw| conversion on MediaTek
  - Shrink MT8192 clock driver by deduplicating clock parent lists
  - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
    clocks for i.MX8MP
  - Drop unnecessary newline in i.MX8MM dt-bindings
  - Add more MU1 and SAI clocks dt-bindings Ids
  - Introduce slice busy bit check for i.MX93 composite clock
  - Introduce white list bit check for i.MX93 composite clock
  - Add new i.MX93 clock gate
  - Add MU1 and MU2 clocks to i.MX93 clock provider
  - Add SAI IPG clocks to i.MX93 clock provider
  - add generic clocks for U(S)ART available on SAMA5D2 SoCs
  - reset controller support for Polarfire clocks
  - .round_rate and .set rate support for clk-mpfs
  - code cleanup for clk-mpfs
  - PLL support for PolarFire SoC's Clock Conditioning Circuitry
  - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car V4H
  - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
  - Add I2C clocks and resets on RZ/V2M
  - Document clock support for the RZ/Five SoC
  - mux-variant clock using the table variant to select parents
  - clock controller for the rv1126 soc
  - conversion of rk3128 to yaml and relicensing of the yaml bindings
    to gpl2+MIT (following dt-binding guildelines)
  - Exynos7885: add FSYS, TREX and MFC clock controllers
  - Exynos850: add IS and AUD (audio) clock controllers with bindings
  - ExynosAutov9: add FSYS clock controllers with bindings
  - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
    controllers, due to duplicated entries.  This is an acceptable ABI
    break: recently developed/added platform so without legacies, acked
    by known users/developers
  - ExynosAutov9: add few missing Peric 0/1 gates
  - ExynosAutov9: correct register offsets of few Peric 0/1 clocks
  - Minor code improvements (use of_device_get_match_data() helper, code
    style)
  - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as he
    already maintainers that architecture/platform
  - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving retention
    issues during suspend of USB on Qualcomm sc7180/sc7280 and SC8280XP
  - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
  - Qualcomm SDM660 SDCC1 moved to floor clk ops
  - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018 was
    added/fixed
  - The Qualcomm MSM8996 CPU clocks are updated with support for ACD
  - Support for Qualcomm SDM670 GCC and RPMh clks was added
  - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
    num_parents was done for many Qualcomm SoCs
  - Support for per-reset defined delay on Qualcomm was introduced
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "We have some late breaking reports that a patch series to rework clk
  rate range support broke boot on some devices, so I've left that
  branch out of this. Hopefully we can get to that next week, or punt on
  it and let it bake another cycle. That means we don't really have any
  changes to the core framework this time around besides a few typo
  fixes. Instead this is all clk driver updates and fixes.

  The usual suspects are here (again), with Qualcomm dominating the
  diffstat. We look to have gained support for quite a few new Qualcomm
  SoCs and Dmitry worked on updating many of the existing Qualcomm
  drivers to use clk_parent_data. After that we have MediaTek drivers
  getting some much needed updates, in particular to support GPU DVFS.
  There are also quite a few Samsung clk driver patches, but that's
  mostly because there was a maintainer change and so last release we
  missed some of those patches.

  Overall things look normal, but I'm slowly reviewing core framework
  code nowadays and that shows given the rate range patches had to be
  yanked last minute. Let's hope this situation changes soon.

  New Drivers:
   - Support for Renesas VersaClock7 clock generator family
   - Add Spreadtrum UMS512 SoC clk support
   - New clock drivers for MediaTek Helio X10 MT6795
   - Display clks for Qualcomm SM6115, SM8450
   - GPU clks for Qualcomm SC8280XP
   - Qualcomm MSM8909 and SM6375 global and SMD RPM clk drivers

  Deleted Drivers:
   - Remove DaVinci DM644x and DM646x clk driver support

  Updates:
   - Convert Baikal-T1 CCU driver to platform driver
   - Split reset support out of primary Baikal-T1 CCU driver
   - Add some missing clks required for RPiVid Video Decoder on
     RaspberryPi
   - Mark PLLC critical on bcm2835
   - More devm helpers for fixed rate registration
   - Various PXA168 clk driver fixes
   - Add resets for MediaTek MT8195 PCIe and USB
   - Miscellaneous of_node_put() fixes
   - Nuke dt-bindings/clk path (again) by moving headers to
     dt-bindings/clock
   - Convert gpio-clk-gate binding to YAML
   - Various fixes to AMD/Xilinx Zynqmp clk driver
   - Graduate AMD/Xilinx "clocking wizard" driver from staging
   - Add missing DPI1_HDMI clock in MT8195 VDOSYS1
   - Clock driver changes to support GPU DVFS on MT8183, MT8192, MT8195
   - Fix GPU clock topology on MT8195
   - Propogate rate changes from GPU clock gate up the tree
   - Clock mux notifiers for GPU-related PLLs
   - Conversion of more "simple" drivers to mtk_clk_simple_probe()
   - Hook up mtk_clk_simple_remove() for "simple" MT8192 clock drivers
   - Fixes to previous |struct clk| to |struct clk_hw| conversion on
     MediaTek
   - Shrink MT8192 clock driver by deduplicating clock parent lists
   - Change order between 'sim_enet_root_clk' and 'enet_qos_root_clk'
     clocks for i.MX8MP
   - Drop unnecessary newline in i.MX8MM dt-bindings
   - Add more MU1 and SAI clocks dt-bindings Ids
   - Introduce slice busy bit check for i.MX93 composite clock
   - Introduce white list bit check for i.MX93 composite clock
   - Add new i.MX93 clock gate
   - Add MU1 and MU2 clocks to i.MX93 clock provider
   - Add SAI IPG clocks to i.MX93 clock provider
   - add generic clocks for U(S)ART available on SAMA5D2 SoCs
   - reset controller support for Polarfire clocks
   - .round_rate and .set rate support for clk-mpfs
   - code cleanup for clk-mpfs
   - PLL support for PolarFire SoC's Clock Conditioning Circuitry
   - Add watchdog, I2C, pin control/GPIO, and Ethernet clocks on R-Car
     V4H
   - Add SDHI, Timer (CMT/TMU), and SPI (MSIOF) clocks on R-Car S4-8
   - Add I2C clocks and resets on RZ/V2M
   - Document clock support for the RZ/Five SoC
   - mux-variant clock using the table variant to select parents
   - clock controller for the rv1126 soc
   - conversion of rk3128 to yaml and relicensing of the yaml bindings
     to gpl2+MIT (following dt-binding guildelines)
   - Exynos7885: add FSYS, TREX and MFC clock controllers
   - Exynos850: add IS and AUD (audio) clock controllers with bindings
   - ExynosAutov9: add FSYS clock controllers with bindings
   - ExynosAutov9: correct clock IDs in bindings of Peric 0 and 1 clock
     controllers, due to duplicated entries. This is an acceptable ABI
     break: recently developed/added platform so without legacies, acked
     by known users/developers
   - ExynosAutov9: add few missing Peric 0/1 gates
   - ExynosAutov9: correct register offsets of few Peric 0/1 clocks
   - Minor code improvements (use of_device_get_match_data() helper,
     code style)
   - Add Krzysztof Kozlowski as co-maintainer of Samsung SoC clocks, as
     he already maintainers that architecture/platform
   - Keep Qualcomm GDSCs enabled when PWRSTS_RET flag is there, solving
     retention issues during suspend of USB on Qualcomm sc7180/sc7280
     and SC8280XP
   - Qualcomm SM6115 and QCM2260 are moved to reuse PLL configuration
   - Qualcomm SDM660 SDCC1 moved to floor clk ops
   - Support for the APCS PLLs for Qualcomm IPQ8064, IPQ8074 and IPQ6018
     was added/fixed
   - The Qualcomm MSM8996 CPU clocks are updated with support for ACD
   - Support for Qualcomm SDM670 GCC and RPMh clks was added
   - Transition to parent_data, parent_hws and use of ARRAY_SIZE() for
     num_parents was done for many Qualcomm SoCs
   - Support for per-reset defined delay on Qualcomm was introduced"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (283 commits)
  clk: qcom: gcc-sm6375: Ensure unsigned long type
  clk: qcom: gcc-sm6375: Remove unused variables
  clk: qcom: kpss-xcc: convert to parent data API
  clk: introduce (devm_)hw_register_mux_parent_data_table API
  clk: allow building lan966x as a module
  clk: clk-xgene: simplify if-if to if-else
  clk: ast2600: BCLK comes from EPLL
  clk: clocking-wizard: Depend on HAS_IOMEM
  clk: clocking-wizard: Use dev_err_probe() helper
  clk: nxp: fix typo in comment
  clk: pxa: add a check for the return value of kzalloc()
  clk: vc5: Add support for IDT/Renesas VersaClock 5P49V6975
  dt-bindings: clock: vc5: Add 5P49V6975
  clk: mvebu: armada-37xx-tbg: Remove the unneeded result variable
  clk: ti: dra7-atl: Fix reference leak in of_dra7_atl_clk_probe
  clk: Renesas versaclock7 ccf device driver
  dt-bindings: Renesas versaclock7 device tree bindings
  clk: ti: Balance of_node_get() calls for of_find_node_by_name()
  clk: imx: scu: fix memleak on platform_device_add() fails
  clk: vc5: Use regmap_{set,clear}_bits() where appropriate
  ...
2022-10-08 10:06:48 -07:00

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# SPDX-License-Identifier: GPL-2.0-only
config ARCH_HAS_RESET_CONTROLLER
bool
menuconfig RESET_CONTROLLER
bool "Reset Controller Support"
default y if ARCH_HAS_RESET_CONTROLLER
help
Generic Reset Controller support.
This framework is designed to abstract reset handling of devices
via GPIOs or SoC-internal reset controller modules.
If unsure, say no.
if RESET_CONTROLLER
config RESET_A10SR
tristate "Altera Arria10 System Resource Reset"
depends on MFD_ALTERA_A10SR || COMPILE_TEST
help
This option enables support for the external reset functions for
peripheral PHYs on the Altera Arria10 System Resource Chip.
config RESET_ATH79
bool "AR71xx Reset Driver" if COMPILE_TEST
default ATH79
help
This enables the ATH79 reset controller driver that supports the
AR71xx SoC reset controller.
config RESET_AXS10X
bool "AXS10x Reset Driver" if COMPILE_TEST
default ARC_PLAT_AXS10X
help
This enables the reset controller driver for AXS10x.
config RESET_BCM6345
bool "BCM6345 Reset Controller"
depends on BMIPS_GENERIC || COMPILE_TEST
default BMIPS_GENERIC
help
This enables the reset controller driver for BCM6345 SoCs.
config RESET_BERLIN
tristate "Berlin Reset Driver"
depends on ARCH_BERLIN || COMPILE_TEST
default m if ARCH_BERLIN
help
This enables the reset controller driver for Marvell Berlin SoCs.
config RESET_BRCMSTB
tristate "Broadcom STB reset controller"
depends on ARCH_BRCMSTB || COMPILE_TEST
default ARCH_BRCMSTB
help
This enables the reset controller driver for Broadcom STB SoCs using
a SUN_TOP_CTRL_SW_INIT style controller.
config RESET_BRCMSTB_RESCAL
tristate "Broadcom STB RESCAL reset controller"
depends on HAS_IOMEM
depends on ARCH_BRCMSTB || COMPILE_TEST
default ARCH_BRCMSTB
help
This enables the RESCAL reset controller for SATA, PCIe0, or PCIe1 on
BCM7216.
config RESET_HSDK
bool "Synopsys HSDK Reset Driver"
depends on HAS_IOMEM
depends on ARC_SOC_HSDK || COMPILE_TEST
help
This enables the reset controller driver for HSDK board.
config RESET_IMX7
tristate "i.MX7/8 Reset Driver"
depends on HAS_IOMEM
depends on SOC_IMX7D || (ARM64 && ARCH_MXC) || COMPILE_TEST
default y if SOC_IMX7D
select MFD_SYSCON
help
This enables the reset controller driver for i.MX7 SoCs.
config RESET_INTEL_GW
bool "Intel Reset Controller Driver"
depends on X86 || COMPILE_TEST
depends on OF && HAS_IOMEM
select REGMAP_MMIO
help
This enables the reset controller driver for Intel Gateway SoCs.
Say Y to control the reset signals provided by reset controller.
Otherwise, say N.
config RESET_K210
bool "Reset controller driver for Canaan Kendryte K210 SoC"
depends on (SOC_CANAAN || COMPILE_TEST) && OF
select MFD_SYSCON
default SOC_CANAAN
help
Support for the Canaan Kendryte K210 RISC-V SoC reset controller.
Say Y if you want to control reset signals provided by this
controller.
config RESET_LANTIQ
bool "Lantiq XWAY Reset Driver" if COMPILE_TEST
default SOC_TYPE_XWAY
help
This enables the reset controller driver for Lantiq / Intel XWAY SoCs.
config RESET_LPC18XX
bool "LPC18xx/43xx Reset Driver" if COMPILE_TEST
default ARCH_LPC18XX
help
This enables the reset controller driver for NXP LPC18xx/43xx SoCs.
config RESET_MCHP_SPARX5
bool "Microchip Sparx5 reset driver"
depends on ARCH_SPARX5 || SOC_LAN966 || COMPILE_TEST
default y if SPARX5_SWITCH
select MFD_SYSCON
help
This driver supports switch core reset for the Microchip Sparx5 SoC.
config RESET_MESON
tristate "Meson Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
default ARCH_MESON
help
This enables the reset driver for Amlogic Meson SoCs.
config RESET_MESON_AUDIO_ARB
tristate "Meson Audio Memory Arbiter Reset Driver"
depends on ARCH_MESON || COMPILE_TEST
help
This enables the reset driver for Audio Memory Arbiter of
Amlogic's A113 based SoCs
config RESET_NPCM
bool "NPCM BMC Reset Driver" if COMPILE_TEST
default ARCH_NPCM
help
This enables the reset controller driver for Nuvoton NPCM
BMC SoCs.
config RESET_OXNAS
bool
config RESET_PISTACHIO
bool "Pistachio Reset Driver"
depends on MIPS || COMPILE_TEST
help
This enables the reset driver for ImgTec Pistachio SoCs.
config RESET_POLARFIRE_SOC
bool "Microchip PolarFire SoC (MPFS) Reset Driver"
depends on AUXILIARY_BUS && MCHP_CLK_MPFS
default MCHP_CLK_MPFS
help
This driver supports peripheral reset for the Microchip PolarFire SoC
config RESET_QCOM_AOSS
tristate "Qcom AOSS Reset Driver"
depends on ARCH_QCOM || COMPILE_TEST
help
This enables the AOSS (always on subsystem) reset driver
for Qualcomm SDM845 SoCs. Say Y if you want to control
reset signals provided by AOSS for Modem, Venus, ADSP,
GPU, Camera, Wireless, Display subsystem. Otherwise, say N.
config RESET_QCOM_PDC
tristate "Qualcomm PDC Reset Driver"
depends on ARCH_QCOM || COMPILE_TEST
help
This enables the PDC (Power Domain Controller) reset driver
for Qualcomm Technologies Inc SDM845 SoCs. Say Y if you want
to control reset signals provided by PDC for Modem, Compute,
Display, GPU, Debug, AOP, Sensors, Audio, SP and APPS.
config RESET_RASPBERRYPI
tristate "Raspberry Pi 4 Firmware Reset Driver"
depends on RASPBERRYPI_FIRMWARE || (RASPBERRYPI_FIRMWARE=n && COMPILE_TEST)
default USB_XHCI_PCI
help
Raspberry Pi 4's co-processor controls some of the board's HW
initialization process, but it's up to Linux to trigger it when
relevant. This driver provides a reset controller capable of
interfacing with RPi4's co-processor and model these firmware
initialization routines as reset lines.
config RESET_RZG2L_USBPHY_CTRL
tristate "Renesas RZ/G2L USBPHY control driver"
depends on ARCH_RZG2L || COMPILE_TEST
help
Support for USBPHY Control found on RZ/G2L family. It mainly
controls reset and power down of the USB/PHY.
config RESET_SCMI
tristate "Reset driver controlled via ARM SCMI interface"
depends on ARM_SCMI_PROTOCOL || COMPILE_TEST
default ARM_SCMI_PROTOCOL
help
This driver provides support for reset signal/domains that are
controlled by firmware that implements the SCMI interface.
This driver uses SCMI Message Protocol to interact with the
firmware controlling all the reset signals.
config RESET_SIMPLE
bool "Simple Reset Controller Driver" if COMPILE_TEST || EXPERT
default ARCH_ASPEED || ARCH_BCMBCA || ARCH_BITMAIN || ARCH_REALTEK || ARCH_STM32 || (ARCH_INTEL_SOCFPGA && ARM64) || ARCH_SUNXI || ARC
depends on HAS_IOMEM
help
This enables a simple reset controller driver for reset lines that
that can be asserted and deasserted by toggling bits in a contiguous,
exclusive register space.
Currently this driver supports:
- Altera SoCFPGAs
- ASPEED BMC SoCs
- Bitmain BM1880 SoC
- Realtek SoCs
- RCC reset controller in STM32 MCUs
- Allwinner SoCs
- SiFive FU740 SoCs
config RESET_SOCFPGA
bool "SoCFPGA Reset Driver" if COMPILE_TEST && (!ARM || !ARCH_INTEL_SOCFPGA)
default ARM && ARCH_INTEL_SOCFPGA
select RESET_SIMPLE
help
This enables the reset driver for the SoCFPGA ARMv7 platforms. This
driver gets initialized early during platform init calls.
config RESET_STARFIVE_JH7100
bool "StarFive JH7100 Reset Driver"
depends on SOC_STARFIVE || COMPILE_TEST
default SOC_STARFIVE
help
This enables the reset controller driver for the StarFive JH7100 SoC.
config RESET_SUNPLUS
bool "Sunplus SoCs Reset Driver" if COMPILE_TEST
default ARCH_SUNPLUS
help
This enables the reset driver support for Sunplus SoCs.
The reset lines that can be asserted and deasserted by toggling bits
in a contiguous, exclusive register space. The register is HIWORD_MASKED,
which means each register holds 16 reset lines.
config RESET_SUNXI
bool "Allwinner SoCs Reset Driver" if COMPILE_TEST && !ARCH_SUNXI
default ARCH_SUNXI
select RESET_SIMPLE
help
This enables the reset driver for Allwinner SoCs.
config RESET_TI_SCI
tristate "TI System Control Interface (TI-SCI) reset driver"
depends on TI_SCI_PROTOCOL || COMPILE_TEST
help
This enables the reset driver support over TI System Control Interface
available on some new TI's SoCs. If you wish to use reset resources
managed by the TI System Controller, say Y here. Otherwise, say N.
config RESET_TI_SYSCON
tristate "TI SYSCON Reset Driver"
depends on HAS_IOMEM
select MFD_SYSCON
help
This enables the reset driver support for TI devices with
memory-mapped reset registers as part of a syscon device node. If
you wish to use the reset framework for such memory-mapped devices,
say Y here. Otherwise, say N.
config RESET_TI_TPS380X
tristate "TI TPS380x Reset Driver"
select GPIOLIB
help
This enables the reset driver support for TI TPS380x devices. If
you wish to use the reset framework for such devices, say Y here.
Otherwise, say N.
config RESET_TN48M_CPLD
tristate "Delta Networks TN48M switch CPLD reset controller"
depends on MFD_TN48M_CPLD || COMPILE_TEST
default MFD_TN48M_CPLD
help
This enables the reset controller driver for the Delta TN48M CPLD.
It provides reset signals for Armada 7040 and 385 SoC-s, Alleycat 3X
switch MAC-s, Alaska OOB ethernet PHY, Quad Alaska ethernet PHY-s and
Microchip PD69200 PoE PSE controller.
This driver can also be built as a module. If so, the module will be
called reset-tn48m.
config RESET_UNIPHIER
tristate "Reset controller driver for UniPhier SoCs"
depends on ARCH_UNIPHIER || COMPILE_TEST
depends on OF && MFD_SYSCON
default ARCH_UNIPHIER
help
Support for reset controllers on UniPhier SoCs.
Say Y if you want to control reset signals provided by System Control
block, Media I/O block, Peripheral Block.
config RESET_UNIPHIER_GLUE
tristate "Reset driver in glue layer for UniPhier SoCs"
depends on (ARCH_UNIPHIER || COMPILE_TEST) && OF
default ARCH_UNIPHIER
select RESET_SIMPLE
help
Support for peripheral core reset included in its own glue layer
on UniPhier SoCs. Say Y if you want to control reset signals
provided by the glue layer.
config RESET_ZYNQ
bool "ZYNQ Reset Driver" if COMPILE_TEST
default ARCH_ZYNQ
help
This enables the reset controller driver for Xilinx Zynq SoCs.
source "drivers/reset/sti/Kconfig"
source "drivers/reset/hisilicon/Kconfig"
source "drivers/reset/tegra/Kconfig"
endif
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