mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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3084b48fa1
Here we configure TMU mode to HiFi uni-directional once DP tunnel is created. This is due to accuracy requirement for DP tunneling as appears in CM guide 1.0, section 7.3.2. Due to Intel hardware limitation, once we changed the TMU mode to HiFi uni-directional (when DP tunnel exists), we don't change TMU mode back to normal uni-directional, even if DP tunnel is torn down later. Signed-off-by: Gil Fine <gil.fine@intel.com> Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
773 lines
19 KiB
C
773 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Thunderbolt Time Management Unit (TMU) support
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*
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* Copyright (C) 2019, Intel Corporation
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* Authors: Mika Westerberg <mika.westerberg@linux.intel.com>
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* Rajmohan Mani <rajmohan.mani@intel.com>
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*/
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#include <linux/delay.h>
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#include "tb.h"
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static int tb_switch_set_tmu_mode_params(struct tb_switch *sw,
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enum tb_switch_tmu_rate rate)
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{
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u32 freq_meas_wind[2] = { 30, 800 };
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u32 avg_const[2] = { 4, 8 };
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u32 freq, avg, val;
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int ret;
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if (rate == TB_SWITCH_TMU_RATE_NORMAL) {
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freq = freq_meas_wind[0];
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avg = avg_const[0];
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} else if (rate == TB_SWITCH_TMU_RATE_HIFI) {
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freq = freq_meas_wind[1];
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avg = avg_const[1];
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} else {
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return 0;
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}
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_0, 1);
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if (ret)
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return ret;
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val &= ~TMU_RTR_CS_0_FREQ_WIND_MASK;
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val |= FIELD_PREP(TMU_RTR_CS_0_FREQ_WIND_MASK, freq);
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ret = tb_sw_write(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_0, 1);
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if (ret)
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return ret;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_15, 1);
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if (ret)
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return ret;
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val &= ~TMU_RTR_CS_15_FREQ_AVG_MASK &
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~TMU_RTR_CS_15_DELAY_AVG_MASK &
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~TMU_RTR_CS_15_OFFSET_AVG_MASK &
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~TMU_RTR_CS_15_ERROR_AVG_MASK;
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val |= FIELD_PREP(TMU_RTR_CS_15_FREQ_AVG_MASK, avg) |
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FIELD_PREP(TMU_RTR_CS_15_DELAY_AVG_MASK, avg) |
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FIELD_PREP(TMU_RTR_CS_15_OFFSET_AVG_MASK, avg) |
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FIELD_PREP(TMU_RTR_CS_15_ERROR_AVG_MASK, avg);
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return tb_sw_write(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_15, 1);
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}
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static const char *tb_switch_tmu_mode_name(const struct tb_switch *sw)
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{
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bool root_switch = !tb_route(sw);
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switch (sw->tmu.rate) {
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case TB_SWITCH_TMU_RATE_OFF:
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return "off";
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case TB_SWITCH_TMU_RATE_HIFI:
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/* Root switch does not have upstream directionality */
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if (root_switch)
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return "HiFi";
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if (sw->tmu.unidirectional)
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return "uni-directional, HiFi";
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return "bi-directional, HiFi";
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case TB_SWITCH_TMU_RATE_NORMAL:
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if (root_switch)
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return "normal";
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return "uni-directional, normal";
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default:
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return "unknown";
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}
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}
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static bool tb_switch_tmu_ucap_supported(struct tb_switch *sw)
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{
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int ret;
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u32 val;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_0, 1);
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if (ret)
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return false;
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return !!(val & TMU_RTR_CS_0_UCAP);
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}
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static int tb_switch_tmu_rate_read(struct tb_switch *sw)
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{
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int ret;
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u32 val;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_3, 1);
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if (ret)
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return ret;
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val >>= TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT;
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return val;
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}
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static int tb_switch_tmu_rate_write(struct tb_switch *sw, int rate)
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{
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int ret;
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u32 val;
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_3, 1);
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if (ret)
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return ret;
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val &= ~TMU_RTR_CS_3_TS_PACKET_INTERVAL_MASK;
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val |= rate << TMU_RTR_CS_3_TS_PACKET_INTERVAL_SHIFT;
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return tb_sw_write(sw, &val, TB_CFG_SWITCH,
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sw->tmu.cap + TMU_RTR_CS_3, 1);
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}
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static int tb_port_tmu_write(struct tb_port *port, u8 offset, u32 mask,
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u32 value)
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{
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u32 data;
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int ret;
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ret = tb_port_read(port, &data, TB_CFG_PORT, port->cap_tmu + offset, 1);
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if (ret)
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return ret;
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data &= ~mask;
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data |= value;
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return tb_port_write(port, &data, TB_CFG_PORT,
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port->cap_tmu + offset, 1);
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}
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static int tb_port_tmu_set_unidirectional(struct tb_port *port,
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bool unidirectional)
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{
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u32 val;
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if (!port->sw->tmu.has_ucap)
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return 0;
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val = unidirectional ? TMU_ADP_CS_3_UDM : 0;
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return tb_port_tmu_write(port, TMU_ADP_CS_3, TMU_ADP_CS_3_UDM, val);
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}
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static inline int tb_port_tmu_unidirectional_disable(struct tb_port *port)
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{
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return tb_port_tmu_set_unidirectional(port, false);
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}
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static inline int tb_port_tmu_unidirectional_enable(struct tb_port *port)
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{
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return tb_port_tmu_set_unidirectional(port, true);
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}
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static bool tb_port_tmu_is_unidirectional(struct tb_port *port)
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{
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int ret;
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u32 val;
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ret = tb_port_read(port, &val, TB_CFG_PORT,
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port->cap_tmu + TMU_ADP_CS_3, 1);
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if (ret)
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return false;
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return val & TMU_ADP_CS_3_UDM;
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}
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static int tb_port_tmu_time_sync(struct tb_port *port, bool time_sync)
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{
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u32 val = time_sync ? TMU_ADP_CS_6_DTS : 0;
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return tb_port_tmu_write(port, TMU_ADP_CS_6, TMU_ADP_CS_6_DTS, val);
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}
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static int tb_port_tmu_time_sync_disable(struct tb_port *port)
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{
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return tb_port_tmu_time_sync(port, true);
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}
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static int tb_port_tmu_time_sync_enable(struct tb_port *port)
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{
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return tb_port_tmu_time_sync(port, false);
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}
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static int tb_switch_tmu_set_time_disruption(struct tb_switch *sw, bool set)
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{
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u32 val, offset, bit;
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int ret;
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if (tb_switch_is_usb4(sw)) {
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offset = sw->tmu.cap + TMU_RTR_CS_0;
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bit = TMU_RTR_CS_0_TD;
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} else {
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offset = sw->cap_vsec_tmu + TB_TIME_VSEC_3_CS_26;
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bit = TB_TIME_VSEC_3_CS_26_TD;
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}
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ret = tb_sw_read(sw, &val, TB_CFG_SWITCH, offset, 1);
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if (ret)
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return ret;
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if (set)
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val |= bit;
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else
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val &= ~bit;
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return tb_sw_write(sw, &val, TB_CFG_SWITCH, offset, 1);
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}
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/**
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* tb_switch_tmu_init() - Initialize switch TMU structures
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* @sw: Switch to initialized
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*
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* This function must be called before other TMU related functions to
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* makes the internal structures are filled in correctly. Does not
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* change any hardware configuration.
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*/
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int tb_switch_tmu_init(struct tb_switch *sw)
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{
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struct tb_port *port;
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int ret;
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if (tb_switch_is_icm(sw))
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return 0;
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ret = tb_switch_find_cap(sw, TB_SWITCH_CAP_TMU);
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if (ret > 0)
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sw->tmu.cap = ret;
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tb_switch_for_each_port(sw, port) {
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int cap;
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cap = tb_port_find_cap(port, TB_PORT_CAP_TIME1);
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if (cap > 0)
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port->cap_tmu = cap;
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}
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ret = tb_switch_tmu_rate_read(sw);
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if (ret < 0)
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return ret;
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sw->tmu.rate = ret;
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sw->tmu.has_ucap = tb_switch_tmu_ucap_supported(sw);
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if (sw->tmu.has_ucap) {
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tb_sw_dbg(sw, "TMU: supports uni-directional mode\n");
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if (tb_route(sw)) {
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struct tb_port *up = tb_upstream_port(sw);
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sw->tmu.unidirectional =
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tb_port_tmu_is_unidirectional(up);
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}
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} else {
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sw->tmu.unidirectional = false;
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}
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tb_sw_dbg(sw, "TMU: current mode: %s\n", tb_switch_tmu_mode_name(sw));
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return 0;
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}
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/**
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* tb_switch_tmu_post_time() - Update switch local time
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* @sw: Switch whose time to update
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*
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* Updates switch local time using time posting procedure.
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*/
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int tb_switch_tmu_post_time(struct tb_switch *sw)
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{
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unsigned int post_time_high_offset, post_time_high = 0;
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unsigned int post_local_time_offset, post_time_offset;
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struct tb_switch *root_switch = sw->tb->root_switch;
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u64 hi, mid, lo, local_time, post_time;
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int i, ret, retries = 100;
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u32 gm_local_time[3];
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if (!tb_route(sw))
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return 0;
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if (!tb_switch_is_usb4(sw))
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return 0;
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/* Need to be able to read the grand master time */
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if (!root_switch->tmu.cap)
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return 0;
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ret = tb_sw_read(root_switch, gm_local_time, TB_CFG_SWITCH,
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root_switch->tmu.cap + TMU_RTR_CS_1,
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ARRAY_SIZE(gm_local_time));
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if (ret)
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return ret;
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for (i = 0; i < ARRAY_SIZE(gm_local_time); i++)
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tb_sw_dbg(root_switch, "local_time[%d]=0x%08x\n", i,
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gm_local_time[i]);
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/* Convert to nanoseconds (drop fractional part) */
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hi = gm_local_time[2] & TMU_RTR_CS_3_LOCAL_TIME_NS_MASK;
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mid = gm_local_time[1];
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lo = (gm_local_time[0] & TMU_RTR_CS_1_LOCAL_TIME_NS_MASK) >>
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TMU_RTR_CS_1_LOCAL_TIME_NS_SHIFT;
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local_time = hi << 48 | mid << 16 | lo;
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/* Tell the switch that time sync is disrupted for a while */
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ret = tb_switch_tmu_set_time_disruption(sw, true);
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if (ret)
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return ret;
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post_local_time_offset = sw->tmu.cap + TMU_RTR_CS_22;
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post_time_offset = sw->tmu.cap + TMU_RTR_CS_24;
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post_time_high_offset = sw->tmu.cap + TMU_RTR_CS_25;
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/*
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* Write the Grandmaster time to the Post Local Time registers
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* of the new switch.
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*/
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ret = tb_sw_write(sw, &local_time, TB_CFG_SWITCH,
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post_local_time_offset, 2);
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if (ret)
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goto out;
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/*
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* Have the new switch update its local time by:
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* 1) writing 0x1 to the Post Time Low register and 0xffffffff to
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* Post Time High register.
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* 2) write 0 to Post Time High register and then wait for
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* the completion of the post_time register becomes 0.
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* This means the time has been converged properly.
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*/
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post_time = 0xffffffff00000001ULL;
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ret = tb_sw_write(sw, &post_time, TB_CFG_SWITCH, post_time_offset, 2);
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if (ret)
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goto out;
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ret = tb_sw_write(sw, &post_time_high, TB_CFG_SWITCH,
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post_time_high_offset, 1);
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if (ret)
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goto out;
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do {
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usleep_range(5, 10);
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ret = tb_sw_read(sw, &post_time, TB_CFG_SWITCH,
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post_time_offset, 2);
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if (ret)
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goto out;
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} while (--retries && post_time);
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if (!retries) {
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ret = -ETIMEDOUT;
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goto out;
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}
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tb_sw_dbg(sw, "TMU: updated local time to %#llx\n", local_time);
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out:
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tb_switch_tmu_set_time_disruption(sw, false);
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return ret;
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}
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/**
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* tb_switch_tmu_disable() - Disable TMU of a switch
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* @sw: Switch whose TMU to disable
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*
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* Turns off TMU of @sw if it is enabled. If not enabled does nothing.
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*/
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int tb_switch_tmu_disable(struct tb_switch *sw)
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{
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/*
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* No need to disable TMU on devices that don't support CLx since
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* on these devices e.g. Alpine Ridge and earlier, the TMU mode
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* HiFi bi-directional is enabled by default and we don't change it.
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*/
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if (!tb_switch_is_clx_supported(sw))
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return 0;
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/* Already disabled? */
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if (sw->tmu.rate == TB_SWITCH_TMU_RATE_OFF)
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return 0;
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if (tb_route(sw)) {
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bool unidirectional = sw->tmu.unidirectional;
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struct tb_switch *parent = tb_switch_parent(sw);
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struct tb_port *down, *up;
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int ret;
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down = tb_port_at(tb_route(sw), parent);
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up = tb_upstream_port(sw);
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/*
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* In case of uni-directional time sync, TMU handshake is
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* initiated by upstream router. In case of bi-directional
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* time sync, TMU handshake is initiated by downstream router.
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* We change downstream router's rate to off for both uni/bidir
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* cases although it is needed only for the bi-directional mode.
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* We avoid changing upstream router's mode since it might
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* have another downstream router plugged, that is set to
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* uni-directional mode and we don't want to change it's TMU
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* mode.
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*/
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tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_OFF);
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tb_port_tmu_time_sync_disable(up);
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ret = tb_port_tmu_time_sync_disable(down);
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if (ret)
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return ret;
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if (unidirectional) {
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/* The switch may be unplugged so ignore any errors */
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tb_port_tmu_unidirectional_disable(up);
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ret = tb_port_tmu_unidirectional_disable(down);
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if (ret)
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return ret;
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}
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} else {
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tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_OFF);
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}
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sw->tmu.unidirectional = false;
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sw->tmu.rate = TB_SWITCH_TMU_RATE_OFF;
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tb_sw_dbg(sw, "TMU: disabled\n");
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return 0;
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}
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static void __tb_switch_tmu_off(struct tb_switch *sw, bool unidirectional)
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{
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struct tb_switch *parent = tb_switch_parent(sw);
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struct tb_port *down, *up;
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down = tb_port_at(tb_route(sw), parent);
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up = tb_upstream_port(sw);
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/*
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* In case of any failure in one of the steps when setting
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* bi-directional or uni-directional TMU mode, get back to the TMU
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* configurations in off mode. In case of additional failures in
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* the functions below, ignore them since the caller shall already
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* report a failure.
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*/
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tb_port_tmu_time_sync_disable(down);
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tb_port_tmu_time_sync_disable(up);
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if (unidirectional)
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tb_switch_tmu_rate_write(parent, TB_SWITCH_TMU_RATE_OFF);
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else
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tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_OFF);
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tb_switch_set_tmu_mode_params(sw, sw->tmu.rate);
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tb_port_tmu_unidirectional_disable(down);
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tb_port_tmu_unidirectional_disable(up);
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}
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/*
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* This function is called when the previous TMU mode was
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* TB_SWITCH_TMU_RATE_OFF.
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*/
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static int __tb_switch_tmu_enable_bidirectional(struct tb_switch *sw)
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{
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struct tb_switch *parent = tb_switch_parent(sw);
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struct tb_port *up, *down;
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int ret;
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up = tb_upstream_port(sw);
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down = tb_port_at(tb_route(sw), parent);
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ret = tb_port_tmu_unidirectional_disable(up);
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if (ret)
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return ret;
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ret = tb_port_tmu_unidirectional_disable(down);
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if (ret)
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goto out;
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|
|
|
ret = tb_switch_tmu_rate_write(sw, TB_SWITCH_TMU_RATE_HIFI);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = tb_port_tmu_time_sync_enable(up);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = tb_port_tmu_time_sync_enable(down);
|
|
if (ret)
|
|
goto out;
|
|
|
|
return 0;
|
|
|
|
out:
|
|
__tb_switch_tmu_off(sw, false);
|
|
return ret;
|
|
}
|
|
|
|
static int tb_switch_tmu_objection_mask(struct tb_switch *sw)
|
|
{
|
|
u32 val;
|
|
int ret;
|
|
|
|
ret = tb_sw_read(sw, &val, TB_CFG_SWITCH,
|
|
sw->cap_vsec_tmu + TB_TIME_VSEC_3_CS_9, 1);
|
|
if (ret)
|
|
return ret;
|
|
|
|
val &= ~TB_TIME_VSEC_3_CS_9_TMU_OBJ_MASK;
|
|
|
|
return tb_sw_write(sw, &val, TB_CFG_SWITCH,
|
|
sw->cap_vsec_tmu + TB_TIME_VSEC_3_CS_9, 1);
|
|
}
|
|
|
|
static int tb_switch_tmu_unidirectional_enable(struct tb_switch *sw)
|
|
{
|
|
struct tb_port *up = tb_upstream_port(sw);
|
|
|
|
return tb_port_tmu_write(up, TMU_ADP_CS_6,
|
|
TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK,
|
|
TMU_ADP_CS_6_DISABLE_TMU_OBJ_MASK);
|
|
}
|
|
|
|
/*
|
|
* This function is called when the previous TMU mode was
|
|
* TB_SWITCH_TMU_RATE_OFF.
|
|
*/
|
|
static int __tb_switch_tmu_enable_unidirectional(struct tb_switch *sw)
|
|
{
|
|
struct tb_switch *parent = tb_switch_parent(sw);
|
|
struct tb_port *up, *down;
|
|
int ret;
|
|
|
|
up = tb_upstream_port(sw);
|
|
down = tb_port_at(tb_route(sw), parent);
|
|
ret = tb_switch_tmu_rate_write(parent, sw->tmu.rate_request);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = tb_switch_set_tmu_mode_params(sw, sw->tmu.rate_request);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = tb_port_tmu_unidirectional_enable(up);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = tb_port_tmu_time_sync_enable(up);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = tb_port_tmu_unidirectional_enable(down);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = tb_port_tmu_time_sync_enable(down);
|
|
if (ret)
|
|
goto out;
|
|
|
|
return 0;
|
|
|
|
out:
|
|
__tb_switch_tmu_off(sw, true);
|
|
return ret;
|
|
}
|
|
|
|
static void __tb_switch_tmu_change_mode_prev(struct tb_switch *sw)
|
|
{
|
|
struct tb_switch *parent = tb_switch_parent(sw);
|
|
struct tb_port *down, *up;
|
|
|
|
down = tb_port_at(tb_route(sw), parent);
|
|
up = tb_upstream_port(sw);
|
|
/*
|
|
* In case of any failure in one of the steps when change mode,
|
|
* get back to the TMU configurations in previous mode.
|
|
* In case of additional failures in the functions below,
|
|
* ignore them since the caller shall already report a failure.
|
|
*/
|
|
tb_port_tmu_set_unidirectional(down, sw->tmu.unidirectional);
|
|
if (sw->tmu.unidirectional_request)
|
|
tb_switch_tmu_rate_write(parent, sw->tmu.rate);
|
|
else
|
|
tb_switch_tmu_rate_write(sw, sw->tmu.rate);
|
|
|
|
tb_switch_set_tmu_mode_params(sw, sw->tmu.rate);
|
|
tb_port_tmu_set_unidirectional(up, sw->tmu.unidirectional);
|
|
}
|
|
|
|
static int __tb_switch_tmu_change_mode(struct tb_switch *sw)
|
|
{
|
|
struct tb_switch *parent = tb_switch_parent(sw);
|
|
struct tb_port *up, *down;
|
|
int ret;
|
|
|
|
up = tb_upstream_port(sw);
|
|
down = tb_port_at(tb_route(sw), parent);
|
|
ret = tb_port_tmu_set_unidirectional(down, sw->tmu.unidirectional_request);
|
|
if (ret)
|
|
goto out;
|
|
|
|
if (sw->tmu.unidirectional_request)
|
|
ret = tb_switch_tmu_rate_write(parent, sw->tmu.rate_request);
|
|
else
|
|
ret = tb_switch_tmu_rate_write(sw, sw->tmu.rate_request);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = tb_switch_set_tmu_mode_params(sw, sw->tmu.rate_request);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = tb_port_tmu_set_unidirectional(up, sw->tmu.unidirectional_request);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = tb_port_tmu_time_sync_enable(down);
|
|
if (ret)
|
|
goto out;
|
|
|
|
ret = tb_port_tmu_time_sync_enable(up);
|
|
if (ret)
|
|
goto out;
|
|
|
|
return 0;
|
|
|
|
out:
|
|
__tb_switch_tmu_change_mode_prev(sw);
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* tb_switch_tmu_enable() - Enable TMU on a router
|
|
* @sw: Router whose TMU to enable
|
|
*
|
|
* Enables TMU of a router to be in uni-directional Normal/HiFi
|
|
* or bi-directional HiFi mode. Calling tb_switch_tmu_configure() is required
|
|
* before calling this function, to select the mode Normal/HiFi and
|
|
* directionality (uni-directional/bi-directional).
|
|
* In HiFi mode all tunneling should work. In Normal mode, DP tunneling can't
|
|
* work. Uni-directional mode is required for CLx (Link Low-Power) to work.
|
|
*/
|
|
int tb_switch_tmu_enable(struct tb_switch *sw)
|
|
{
|
|
bool unidirectional = sw->tmu.unidirectional_request;
|
|
int ret;
|
|
|
|
if (unidirectional && !sw->tmu.has_ucap)
|
|
return -EOPNOTSUPP;
|
|
|
|
/*
|
|
* No need to enable TMU on devices that don't support CLx since on
|
|
* these devices e.g. Alpine Ridge and earlier, the TMU mode HiFi
|
|
* bi-directional is enabled by default.
|
|
*/
|
|
if (!tb_switch_is_clx_supported(sw))
|
|
return 0;
|
|
|
|
if (tb_switch_tmu_is_enabled(sw, sw->tmu.unidirectional_request))
|
|
return 0;
|
|
|
|
if (tb_switch_is_titan_ridge(sw) && unidirectional) {
|
|
/*
|
|
* Titan Ridge supports CL0s and CL1 only. CL0s and CL1 are
|
|
* enabled and supported together.
|
|
*/
|
|
if (!tb_switch_is_clx_enabled(sw, TB_CL1))
|
|
return -EOPNOTSUPP;
|
|
|
|
ret = tb_switch_tmu_objection_mask(sw);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = tb_switch_tmu_unidirectional_enable(sw);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
ret = tb_switch_tmu_set_time_disruption(sw, true);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (tb_route(sw)) {
|
|
/*
|
|
* The used mode changes are from OFF to
|
|
* HiFi-Uni/HiFi-BiDir/Normal-Uni or from Normal-Uni to
|
|
* HiFi-Uni.
|
|
*/
|
|
if (sw->tmu.rate == TB_SWITCH_TMU_RATE_OFF) {
|
|
if (unidirectional)
|
|
ret = __tb_switch_tmu_enable_unidirectional(sw);
|
|
else
|
|
ret = __tb_switch_tmu_enable_bidirectional(sw);
|
|
if (ret)
|
|
return ret;
|
|
} else if (sw->tmu.rate == TB_SWITCH_TMU_RATE_NORMAL) {
|
|
ret = __tb_switch_tmu_change_mode(sw);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
sw->tmu.unidirectional = unidirectional;
|
|
} else {
|
|
/*
|
|
* Host router port configurations are written as
|
|
* part of configurations for downstream port of the parent
|
|
* of the child node - see above.
|
|
* Here only the host router' rate configuration is written.
|
|
*/
|
|
ret = tb_switch_tmu_rate_write(sw, sw->tmu.rate_request);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
sw->tmu.rate = sw->tmu.rate_request;
|
|
|
|
tb_sw_dbg(sw, "TMU: mode set to: %s\n", tb_switch_tmu_mode_name(sw));
|
|
return tb_switch_tmu_set_time_disruption(sw, false);
|
|
}
|
|
|
|
/**
|
|
* tb_switch_tmu_configure() - Configure the TMU rate and directionality
|
|
* @sw: Router whose mode to change
|
|
* @rate: Rate to configure Off/Normal/HiFi
|
|
* @unidirectional: If uni-directional (bi-directional otherwise)
|
|
*
|
|
* Selects the rate of the TMU and directionality (uni-directional or
|
|
* bi-directional). Must be called before tb_switch_tmu_enable().
|
|
*/
|
|
void tb_switch_tmu_configure(struct tb_switch *sw,
|
|
enum tb_switch_tmu_rate rate, bool unidirectional)
|
|
{
|
|
sw->tmu.unidirectional_request = unidirectional;
|
|
sw->tmu.rate_request = rate;
|
|
}
|
|
|
|
static int tb_switch_tmu_config_enable(struct device *dev, void *rate)
|
|
{
|
|
if (tb_is_switch(dev)) {
|
|
struct tb_switch *sw = tb_to_switch(dev);
|
|
|
|
tb_switch_tmu_configure(sw, *(enum tb_switch_tmu_rate *)rate,
|
|
tb_switch_is_clx_enabled(sw, TB_CL1));
|
|
if (tb_switch_tmu_enable(sw))
|
|
tb_sw_dbg(sw, "fail switching TMU mode for 1st depth router\n");
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
/**
|
|
* tb_switch_enable_tmu_1st_child - Configure and enable TMU for 1st chidren
|
|
* @sw: The router to configure and enable it's children TMU
|
|
* @rate: Rate of the TMU to configure the router's chidren to
|
|
*
|
|
* Configures and enables the TMU mode of 1st depth children of the specified
|
|
* router to the specified rate.
|
|
*/
|
|
void tb_switch_enable_tmu_1st_child(struct tb_switch *sw,
|
|
enum tb_switch_tmu_rate rate)
|
|
{
|
|
device_for_each_child(&sw->dev, &rate,
|
|
tb_switch_tmu_config_enable);
|
|
}
|