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![Sudeep Holla](/assets/img/avatar_default.png)
Currently, quite a few clockevent devices have cpumask set to cpu_all_mask which should be fine. However, cpu_possible_mask is more accurate and if there are any other clockevent devices in the system which have cpumask set to cpu_possible_mask, then having cpu_all_mask may result in issues (mostly boot hang with forever loops in clockevents_notify_released). So, lets replace all the clockevent device cpu_all_mask to cpu_possible_mask in order to prevent above mentioned possible issue. Cc: Daniel Lezcano <daniel.lezcano@linaro.org> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Thierry Reding <thierry.reding@gmail.com> Cc: Jonathan Hunter <jonathanh@nvidia.com> Cc: Santosh Shilimkar <ssantosh@kernel.org> Signed-off-by: Sudeep Holla <sudeep.holla@arm.com> Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
266 lines
6 KiB
C
266 lines
6 KiB
C
// SPDX-License-Identifier: GPL-2.0
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// Copyright (C) 2005-2017 Andes Technology Corporation
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/*
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* Andestech ATCPIT100 Timer Device Driver Implementation
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* Rick Chen, Andes Technology Corporation <rick@andestech.com>
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*
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*/
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#include <linux/irq.h>
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#include <linux/clocksource.h>
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#include <linux/clockchips.h>
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#include <linux/interrupt.h>
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#include <linux/ioport.h>
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#include <linux/cpufreq.h>
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#include <linux/sched.h>
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#include <linux/sched_clock.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include "timer-of.h"
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#ifdef CONFIG_NDS32
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#include <asm/vdso_timer_info.h>
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#endif
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/*
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* Definition of register offsets
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*/
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/* ID and Revision Register */
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#define ID_REV 0x0
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/* Configuration Register */
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#define CFG 0x10
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/* Interrupt Enable Register */
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#define INT_EN 0x14
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#define CH_INT_EN(c, i) ((1<<i)<<(4*c))
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#define CH0INT0EN 0x01
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/* Interrupt Status Register */
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#define INT_STA 0x18
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#define CH0INT0 0x01
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/* Channel Enable Register */
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#define CH_EN 0x1C
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#define CH0TMR0EN 0x1
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#define CH1TMR0EN 0x10
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/* Channel 0 , 1 Control Register */
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#define CH0_CTL (0x20)
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#define CH1_CTL (0x20 + 0x10)
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/* Channel clock source , bit 3 , 0:External clock , 1:APB clock */
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#define APB_CLK BIT(3)
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/* Channel mode , bit 0~2 */
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#define TMR_32 0x1
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#define TMR_16 0x2
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#define TMR_8 0x3
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/* Channel 0 , 1 Reload Register */
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#define CH0_REL (0x24)
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#define CH1_REL (0x24 + 0x10)
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/* Channel 0 , 1 Counter Register */
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#define CH0_CNT (0x28)
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#define CH1_CNT (0x28 + 0x10)
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#define TIMER_SYNC_TICKS 3
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static void atcpit100_ch1_tmr0_en(void __iomem *base)
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{
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writel(~0, base + CH1_REL);
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writel(APB_CLK|TMR_32, base + CH1_CTL);
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}
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static void atcpit100_ch0_tmr0_en(void __iomem *base)
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{
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writel(APB_CLK|TMR_32, base + CH0_CTL);
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}
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static void atcpit100_clkevt_time_setup(void __iomem *base, unsigned long delay)
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{
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writel(delay, base + CH0_CNT);
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writel(delay, base + CH0_REL);
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}
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static void atcpit100_timer_clear_interrupt(void __iomem *base)
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{
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u32 val;
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val = readl(base + INT_STA);
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writel(val | CH0INT0, base + INT_STA);
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}
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static void atcpit100_clocksource_start(void __iomem *base)
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{
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u32 val;
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val = readl(base + CH_EN);
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writel(val | CH1TMR0EN, base + CH_EN);
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}
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static void atcpit100_clkevt_time_start(void __iomem *base)
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{
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u32 val;
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val = readl(base + CH_EN);
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writel(val | CH0TMR0EN, base + CH_EN);
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}
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static void atcpit100_clkevt_time_stop(void __iomem *base)
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{
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u32 val;
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atcpit100_timer_clear_interrupt(base);
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val = readl(base + CH_EN);
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writel(val & ~CH0TMR0EN, base + CH_EN);
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}
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static int atcpit100_clkevt_next_event(unsigned long evt,
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struct clock_event_device *clkevt)
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{
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u32 val;
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struct timer_of *to = to_timer_of(clkevt);
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val = readl(timer_of_base(to) + CH_EN);
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writel(val & ~CH0TMR0EN, timer_of_base(to) + CH_EN);
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writel(evt, timer_of_base(to) + CH0_REL);
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writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN);
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return 0;
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}
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static int atcpit100_clkevt_set_periodic(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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atcpit100_clkevt_time_setup(timer_of_base(to), timer_of_period(to));
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atcpit100_clkevt_time_start(timer_of_base(to));
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return 0;
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}
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static int atcpit100_clkevt_shutdown(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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atcpit100_clkevt_time_stop(timer_of_base(to));
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return 0;
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}
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static int atcpit100_clkevt_set_oneshot(struct clock_event_device *evt)
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{
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struct timer_of *to = to_timer_of(evt);
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u32 val;
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writel(~0x0, timer_of_base(to) + CH0_REL);
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val = readl(timer_of_base(to) + CH_EN);
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writel(val | CH0TMR0EN, timer_of_base(to) + CH_EN);
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return 0;
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}
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static irqreturn_t atcpit100_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *evt = (struct clock_event_device *)dev_id;
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struct timer_of *to = to_timer_of(evt);
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atcpit100_timer_clear_interrupt(timer_of_base(to));
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evt->event_handler(evt);
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return IRQ_HANDLED;
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}
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static struct timer_of to = {
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.flags = TIMER_OF_IRQ | TIMER_OF_CLOCK | TIMER_OF_BASE,
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.clkevt = {
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.name = "atcpit100_tick",
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.rating = 300,
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.features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT,
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.set_state_shutdown = atcpit100_clkevt_shutdown,
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.set_state_periodic = atcpit100_clkevt_set_periodic,
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.set_state_oneshot = atcpit100_clkevt_set_oneshot,
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.tick_resume = atcpit100_clkevt_shutdown,
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.set_next_event = atcpit100_clkevt_next_event,
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.cpumask = cpu_possible_mask,
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},
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.of_irq = {
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.handler = atcpit100_timer_interrupt,
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.flags = IRQF_TIMER | IRQF_IRQPOLL,
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},
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/*
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* FIXME: we currently only support clocking using PCLK
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* and using EXTCLK is not supported in the driver.
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*/
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.of_clk = {
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.name = "PCLK",
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}
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};
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static u64 notrace atcpit100_timer_sched_read(void)
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{
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return ~readl(timer_of_base(&to) + CH1_CNT);
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}
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#ifdef CONFIG_NDS32
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static void fill_vdso_need_info(struct device_node *node)
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{
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struct resource timer_res;
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of_address_to_resource(node, 0, &timer_res);
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timer_info.mapping_base = (unsigned long)timer_res.start;
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timer_info.cycle_count_down = true;
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timer_info.cycle_count_reg_offset = CH1_CNT;
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}
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#endif
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static int __init atcpit100_timer_init(struct device_node *node)
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{
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int ret;
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u32 val;
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void __iomem *base;
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ret = timer_of_init(node, &to);
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if (ret)
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return ret;
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base = timer_of_base(&to);
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sched_clock_register(atcpit100_timer_sched_read, 32,
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timer_of_rate(&to));
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ret = clocksource_mmio_init(base + CH1_CNT,
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node->name, timer_of_rate(&to), 300, 32,
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clocksource_mmio_readl_down);
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if (ret) {
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pr_err("Failed to register clocksource\n");
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return ret;
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}
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/* clear channel 0 timer0 interrupt */
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atcpit100_timer_clear_interrupt(base);
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clockevents_config_and_register(&to.clkevt, timer_of_rate(&to),
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TIMER_SYNC_TICKS, 0xffffffff);
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atcpit100_ch0_tmr0_en(base);
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atcpit100_ch1_tmr0_en(base);
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atcpit100_clocksource_start(base);
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atcpit100_clkevt_time_start(base);
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/* Enable channel 0 timer0 interrupt */
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val = readl(base + INT_EN);
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writel(val | CH0INT0EN, base + INT_EN);
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#ifdef CONFIG_NDS32
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fill_vdso_need_info(node);
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#endif
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return ret;
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}
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TIMER_OF_DECLARE(atcpit100, "andestech,atcpit100", atcpit100_timer_init);
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