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![Thomas Gleixner](/assets/img/avatar_default.png)
Based on 2 normalized pattern(s): this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation this program is free software you can redistribute it and or modify it under the terms of the gnu general public license version 2 as published by the free software foundation # extracted by the scancode license scanner the SPDX license identifier GPL-2.0-only has been chosen to replace the boilerplate/reference in 4122 file(s). Signed-off-by: Thomas Gleixner <tglx@linutronix.de> Reviewed-by: Enrico Weigelt <info@metux.net> Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org> Reviewed-by: Allison Randal <allison@lohutok.net> Cc: linux-spdx@vger.kernel.org Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
304 lines
6.8 KiB
C
304 lines
6.8 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Rockchip timer support
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*
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* Copyright (C) Daniel Lezcano <daniel.lezcano@linaro.org>
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*/
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#include <linux/clk.h>
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#include <linux/clockchips.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/sched_clock.h>
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#include <linux/slab.h>
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_irq.h>
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#define TIMER_NAME "rk_timer"
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#define TIMER_LOAD_COUNT0 0x00
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#define TIMER_LOAD_COUNT1 0x04
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#define TIMER_CURRENT_VALUE0 0x08
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#define TIMER_CURRENT_VALUE1 0x0C
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#define TIMER_CONTROL_REG3288 0x10
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#define TIMER_CONTROL_REG3399 0x1c
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#define TIMER_INT_STATUS 0x18
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#define TIMER_DISABLE 0x0
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#define TIMER_ENABLE 0x1
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#define TIMER_MODE_FREE_RUNNING (0 << 1)
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#define TIMER_MODE_USER_DEFINED_COUNT (1 << 1)
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#define TIMER_INT_UNMASK (1 << 2)
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struct rk_timer {
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void __iomem *base;
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void __iomem *ctrl;
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struct clk *clk;
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struct clk *pclk;
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u32 freq;
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int irq;
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};
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struct rk_clkevt {
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struct clock_event_device ce;
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struct rk_timer timer;
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};
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static struct rk_clkevt *rk_clkevt;
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static struct rk_timer *rk_clksrc;
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static inline struct rk_timer *rk_timer(struct clock_event_device *ce)
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{
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return &container_of(ce, struct rk_clkevt, ce)->timer;
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}
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static inline void rk_timer_disable(struct rk_timer *timer)
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{
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writel_relaxed(TIMER_DISABLE, timer->ctrl);
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}
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static inline void rk_timer_enable(struct rk_timer *timer, u32 flags)
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{
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writel_relaxed(TIMER_ENABLE | flags, timer->ctrl);
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}
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static void rk_timer_update_counter(unsigned long cycles,
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struct rk_timer *timer)
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{
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writel_relaxed(cycles, timer->base + TIMER_LOAD_COUNT0);
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writel_relaxed(0, timer->base + TIMER_LOAD_COUNT1);
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}
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static void rk_timer_interrupt_clear(struct rk_timer *timer)
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{
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writel_relaxed(1, timer->base + TIMER_INT_STATUS);
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}
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static inline int rk_timer_set_next_event(unsigned long cycles,
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struct clock_event_device *ce)
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{
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struct rk_timer *timer = rk_timer(ce);
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rk_timer_disable(timer);
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rk_timer_update_counter(cycles, timer);
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rk_timer_enable(timer, TIMER_MODE_USER_DEFINED_COUNT |
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TIMER_INT_UNMASK);
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return 0;
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}
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static int rk_timer_shutdown(struct clock_event_device *ce)
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{
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struct rk_timer *timer = rk_timer(ce);
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rk_timer_disable(timer);
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return 0;
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}
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static int rk_timer_set_periodic(struct clock_event_device *ce)
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{
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struct rk_timer *timer = rk_timer(ce);
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rk_timer_disable(timer);
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rk_timer_update_counter(timer->freq / HZ - 1, timer);
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rk_timer_enable(timer, TIMER_MODE_FREE_RUNNING | TIMER_INT_UNMASK);
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return 0;
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}
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static irqreturn_t rk_timer_interrupt(int irq, void *dev_id)
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{
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struct clock_event_device *ce = dev_id;
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struct rk_timer *timer = rk_timer(ce);
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rk_timer_interrupt_clear(timer);
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if (clockevent_state_oneshot(ce))
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rk_timer_disable(timer);
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ce->event_handler(ce);
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return IRQ_HANDLED;
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}
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static u64 notrace rk_timer_sched_read(void)
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{
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return ~readl_relaxed(rk_clksrc->base + TIMER_CURRENT_VALUE0);
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}
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static int __init
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rk_timer_probe(struct rk_timer *timer, struct device_node *np)
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{
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struct clk *timer_clk;
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struct clk *pclk;
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int ret = -EINVAL, irq;
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u32 ctrl_reg = TIMER_CONTROL_REG3288;
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timer->base = of_iomap(np, 0);
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if (!timer->base) {
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pr_err("Failed to get base address for '%s'\n", TIMER_NAME);
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return -ENXIO;
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}
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if (of_device_is_compatible(np, "rockchip,rk3399-timer"))
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ctrl_reg = TIMER_CONTROL_REG3399;
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timer->ctrl = timer->base + ctrl_reg;
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pclk = of_clk_get_by_name(np, "pclk");
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if (IS_ERR(pclk)) {
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ret = PTR_ERR(pclk);
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pr_err("Failed to get pclk for '%s'\n", TIMER_NAME);
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goto out_unmap;
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}
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ret = clk_prepare_enable(pclk);
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if (ret) {
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pr_err("Failed to enable pclk for '%s'\n", TIMER_NAME);
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goto out_unmap;
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}
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timer->pclk = pclk;
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timer_clk = of_clk_get_by_name(np, "timer");
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if (IS_ERR(timer_clk)) {
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ret = PTR_ERR(timer_clk);
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pr_err("Failed to get timer clock for '%s'\n", TIMER_NAME);
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goto out_timer_clk;
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}
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ret = clk_prepare_enable(timer_clk);
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if (ret) {
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pr_err("Failed to enable timer clock\n");
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goto out_timer_clk;
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}
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timer->clk = timer_clk;
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timer->freq = clk_get_rate(timer_clk);
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irq = irq_of_parse_and_map(np, 0);
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if (!irq) {
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ret = -EINVAL;
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pr_err("Failed to map interrupts for '%s'\n", TIMER_NAME);
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goto out_irq;
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}
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timer->irq = irq;
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rk_timer_interrupt_clear(timer);
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rk_timer_disable(timer);
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return 0;
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out_irq:
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clk_disable_unprepare(timer_clk);
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out_timer_clk:
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clk_disable_unprepare(pclk);
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out_unmap:
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iounmap(timer->base);
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return ret;
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}
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static void __init rk_timer_cleanup(struct rk_timer *timer)
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{
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clk_disable_unprepare(timer->clk);
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clk_disable_unprepare(timer->pclk);
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iounmap(timer->base);
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}
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static int __init rk_clkevt_init(struct device_node *np)
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{
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struct clock_event_device *ce;
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int ret = -EINVAL;
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rk_clkevt = kzalloc(sizeof(struct rk_clkevt), GFP_KERNEL);
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if (!rk_clkevt) {
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ret = -ENOMEM;
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goto out;
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}
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ret = rk_timer_probe(&rk_clkevt->timer, np);
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if (ret)
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goto out_probe;
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ce = &rk_clkevt->ce;
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ce->name = TIMER_NAME;
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ce->features = CLOCK_EVT_FEAT_PERIODIC | CLOCK_EVT_FEAT_ONESHOT |
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CLOCK_EVT_FEAT_DYNIRQ;
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ce->set_next_event = rk_timer_set_next_event;
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ce->set_state_shutdown = rk_timer_shutdown;
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ce->set_state_periodic = rk_timer_set_periodic;
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ce->irq = rk_clkevt->timer.irq;
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ce->cpumask = cpu_possible_mask;
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ce->rating = 250;
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ret = request_irq(rk_clkevt->timer.irq, rk_timer_interrupt, IRQF_TIMER,
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TIMER_NAME, ce);
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if (ret) {
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pr_err("Failed to initialize '%s': %d\n",
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TIMER_NAME, ret);
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goto out_irq;
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}
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clockevents_config_and_register(&rk_clkevt->ce,
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rk_clkevt->timer.freq, 1, UINT_MAX);
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return 0;
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out_irq:
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rk_timer_cleanup(&rk_clkevt->timer);
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out_probe:
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kfree(rk_clkevt);
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out:
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/* Leave rk_clkevt not NULL to prevent future init */
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rk_clkevt = ERR_PTR(ret);
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return ret;
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}
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static int __init rk_clksrc_init(struct device_node *np)
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{
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int ret = -EINVAL;
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rk_clksrc = kzalloc(sizeof(struct rk_timer), GFP_KERNEL);
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if (!rk_clksrc) {
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ret = -ENOMEM;
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goto out;
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}
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ret = rk_timer_probe(rk_clksrc, np);
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if (ret)
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goto out_probe;
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rk_timer_update_counter(UINT_MAX, rk_clksrc);
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rk_timer_enable(rk_clksrc, 0);
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ret = clocksource_mmio_init(rk_clksrc->base + TIMER_CURRENT_VALUE0,
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TIMER_NAME, rk_clksrc->freq, 250, 32,
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clocksource_mmio_readl_down);
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if (ret) {
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pr_err("Failed to register clocksource\n");
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goto out_clocksource;
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}
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sched_clock_register(rk_timer_sched_read, 32, rk_clksrc->freq);
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return 0;
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out_clocksource:
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rk_timer_cleanup(rk_clksrc);
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out_probe:
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kfree(rk_clksrc);
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out:
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/* Leave rk_clksrc not NULL to prevent future init */
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rk_clksrc = ERR_PTR(ret);
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return ret;
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}
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static int __init rk_timer_init(struct device_node *np)
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{
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if (!rk_clkevt)
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return rk_clkevt_init(np);
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if (!rk_clksrc)
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return rk_clksrc_init(np);
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pr_err("Too many timer definitions for '%s'\n", TIMER_NAME);
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return -EINVAL;
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}
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TIMER_OF_DECLARE(rk3288_timer, "rockchip,rk3288-timer", rk_timer_init);
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TIMER_OF_DECLARE(rk3399_timer, "rockchip,rk3399-timer", rk_timer_init);
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