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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
![Lubomir Rintel](/assets/img/avatar_default.png)
[ Upstream commit 0c89446379
]
When a channel configuration fails, the status of the channel is set to
DEV_ERROR so that an attempt to submit it fails. However, this status
sticks until the heat end of the universe, making it impossible to
recover from the error.
Let's reset it when the channel is released so that further use of the
channel with correct configuration is not impacted.
Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lore.kernel.org/r/20200419164912.670973-5-lkundrak@v3.sk
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Sasha Levin <sashal@kernel.org>
749 lines
18 KiB
C
749 lines
18 KiB
C
// SPDX-License-Identifier: GPL-2.0-or-later
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/*
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* Driver For Marvell Two-channel DMA Engine
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*
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* Copyright: Marvell International Ltd.
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*/
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#include <linux/err.h>
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/interrupt.h>
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#include <linux/dma-mapping.h>
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#include <linux/slab.h>
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#include <linux/dmaengine.h>
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#include <linux/platform_device.h>
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#include <linux/device.h>
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#include <linux/platform_data/dma-mmp_tdma.h>
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#include <linux/of_device.h>
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#include <linux/of_dma.h>
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#include "dmaengine.h"
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/*
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* Two-Channel DMA registers
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*/
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#define TDBCR 0x00 /* Byte Count */
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#define TDSAR 0x10 /* Src Addr */
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#define TDDAR 0x20 /* Dst Addr */
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#define TDNDPR 0x30 /* Next Desc */
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#define TDCR 0x40 /* Control */
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#define TDCP 0x60 /* Priority*/
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#define TDCDPR 0x70 /* Current Desc */
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#define TDIMR 0x80 /* Int Mask */
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#define TDISR 0xa0 /* Int Status */
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/* Two-Channel DMA Control Register */
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#define TDCR_SSZ_8_BITS (0x0 << 22) /* Sample Size */
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#define TDCR_SSZ_12_BITS (0x1 << 22)
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#define TDCR_SSZ_16_BITS (0x2 << 22)
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#define TDCR_SSZ_20_BITS (0x3 << 22)
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#define TDCR_SSZ_24_BITS (0x4 << 22)
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#define TDCR_SSZ_32_BITS (0x5 << 22)
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#define TDCR_SSZ_SHIFT (0x1 << 22)
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#define TDCR_SSZ_MASK (0x7 << 22)
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#define TDCR_SSPMOD (0x1 << 21) /* SSP MOD */
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#define TDCR_ABR (0x1 << 20) /* Channel Abort */
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#define TDCR_CDE (0x1 << 17) /* Close Desc Enable */
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#define TDCR_PACKMOD (0x1 << 16) /* Pack Mode (ADMA Only) */
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#define TDCR_CHANACT (0x1 << 14) /* Channel Active */
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#define TDCR_FETCHND (0x1 << 13) /* Fetch Next Desc */
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#define TDCR_CHANEN (0x1 << 12) /* Channel Enable */
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#define TDCR_INTMODE (0x1 << 10) /* Interrupt Mode */
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#define TDCR_CHAINMOD (0x1 << 9) /* Chain Mode */
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#define TDCR_BURSTSZ_MSK (0x7 << 6) /* Burst Size */
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#define TDCR_BURSTSZ_4B (0x0 << 6)
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#define TDCR_BURSTSZ_8B (0x1 << 6)
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#define TDCR_BURSTSZ_16B (0x3 << 6)
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#define TDCR_BURSTSZ_32B (0x6 << 6)
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#define TDCR_BURSTSZ_64B (0x7 << 6)
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#define TDCR_BURSTSZ_SQU_1B (0x5 << 6)
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#define TDCR_BURSTSZ_SQU_2B (0x6 << 6)
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#define TDCR_BURSTSZ_SQU_4B (0x0 << 6)
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#define TDCR_BURSTSZ_SQU_8B (0x1 << 6)
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#define TDCR_BURSTSZ_SQU_16B (0x3 << 6)
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#define TDCR_BURSTSZ_SQU_32B (0x7 << 6)
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#define TDCR_BURSTSZ_128B (0x5 << 6)
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#define TDCR_DSTDIR_MSK (0x3 << 4) /* Dst Direction */
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#define TDCR_DSTDIR_ADDR_HOLD (0x2 << 4) /* Dst Addr Hold */
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#define TDCR_DSTDIR_ADDR_INC (0x0 << 4) /* Dst Addr Increment */
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#define TDCR_SRCDIR_MSK (0x3 << 2) /* Src Direction */
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#define TDCR_SRCDIR_ADDR_HOLD (0x2 << 2) /* Src Addr Hold */
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#define TDCR_SRCDIR_ADDR_INC (0x0 << 2) /* Src Addr Increment */
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#define TDCR_DSTDESCCONT (0x1 << 1)
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#define TDCR_SRCDESTCONT (0x1 << 0)
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/* Two-Channel DMA Int Mask Register */
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#define TDIMR_COMP (0x1 << 0)
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/* Two-Channel DMA Int Status Register */
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#define TDISR_COMP (0x1 << 0)
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/*
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* Two-Channel DMA Descriptor Struct
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* NOTE: desc's buf must be aligned to 16 bytes.
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*/
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struct mmp_tdma_desc {
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u32 byte_cnt;
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u32 src_addr;
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u32 dst_addr;
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u32 nxt_desc;
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};
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enum mmp_tdma_type {
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MMP_AUD_TDMA = 0,
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PXA910_SQU,
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};
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#define TDMA_MAX_XFER_BYTES SZ_64K
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struct mmp_tdma_chan {
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struct device *dev;
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struct dma_chan chan;
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struct dma_async_tx_descriptor desc;
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struct tasklet_struct tasklet;
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struct mmp_tdma_desc *desc_arr;
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dma_addr_t desc_arr_phys;
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int desc_num;
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enum dma_transfer_direction dir;
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dma_addr_t dev_addr;
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u32 burst_sz;
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enum dma_slave_buswidth buswidth;
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enum dma_status status;
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struct dma_slave_config slave_config;
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int idx;
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enum mmp_tdma_type type;
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int irq;
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void __iomem *reg_base;
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size_t buf_len;
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size_t period_len;
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size_t pos;
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struct gen_pool *pool;
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};
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#define TDMA_CHANNEL_NUM 2
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struct mmp_tdma_device {
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struct device *dev;
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void __iomem *base;
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struct dma_device device;
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struct mmp_tdma_chan *tdmac[TDMA_CHANNEL_NUM];
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};
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#define to_mmp_tdma_chan(dchan) container_of(dchan, struct mmp_tdma_chan, chan)
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static int mmp_tdma_config_write(struct dma_chan *chan,
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enum dma_transfer_direction dir,
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struct dma_slave_config *dmaengine_cfg);
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static void mmp_tdma_chan_set_desc(struct mmp_tdma_chan *tdmac, dma_addr_t phys)
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{
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writel(phys, tdmac->reg_base + TDNDPR);
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writel(readl(tdmac->reg_base + TDCR) | TDCR_FETCHND,
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tdmac->reg_base + TDCR);
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}
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static void mmp_tdma_enable_irq(struct mmp_tdma_chan *tdmac, bool enable)
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{
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if (enable)
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writel(TDIMR_COMP, tdmac->reg_base + TDIMR);
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else
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writel(0, tdmac->reg_base + TDIMR);
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}
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static void mmp_tdma_enable_chan(struct mmp_tdma_chan *tdmac)
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{
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/* enable dma chan */
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writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
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tdmac->reg_base + TDCR);
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tdmac->status = DMA_IN_PROGRESS;
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}
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static int mmp_tdma_disable_chan(struct dma_chan *chan)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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u32 tdcr;
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tdcr = readl(tdmac->reg_base + TDCR);
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tdcr |= TDCR_ABR;
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tdcr &= ~TDCR_CHANEN;
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writel(tdcr, tdmac->reg_base + TDCR);
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tdmac->status = DMA_COMPLETE;
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return 0;
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}
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static int mmp_tdma_resume_chan(struct dma_chan *chan)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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writel(readl(tdmac->reg_base + TDCR) | TDCR_CHANEN,
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tdmac->reg_base + TDCR);
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tdmac->status = DMA_IN_PROGRESS;
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return 0;
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}
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static int mmp_tdma_pause_chan(struct dma_chan *chan)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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writel(readl(tdmac->reg_base + TDCR) & ~TDCR_CHANEN,
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tdmac->reg_base + TDCR);
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tdmac->status = DMA_PAUSED;
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return 0;
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}
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static int mmp_tdma_config_chan(struct dma_chan *chan)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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unsigned int tdcr = 0;
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mmp_tdma_disable_chan(chan);
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if (tdmac->dir == DMA_MEM_TO_DEV)
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tdcr = TDCR_DSTDIR_ADDR_HOLD | TDCR_SRCDIR_ADDR_INC;
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else if (tdmac->dir == DMA_DEV_TO_MEM)
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tdcr = TDCR_SRCDIR_ADDR_HOLD | TDCR_DSTDIR_ADDR_INC;
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if (tdmac->type == MMP_AUD_TDMA) {
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tdcr |= TDCR_PACKMOD;
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switch (tdmac->burst_sz) {
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case 4:
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tdcr |= TDCR_BURSTSZ_4B;
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break;
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case 8:
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tdcr |= TDCR_BURSTSZ_8B;
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break;
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case 16:
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tdcr |= TDCR_BURSTSZ_16B;
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break;
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case 32:
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tdcr |= TDCR_BURSTSZ_32B;
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break;
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case 64:
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tdcr |= TDCR_BURSTSZ_64B;
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break;
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case 128:
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tdcr |= TDCR_BURSTSZ_128B;
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break;
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default:
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dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
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return -EINVAL;
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}
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switch (tdmac->buswidth) {
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case DMA_SLAVE_BUSWIDTH_1_BYTE:
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tdcr |= TDCR_SSZ_8_BITS;
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break;
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case DMA_SLAVE_BUSWIDTH_2_BYTES:
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tdcr |= TDCR_SSZ_16_BITS;
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break;
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case DMA_SLAVE_BUSWIDTH_4_BYTES:
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tdcr |= TDCR_SSZ_32_BITS;
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break;
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default:
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dev_err(tdmac->dev, "mmp_tdma: unknown bus size.\n");
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return -EINVAL;
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}
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} else if (tdmac->type == PXA910_SQU) {
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tdcr |= TDCR_SSPMOD;
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switch (tdmac->burst_sz) {
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case 1:
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tdcr |= TDCR_BURSTSZ_SQU_1B;
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break;
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case 2:
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tdcr |= TDCR_BURSTSZ_SQU_2B;
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break;
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case 4:
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tdcr |= TDCR_BURSTSZ_SQU_4B;
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break;
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case 8:
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tdcr |= TDCR_BURSTSZ_SQU_8B;
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break;
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case 16:
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tdcr |= TDCR_BURSTSZ_SQU_16B;
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break;
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case 32:
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tdcr |= TDCR_BURSTSZ_SQU_32B;
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break;
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default:
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dev_err(tdmac->dev, "mmp_tdma: unknown burst size.\n");
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return -EINVAL;
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}
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}
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writel(tdcr, tdmac->reg_base + TDCR);
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return 0;
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}
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static int mmp_tdma_clear_chan_irq(struct mmp_tdma_chan *tdmac)
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{
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u32 reg = readl(tdmac->reg_base + TDISR);
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if (reg & TDISR_COMP) {
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/* clear irq */
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reg &= ~TDISR_COMP;
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writel(reg, tdmac->reg_base + TDISR);
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return 0;
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}
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return -EAGAIN;
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}
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static size_t mmp_tdma_get_pos(struct mmp_tdma_chan *tdmac)
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{
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size_t reg;
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if (tdmac->idx == 0) {
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reg = __raw_readl(tdmac->reg_base + TDSAR);
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reg -= tdmac->desc_arr[0].src_addr;
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} else if (tdmac->idx == 1) {
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reg = __raw_readl(tdmac->reg_base + TDDAR);
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reg -= tdmac->desc_arr[0].dst_addr;
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} else
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return -EINVAL;
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return reg;
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}
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static irqreturn_t mmp_tdma_chan_handler(int irq, void *dev_id)
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{
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struct mmp_tdma_chan *tdmac = dev_id;
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if (mmp_tdma_clear_chan_irq(tdmac) == 0) {
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tasklet_schedule(&tdmac->tasklet);
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return IRQ_HANDLED;
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} else
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return IRQ_NONE;
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}
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static irqreturn_t mmp_tdma_int_handler(int irq, void *dev_id)
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{
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struct mmp_tdma_device *tdev = dev_id;
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int i, ret;
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int irq_num = 0;
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for (i = 0; i < TDMA_CHANNEL_NUM; i++) {
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struct mmp_tdma_chan *tdmac = tdev->tdmac[i];
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ret = mmp_tdma_chan_handler(irq, tdmac);
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if (ret == IRQ_HANDLED)
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irq_num++;
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}
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if (irq_num)
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return IRQ_HANDLED;
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else
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return IRQ_NONE;
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}
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static void dma_do_tasklet(unsigned long data)
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{
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struct mmp_tdma_chan *tdmac = (struct mmp_tdma_chan *)data;
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dmaengine_desc_get_callback_invoke(&tdmac->desc, NULL);
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}
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static void mmp_tdma_free_descriptor(struct mmp_tdma_chan *tdmac)
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{
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struct gen_pool *gpool;
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int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
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gpool = tdmac->pool;
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if (gpool && tdmac->desc_arr)
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gen_pool_free(gpool, (unsigned long)tdmac->desc_arr,
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size);
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tdmac->desc_arr = NULL;
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if (tdmac->status == DMA_ERROR)
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tdmac->status = DMA_COMPLETE;
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return;
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}
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static dma_cookie_t mmp_tdma_tx_submit(struct dma_async_tx_descriptor *tx)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(tx->chan);
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mmp_tdma_chan_set_desc(tdmac, tdmac->desc_arr_phys);
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return 0;
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}
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static int mmp_tdma_alloc_chan_resources(struct dma_chan *chan)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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int ret;
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dma_async_tx_descriptor_init(&tdmac->desc, chan);
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tdmac->desc.tx_submit = mmp_tdma_tx_submit;
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if (tdmac->irq) {
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ret = devm_request_irq(tdmac->dev, tdmac->irq,
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mmp_tdma_chan_handler, 0, "tdma", tdmac);
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if (ret)
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return ret;
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}
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return 1;
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}
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static void mmp_tdma_free_chan_resources(struct dma_chan *chan)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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if (tdmac->irq)
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devm_free_irq(tdmac->dev, tdmac->irq, tdmac);
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mmp_tdma_free_descriptor(tdmac);
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return;
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}
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static struct mmp_tdma_desc *mmp_tdma_alloc_descriptor(struct mmp_tdma_chan *tdmac)
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{
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struct gen_pool *gpool;
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int size = tdmac->desc_num * sizeof(struct mmp_tdma_desc);
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gpool = tdmac->pool;
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if (!gpool)
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return NULL;
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tdmac->desc_arr = gen_pool_dma_alloc(gpool, size, &tdmac->desc_arr_phys);
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return tdmac->desc_arr;
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}
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static struct dma_async_tx_descriptor *mmp_tdma_prep_dma_cyclic(
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struct dma_chan *chan, dma_addr_t dma_addr, size_t buf_len,
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size_t period_len, enum dma_transfer_direction direction,
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unsigned long flags)
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{
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struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
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struct mmp_tdma_desc *desc;
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int num_periods = buf_len / period_len;
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int i = 0, buf = 0;
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if (tdmac->status != DMA_COMPLETE)
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return NULL;
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|
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if (period_len > TDMA_MAX_XFER_BYTES) {
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dev_err(tdmac->dev,
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"maximum period size exceeded: %zu > %d\n",
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period_len, TDMA_MAX_XFER_BYTES);
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goto err_out;
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}
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tdmac->status = DMA_IN_PROGRESS;
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tdmac->desc_num = num_periods;
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desc = mmp_tdma_alloc_descriptor(tdmac);
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if (!desc)
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goto err_out;
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if (mmp_tdma_config_write(chan, direction, &tdmac->slave_config))
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goto err_out;
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while (buf < buf_len) {
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desc = &tdmac->desc_arr[i];
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if (i + 1 == num_periods)
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desc->nxt_desc = tdmac->desc_arr_phys;
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else
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desc->nxt_desc = tdmac->desc_arr_phys +
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sizeof(*desc) * (i + 1);
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if (direction == DMA_MEM_TO_DEV) {
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desc->src_addr = dma_addr;
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desc->dst_addr = tdmac->dev_addr;
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} else {
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desc->src_addr = tdmac->dev_addr;
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desc->dst_addr = dma_addr;
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}
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desc->byte_cnt = period_len;
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dma_addr += period_len;
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buf += period_len;
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i++;
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}
|
|
|
|
/* enable interrupt */
|
|
if (flags & DMA_PREP_INTERRUPT)
|
|
mmp_tdma_enable_irq(tdmac, true);
|
|
|
|
tdmac->buf_len = buf_len;
|
|
tdmac->period_len = period_len;
|
|
tdmac->pos = 0;
|
|
|
|
return &tdmac->desc;
|
|
|
|
err_out:
|
|
tdmac->status = DMA_ERROR;
|
|
return NULL;
|
|
}
|
|
|
|
static int mmp_tdma_terminate_all(struct dma_chan *chan)
|
|
{
|
|
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
|
|
|
mmp_tdma_disable_chan(chan);
|
|
/* disable interrupt */
|
|
mmp_tdma_enable_irq(tdmac, false);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mmp_tdma_config(struct dma_chan *chan,
|
|
struct dma_slave_config *dmaengine_cfg)
|
|
{
|
|
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
|
|
|
memcpy(&tdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int mmp_tdma_config_write(struct dma_chan *chan,
|
|
enum dma_transfer_direction dir,
|
|
struct dma_slave_config *dmaengine_cfg)
|
|
{
|
|
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
|
|
|
if (dir == DMA_DEV_TO_MEM) {
|
|
tdmac->dev_addr = dmaengine_cfg->src_addr;
|
|
tdmac->burst_sz = dmaengine_cfg->src_maxburst;
|
|
tdmac->buswidth = dmaengine_cfg->src_addr_width;
|
|
} else {
|
|
tdmac->dev_addr = dmaengine_cfg->dst_addr;
|
|
tdmac->burst_sz = dmaengine_cfg->dst_maxburst;
|
|
tdmac->buswidth = dmaengine_cfg->dst_addr_width;
|
|
}
|
|
tdmac->dir = dir;
|
|
|
|
return mmp_tdma_config_chan(chan);
|
|
}
|
|
|
|
static enum dma_status mmp_tdma_tx_status(struct dma_chan *chan,
|
|
dma_cookie_t cookie, struct dma_tx_state *txstate)
|
|
{
|
|
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
|
|
|
tdmac->pos = mmp_tdma_get_pos(tdmac);
|
|
dma_set_tx_state(txstate, chan->completed_cookie, chan->cookie,
|
|
tdmac->buf_len - tdmac->pos);
|
|
|
|
return tdmac->status;
|
|
}
|
|
|
|
static void mmp_tdma_issue_pending(struct dma_chan *chan)
|
|
{
|
|
struct mmp_tdma_chan *tdmac = to_mmp_tdma_chan(chan);
|
|
|
|
mmp_tdma_enable_chan(tdmac);
|
|
}
|
|
|
|
static int mmp_tdma_remove(struct platform_device *pdev)
|
|
{
|
|
return 0;
|
|
}
|
|
|
|
static int mmp_tdma_chan_init(struct mmp_tdma_device *tdev,
|
|
int idx, int irq,
|
|
int type, struct gen_pool *pool)
|
|
{
|
|
struct mmp_tdma_chan *tdmac;
|
|
|
|
if (idx >= TDMA_CHANNEL_NUM) {
|
|
dev_err(tdev->dev, "too many channels for device!\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
/* alloc channel */
|
|
tdmac = devm_kzalloc(tdev->dev, sizeof(*tdmac), GFP_KERNEL);
|
|
if (!tdmac)
|
|
return -ENOMEM;
|
|
|
|
if (irq)
|
|
tdmac->irq = irq;
|
|
tdmac->dev = tdev->dev;
|
|
tdmac->chan.device = &tdev->device;
|
|
tdmac->idx = idx;
|
|
tdmac->type = type;
|
|
tdmac->reg_base = tdev->base + idx * 4;
|
|
tdmac->pool = pool;
|
|
tdmac->status = DMA_COMPLETE;
|
|
tdev->tdmac[tdmac->idx] = tdmac;
|
|
tasklet_init(&tdmac->tasklet, dma_do_tasklet, (unsigned long)tdmac);
|
|
|
|
/* add the channel to tdma_chan list */
|
|
list_add_tail(&tdmac->chan.device_node,
|
|
&tdev->device.channels);
|
|
return 0;
|
|
}
|
|
|
|
struct mmp_tdma_filter_param {
|
|
unsigned int chan_id;
|
|
};
|
|
|
|
static bool mmp_tdma_filter_fn(struct dma_chan *chan, void *fn_param)
|
|
{
|
|
struct mmp_tdma_filter_param *param = fn_param;
|
|
|
|
if (chan->chan_id != param->chan_id)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static struct dma_chan *mmp_tdma_xlate(struct of_phandle_args *dma_spec,
|
|
struct of_dma *ofdma)
|
|
{
|
|
struct mmp_tdma_device *tdev = ofdma->of_dma_data;
|
|
dma_cap_mask_t mask = tdev->device.cap_mask;
|
|
struct mmp_tdma_filter_param param;
|
|
|
|
if (dma_spec->args_count != 1)
|
|
return NULL;
|
|
|
|
param.chan_id = dma_spec->args[0];
|
|
|
|
if (param.chan_id >= TDMA_CHANNEL_NUM)
|
|
return NULL;
|
|
|
|
return __dma_request_channel(&mask, mmp_tdma_filter_fn, ¶m,
|
|
ofdma->of_node);
|
|
}
|
|
|
|
static const struct of_device_id mmp_tdma_dt_ids[] = {
|
|
{ .compatible = "marvell,adma-1.0", .data = (void *)MMP_AUD_TDMA},
|
|
{ .compatible = "marvell,pxa910-squ", .data = (void *)PXA910_SQU},
|
|
{}
|
|
};
|
|
MODULE_DEVICE_TABLE(of, mmp_tdma_dt_ids);
|
|
|
|
static int mmp_tdma_probe(struct platform_device *pdev)
|
|
{
|
|
enum mmp_tdma_type type;
|
|
const struct of_device_id *of_id;
|
|
struct mmp_tdma_device *tdev;
|
|
struct resource *iores;
|
|
int i, ret;
|
|
int irq = 0, irq_num = 0;
|
|
int chan_num = TDMA_CHANNEL_NUM;
|
|
struct gen_pool *pool = NULL;
|
|
|
|
of_id = of_match_device(mmp_tdma_dt_ids, &pdev->dev);
|
|
if (of_id)
|
|
type = (enum mmp_tdma_type) of_id->data;
|
|
else
|
|
type = platform_get_device_id(pdev)->driver_data;
|
|
|
|
/* always have couple channels */
|
|
tdev = devm_kzalloc(&pdev->dev, sizeof(*tdev), GFP_KERNEL);
|
|
if (!tdev)
|
|
return -ENOMEM;
|
|
|
|
tdev->dev = &pdev->dev;
|
|
|
|
for (i = 0; i < chan_num; i++) {
|
|
if (platform_get_irq(pdev, i) > 0)
|
|
irq_num++;
|
|
}
|
|
|
|
iores = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
tdev->base = devm_ioremap_resource(&pdev->dev, iores);
|
|
if (IS_ERR(tdev->base))
|
|
return PTR_ERR(tdev->base);
|
|
|
|
INIT_LIST_HEAD(&tdev->device.channels);
|
|
|
|
if (pdev->dev.of_node)
|
|
pool = of_gen_pool_get(pdev->dev.of_node, "asram", 0);
|
|
else
|
|
pool = sram_get_gpool("asram");
|
|
if (!pool) {
|
|
dev_err(&pdev->dev, "asram pool not available\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
if (irq_num != chan_num) {
|
|
irq = platform_get_irq(pdev, 0);
|
|
ret = devm_request_irq(&pdev->dev, irq,
|
|
mmp_tdma_int_handler, 0, "tdma", tdev);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
/* initialize channel parameters */
|
|
for (i = 0; i < chan_num; i++) {
|
|
irq = (irq_num != chan_num) ? 0 : platform_get_irq(pdev, i);
|
|
ret = mmp_tdma_chan_init(tdev, i, irq, type, pool);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
dma_cap_set(DMA_SLAVE, tdev->device.cap_mask);
|
|
dma_cap_set(DMA_CYCLIC, tdev->device.cap_mask);
|
|
tdev->device.dev = &pdev->dev;
|
|
tdev->device.device_alloc_chan_resources =
|
|
mmp_tdma_alloc_chan_resources;
|
|
tdev->device.device_free_chan_resources =
|
|
mmp_tdma_free_chan_resources;
|
|
tdev->device.device_prep_dma_cyclic = mmp_tdma_prep_dma_cyclic;
|
|
tdev->device.device_tx_status = mmp_tdma_tx_status;
|
|
tdev->device.device_issue_pending = mmp_tdma_issue_pending;
|
|
tdev->device.device_config = mmp_tdma_config;
|
|
tdev->device.device_pause = mmp_tdma_pause_chan;
|
|
tdev->device.device_resume = mmp_tdma_resume_chan;
|
|
tdev->device.device_terminate_all = mmp_tdma_terminate_all;
|
|
tdev->device.copy_align = DMAENGINE_ALIGN_8_BYTES;
|
|
|
|
dma_set_mask(&pdev->dev, DMA_BIT_MASK(64));
|
|
platform_set_drvdata(pdev, tdev);
|
|
|
|
ret = dmaenginem_async_device_register(&tdev->device);
|
|
if (ret) {
|
|
dev_err(tdev->device.dev, "unable to register\n");
|
|
return ret;
|
|
}
|
|
|
|
if (pdev->dev.of_node) {
|
|
ret = of_dma_controller_register(pdev->dev.of_node,
|
|
mmp_tdma_xlate, tdev);
|
|
if (ret) {
|
|
dev_err(tdev->device.dev,
|
|
"failed to register controller\n");
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
dev_info(tdev->device.dev, "initialized\n");
|
|
return 0;
|
|
}
|
|
|
|
static const struct platform_device_id mmp_tdma_id_table[] = {
|
|
{ "mmp-adma", MMP_AUD_TDMA },
|
|
{ "pxa910-squ", PXA910_SQU },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver mmp_tdma_driver = {
|
|
.driver = {
|
|
.name = "mmp-tdma",
|
|
.of_match_table = mmp_tdma_dt_ids,
|
|
},
|
|
.id_table = mmp_tdma_id_table,
|
|
.probe = mmp_tdma_probe,
|
|
.remove = mmp_tdma_remove,
|
|
};
|
|
|
|
module_platform_driver(mmp_tdma_driver);
|
|
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("MMP Two-Channel DMA Driver");
|
|
MODULE_ALIAS("platform:mmp-tdma");
|
|
MODULE_AUTHOR("Leo Yan <leoy@marvell.com>");
|
|
MODULE_AUTHOR("Zhangfei Gao <zhangfei.gao@marvell.com>");
|