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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 19:29:37 +00:00
![Nikita Shubin](/assets/img/avatar_default.png)
commit28dc10eb77
upstream. Fixes the following warnings which results in interrupts disabled on port B/F: gpio gpiochip1: (B): detected irqchip that is shared with multiple gpiochips: please fix the driver. gpio gpiochip5: (F): detected irqchip that is shared with multiple gpiochips: please fix the driver. - added separate irqchip for each interrupt capable gpiochip - provided unique names for each irqchip Fixes:d2b0919615
("gpio: ep93xx: Pass irqchip when adding gpiochip") Cc: <stable@vger.kernel.org> Signed-off-by: Nikita Shubin <nikita.shubin@maquefel.me> Tested-by: Alexander Sverdlin <alexander.sverdlin@gmail.com> Signed-off-by: Bartosz Golaszewski <bgolaszewski@baylibre.com> Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
465 lines
13 KiB
C
465 lines
13 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* Generic EP93xx GPIO handling
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*
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* Copyright (c) 2008 Ryan Mallon
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* Copyright (c) 2011 H Hartley Sweeten <hsweeten@visionengravers.com>
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*
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* Based on code originally from:
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* linux/arch/arm/mach-ep93xx/core.c
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/platform_device.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/slab.h>
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#include <linux/gpio/driver.h>
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#include <linux/bitops.h>
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#define EP93XX_GPIO_F_INT_STATUS 0x5c
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#define EP93XX_GPIO_A_INT_STATUS 0xa0
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#define EP93XX_GPIO_B_INT_STATUS 0xbc
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/* Maximum value for gpio line identifiers */
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#define EP93XX_GPIO_LINE_MAX 63
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/* Number of GPIO chips in EP93XX */
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#define EP93XX_GPIO_CHIP_NUM 8
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/* Maximum value for irq capable line identifiers */
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#define EP93XX_GPIO_LINE_MAX_IRQ 23
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/*
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* Static mapping of GPIO bank F IRQS:
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* F0..F7 (16..24) to irq 80..87.
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*/
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#define EP93XX_GPIO_F_IRQ_BASE 80
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struct ep93xx_gpio_irq_chip {
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struct irq_chip ic;
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u8 irq_offset;
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u8 int_unmasked;
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u8 int_enabled;
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u8 int_type1;
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u8 int_type2;
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u8 int_debounce;
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};
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struct ep93xx_gpio_chip {
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struct gpio_chip gc;
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struct ep93xx_gpio_irq_chip *eic;
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};
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struct ep93xx_gpio {
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void __iomem *base;
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struct ep93xx_gpio_chip gc[EP93XX_GPIO_CHIP_NUM];
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};
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#define to_ep93xx_gpio_chip(x) container_of(x, struct ep93xx_gpio_chip, gc)
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static struct ep93xx_gpio_irq_chip *to_ep93xx_gpio_irq_chip(struct gpio_chip *gc)
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{
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struct ep93xx_gpio_chip *egc = to_ep93xx_gpio_chip(gc);
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return egc->eic;
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}
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/*************************************************************************
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* Interrupt handling for EP93xx on-chip GPIOs
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*************************************************************************/
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#define EP93XX_INT_TYPE1_OFFSET 0x00
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#define EP93XX_INT_TYPE2_OFFSET 0x04
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#define EP93XX_INT_EOI_OFFSET 0x08
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#define EP93XX_INT_EN_OFFSET 0x0c
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#define EP93XX_INT_STATUS_OFFSET 0x10
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#define EP93XX_INT_RAW_STATUS_OFFSET 0x14
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#define EP93XX_INT_DEBOUNCE_OFFSET 0x18
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static void ep93xx_gpio_update_int_params(struct ep93xx_gpio *epg,
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struct ep93xx_gpio_irq_chip *eic)
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{
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writeb_relaxed(0, epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
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writeb_relaxed(eic->int_type2,
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epg->base + eic->irq_offset + EP93XX_INT_TYPE2_OFFSET);
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writeb_relaxed(eic->int_type1,
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epg->base + eic->irq_offset + EP93XX_INT_TYPE1_OFFSET);
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writeb_relaxed(eic->int_unmasked & eic->int_enabled,
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epg->base + eic->irq_offset + EP93XX_INT_EN_OFFSET);
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}
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static void ep93xx_gpio_int_debounce(struct gpio_chip *gc,
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unsigned int offset, bool enable)
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{
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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int port_mask = BIT(offset);
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if (enable)
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eic->int_debounce |= port_mask;
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else
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eic->int_debounce &= ~port_mask;
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writeb(eic->int_debounce,
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epg->base + eic->irq_offset + EP93XX_INT_DEBOUNCE_OFFSET);
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}
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static void ep93xx_gpio_ab_irq_handler(struct irq_desc *desc)
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{
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struct gpio_chip *gc = irq_desc_get_handler_data(desc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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unsigned long stat;
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int offset;
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chained_irq_enter(irqchip, desc);
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/*
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* Dispatch the IRQs to the irqdomain of each A and B
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* gpiochip irqdomains depending on what has fired.
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* The tricky part is that the IRQ line is shared
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* between bank A and B and each has their own gpiochip.
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*/
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stat = readb(epg->base + EP93XX_GPIO_A_INT_STATUS);
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for_each_set_bit(offset, &stat, 8)
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generic_handle_irq(irq_find_mapping(epg->gc[0].gc.irq.domain,
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offset));
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stat = readb(epg->base + EP93XX_GPIO_B_INT_STATUS);
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for_each_set_bit(offset, &stat, 8)
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generic_handle_irq(irq_find_mapping(epg->gc[1].gc.irq.domain,
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offset));
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chained_irq_exit(irqchip, desc);
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}
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static void ep93xx_gpio_f_irq_handler(struct irq_desc *desc)
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{
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/*
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* map discontiguous hw irq range to continuous sw irq range:
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*
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* IRQ_EP93XX_GPIO{0..7}MUX -> EP93XX_GPIO_LINE_F{0..7}
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*/
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struct irq_chip *irqchip = irq_desc_get_chip(desc);
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unsigned int irq = irq_desc_get_irq(desc);
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int port_f_idx = ((irq + 1) & 7) ^ 4; /* {19..22,47..50} -> {0..7} */
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int gpio_irq = EP93XX_GPIO_F_IRQ_BASE + port_f_idx;
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chained_irq_enter(irqchip, desc);
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generic_handle_irq(gpio_irq);
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chained_irq_exit(irqchip, desc);
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}
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static void ep93xx_gpio_irq_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port_mask = BIT(d->irq & 7);
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if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH) {
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eic->int_type2 ^= port_mask; /* switch edge direction */
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ep93xx_gpio_update_int_params(epg, eic);
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}
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writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
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}
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static void ep93xx_gpio_irq_mask_ack(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int port_mask = BIT(d->irq & 7);
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if (irqd_get_trigger_type(d) == IRQ_TYPE_EDGE_BOTH)
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eic->int_type2 ^= port_mask; /* switch edge direction */
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eic->int_unmasked &= ~port_mask;
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ep93xx_gpio_update_int_params(epg, eic);
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writeb(port_mask, epg->base + eic->irq_offset + EP93XX_INT_EOI_OFFSET);
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}
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static void ep93xx_gpio_irq_mask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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eic->int_unmasked &= ~BIT(d->irq & 7);
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ep93xx_gpio_update_int_params(epg, eic);
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}
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static void ep93xx_gpio_irq_unmask(struct irq_data *d)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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eic->int_unmasked |= BIT(d->irq & 7);
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ep93xx_gpio_update_int_params(epg, eic);
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}
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/*
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* gpio_int_type1 controls whether the interrupt is level (0) or
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* edge (1) triggered, while gpio_int_type2 controls whether it
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* triggers on low/falling (0) or high/rising (1).
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*/
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static int ep93xx_gpio_irq_type(struct irq_data *d, unsigned int type)
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{
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struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
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struct ep93xx_gpio_irq_chip *eic = to_ep93xx_gpio_irq_chip(gc);
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struct ep93xx_gpio *epg = gpiochip_get_data(gc);
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int offset = d->irq & 7;
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int port_mask = BIT(offset);
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irq_flow_handler_t handler;
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gc->direction_input(gc, offset);
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switch (type) {
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case IRQ_TYPE_EDGE_RISING:
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eic->int_type1 |= port_mask;
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eic->int_type2 |= port_mask;
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_EDGE_FALLING:
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eic->int_type1 |= port_mask;
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eic->int_type2 &= ~port_mask;
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handler = handle_edge_irq;
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break;
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case IRQ_TYPE_LEVEL_HIGH:
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eic->int_type1 &= ~port_mask;
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eic->int_type2 |= port_mask;
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handler = handle_level_irq;
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break;
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case IRQ_TYPE_LEVEL_LOW:
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eic->int_type1 &= ~port_mask;
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eic->int_type2 &= ~port_mask;
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handler = handle_level_irq;
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break;
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case IRQ_TYPE_EDGE_BOTH:
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eic->int_type1 |= port_mask;
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/* set initial polarity based on current input level */
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if (gc->get(gc, offset))
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eic->int_type2 &= ~port_mask; /* falling */
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else
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eic->int_type2 |= port_mask; /* rising */
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handler = handle_edge_irq;
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break;
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default:
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return -EINVAL;
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}
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irq_set_handler_locked(d, handler);
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eic->int_enabled |= port_mask;
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ep93xx_gpio_update_int_params(epg, eic);
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return 0;
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}
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/*************************************************************************
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* gpiolib interface for EP93xx on-chip GPIOs
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*************************************************************************/
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struct ep93xx_gpio_bank {
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const char *label;
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int data;
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int dir;
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int irq;
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int base;
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bool has_irq;
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bool has_hierarchical_irq;
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unsigned int irq_base;
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};
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#define EP93XX_GPIO_BANK(_label, _data, _dir, _irq, _base, _has_irq, _has_hier, _irq_base) \
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{ \
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.label = _label, \
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.data = _data, \
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.dir = _dir, \
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.irq = _irq, \
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.base = _base, \
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.has_irq = _has_irq, \
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.has_hierarchical_irq = _has_hier, \
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.irq_base = _irq_base, \
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}
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static struct ep93xx_gpio_bank ep93xx_gpio_banks[] = {
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/* Bank A has 8 IRQs */
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EP93XX_GPIO_BANK("A", 0x00, 0x10, 0x90, 0, true, false, 64),
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/* Bank B has 8 IRQs */
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EP93XX_GPIO_BANK("B", 0x04, 0x14, 0xac, 8, true, false, 72),
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EP93XX_GPIO_BANK("C", 0x08, 0x18, 0x00, 40, false, false, 0),
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EP93XX_GPIO_BANK("D", 0x0c, 0x1c, 0x00, 24, false, false, 0),
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EP93XX_GPIO_BANK("E", 0x20, 0x24, 0x00, 32, false, false, 0),
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/* Bank F has 8 IRQs */
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EP93XX_GPIO_BANK("F", 0x30, 0x34, 0x4c, 16, false, true, 0),
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EP93XX_GPIO_BANK("G", 0x38, 0x3c, 0x00, 48, false, false, 0),
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EP93XX_GPIO_BANK("H", 0x40, 0x44, 0x00, 56, false, false, 0),
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};
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static int ep93xx_gpio_set_config(struct gpio_chip *gc, unsigned offset,
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unsigned long config)
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{
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u32 debounce;
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if (pinconf_to_config_param(config) != PIN_CONFIG_INPUT_DEBOUNCE)
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return -ENOTSUPP;
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debounce = pinconf_to_config_argument(config);
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ep93xx_gpio_int_debounce(gc, offset, debounce ? true : false);
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return 0;
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}
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static int ep93xx_gpio_f_to_irq(struct gpio_chip *gc, unsigned offset)
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{
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return EP93XX_GPIO_F_IRQ_BASE + offset;
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}
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static void ep93xx_init_irq_chip(struct device *dev, struct irq_chip *ic)
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{
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ic->irq_ack = ep93xx_gpio_irq_ack;
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ic->irq_mask_ack = ep93xx_gpio_irq_mask_ack;
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ic->irq_mask = ep93xx_gpio_irq_mask;
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ic->irq_unmask = ep93xx_gpio_irq_unmask;
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ic->irq_set_type = ep93xx_gpio_irq_type;
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}
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static int ep93xx_gpio_add_bank(struct ep93xx_gpio_chip *egc,
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struct platform_device *pdev,
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struct ep93xx_gpio *epg,
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struct ep93xx_gpio_bank *bank)
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{
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void __iomem *data = epg->base + bank->data;
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void __iomem *dir = epg->base + bank->dir;
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struct gpio_chip *gc = &egc->gc;
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struct device *dev = &pdev->dev;
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struct gpio_irq_chip *girq;
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int err;
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err = bgpio_init(gc, dev, 1, data, NULL, NULL, dir, NULL, 0);
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if (err)
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return err;
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gc->label = bank->label;
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gc->base = bank->base;
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girq = &gc->irq;
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if (bank->has_irq || bank->has_hierarchical_irq) {
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struct irq_chip *ic;
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gc->set_config = ep93xx_gpio_set_config;
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egc->eic = devm_kcalloc(dev, 1,
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sizeof(*egc->eic),
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GFP_KERNEL);
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if (!egc->eic)
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return -ENOMEM;
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egc->eic->irq_offset = bank->irq;
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ic = &egc->eic->ic;
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ic->name = devm_kasprintf(dev, GFP_KERNEL, "gpio-irq-%s", bank->label);
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if (!ic->name)
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return -ENOMEM;
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ep93xx_init_irq_chip(dev, ic);
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girq->chip = ic;
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}
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if (bank->has_irq) {
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int ab_parent_irq = platform_get_irq(pdev, 0);
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girq->parent_handler = ep93xx_gpio_ab_irq_handler;
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girq->num_parents = 1;
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girq->parents = devm_kcalloc(dev, 1,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_level_irq;
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girq->parents[0] = ab_parent_irq;
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girq->first = bank->irq_base;
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}
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/* Only bank F has especially funky IRQ handling */
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if (bank->has_hierarchical_irq) {
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int gpio_irq;
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int i;
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/*
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* FIXME: convert this to use hierarchical IRQ support!
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* this requires fixing the root irqchip to be hierarchial.
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*/
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girq->parent_handler = ep93xx_gpio_f_irq_handler;
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girq->num_parents = 8;
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girq->parents = devm_kcalloc(dev, 8,
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sizeof(*girq->parents),
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GFP_KERNEL);
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if (!girq->parents)
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return -ENOMEM;
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/* Pick resources 1..8 for these IRQs */
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for (i = 1; i <= 8; i++)
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girq->parents[i - 1] = platform_get_irq(pdev, i);
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for (i = 0; i < 8; i++) {
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gpio_irq = EP93XX_GPIO_F_IRQ_BASE + i;
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irq_set_chip_data(gpio_irq, &epg->gc[5]);
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irq_set_chip_and_handler(gpio_irq,
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girq->chip,
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handle_level_irq);
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irq_clear_status_flags(gpio_irq, IRQ_NOREQUEST);
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}
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girq->default_type = IRQ_TYPE_NONE;
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girq->handler = handle_level_irq;
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gc->to_irq = ep93xx_gpio_f_to_irq;
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}
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return devm_gpiochip_add_data(dev, gc, epg);
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}
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static int ep93xx_gpio_probe(struct platform_device *pdev)
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{
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struct ep93xx_gpio *epg;
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int i;
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epg = devm_kzalloc(&pdev->dev, sizeof(*epg), GFP_KERNEL);
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if (!epg)
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return -ENOMEM;
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epg->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(epg->base))
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return PTR_ERR(epg->base);
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for (i = 0; i < ARRAY_SIZE(ep93xx_gpio_banks); i++) {
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struct ep93xx_gpio_chip *gc = &epg->gc[i];
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struct ep93xx_gpio_bank *bank = &ep93xx_gpio_banks[i];
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if (ep93xx_gpio_add_bank(gc, pdev, epg, bank))
|
|
dev_warn(&pdev->dev, "Unable to add gpio bank %s\n",
|
|
bank->label);
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver ep93xx_gpio_driver = {
|
|
.driver = {
|
|
.name = "gpio-ep93xx",
|
|
},
|
|
.probe = ep93xx_gpio_probe,
|
|
};
|
|
|
|
static int __init ep93xx_gpio_init(void)
|
|
{
|
|
return platform_driver_register(&ep93xx_gpio_driver);
|
|
}
|
|
postcore_initcall(ep93xx_gpio_init);
|
|
|
|
MODULE_AUTHOR("Ryan Mallon <ryan@bluewatersys.com> "
|
|
"H Hartley Sweeten <hsweeten@visionengravers.com>");
|
|
MODULE_DESCRIPTION("EP93XX GPIO driver");
|
|
MODULE_LICENSE("GPL");
|