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![Enrico Weigelt, metux IT consult](/assets/img/avatar_default.png)
Use the new helper that wraps the calls to platform_get_resource() and devm_ioremap_resource() together. Signed-off-by: Enrico Weigelt, metux IT consult <info@metux.net> Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
197 lines
5.2 KiB
C
197 lines
5.2 KiB
C
/*
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* SPEAr platform SPI chipselect abstraction over gpiolib
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*
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* Copyright (C) 2012 ST Microelectronics
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* Shiraz Hashim <shiraz.linux.kernel@gmail.com>
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*
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* This file is licensed under the terms of the GNU General Public
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* License version 2. This program is licensed "as is" without any
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* warranty of any kind, whether express or implied.
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*/
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#include <linux/err.h>
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#include <linux/gpio/driver.h>
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#include <linux/io.h>
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#include <linux/init.h>
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#include <linux/of.h>
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#include <linux/platform_device.h>
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#include <linux/types.h>
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/* maximum chipselects */
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#define NUM_OF_GPIO 4
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/*
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* Provision is available on some SPEAr SoCs to control ARM PL022 spi cs
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* through system registers. This register lies outside spi (pl022)
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* address space into system registers.
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*
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* It provides control for spi chip select lines so that any chipselect
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* (out of 4 possible chipselects in pl022) can be made low to select
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* the particular slave.
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*/
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/**
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* struct spear_spics - represents spi chip select control
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* @base: base address
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* @perip_cfg: configuration register
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* @sw_enable_bit: bit to enable s/w control over chipselects
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* @cs_value_bit: bit to program high or low chipselect
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* @cs_enable_mask: mask to select bits required to select chipselect
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* @cs_enable_shift: bit pos of cs_enable_mask
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* @use_count: use count of a spi controller cs lines
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* @last_off: stores last offset caller of set_value()
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* @chip: gpio_chip abstraction
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*/
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struct spear_spics {
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void __iomem *base;
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u32 perip_cfg;
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u32 sw_enable_bit;
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u32 cs_value_bit;
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u32 cs_enable_mask;
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u32 cs_enable_shift;
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unsigned long use_count;
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int last_off;
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struct gpio_chip chip;
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};
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/* gpio framework specific routines */
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static int spics_get_value(struct gpio_chip *chip, unsigned offset)
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{
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return -ENXIO;
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}
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static void spics_set_value(struct gpio_chip *chip, unsigned offset, int value)
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{
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struct spear_spics *spics = gpiochip_get_data(chip);
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u32 tmp;
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/* select chip select from register */
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tmp = readl_relaxed(spics->base + spics->perip_cfg);
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if (spics->last_off != offset) {
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spics->last_off = offset;
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tmp &= ~(spics->cs_enable_mask << spics->cs_enable_shift);
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tmp |= offset << spics->cs_enable_shift;
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}
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/* toggle chip select line */
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tmp &= ~(0x1 << spics->cs_value_bit);
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tmp |= value << spics->cs_value_bit;
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writel_relaxed(tmp, spics->base + spics->perip_cfg);
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}
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static int spics_direction_input(struct gpio_chip *chip, unsigned offset)
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{
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return -ENXIO;
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}
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static int spics_direction_output(struct gpio_chip *chip, unsigned offset,
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int value)
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{
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spics_set_value(chip, offset, value);
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return 0;
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}
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static int spics_request(struct gpio_chip *chip, unsigned offset)
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{
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struct spear_spics *spics = gpiochip_get_data(chip);
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u32 tmp;
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if (!spics->use_count++) {
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tmp = readl_relaxed(spics->base + spics->perip_cfg);
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tmp |= 0x1 << spics->sw_enable_bit;
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tmp |= 0x1 << spics->cs_value_bit;
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writel_relaxed(tmp, spics->base + spics->perip_cfg);
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}
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return 0;
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}
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static void spics_free(struct gpio_chip *chip, unsigned offset)
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{
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struct spear_spics *spics = gpiochip_get_data(chip);
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u32 tmp;
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if (!--spics->use_count) {
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tmp = readl_relaxed(spics->base + spics->perip_cfg);
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tmp &= ~(0x1 << spics->sw_enable_bit);
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writel_relaxed(tmp, spics->base + spics->perip_cfg);
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}
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}
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static int spics_gpio_probe(struct platform_device *pdev)
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{
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struct device_node *np = pdev->dev.of_node;
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struct spear_spics *spics;
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int ret;
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spics = devm_kzalloc(&pdev->dev, sizeof(*spics), GFP_KERNEL);
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if (!spics)
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return -ENOMEM;
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spics->base = devm_platform_ioremap_resource(pdev, 0);
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if (IS_ERR(spics->base))
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return PTR_ERR(spics->base);
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if (of_property_read_u32(np, "st-spics,peripcfg-reg",
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&spics->perip_cfg))
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goto err_dt_data;
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if (of_property_read_u32(np, "st-spics,sw-enable-bit",
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&spics->sw_enable_bit))
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goto err_dt_data;
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if (of_property_read_u32(np, "st-spics,cs-value-bit",
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&spics->cs_value_bit))
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goto err_dt_data;
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if (of_property_read_u32(np, "st-spics,cs-enable-mask",
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&spics->cs_enable_mask))
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goto err_dt_data;
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if (of_property_read_u32(np, "st-spics,cs-enable-shift",
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&spics->cs_enable_shift))
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goto err_dt_data;
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platform_set_drvdata(pdev, spics);
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spics->chip.ngpio = NUM_OF_GPIO;
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spics->chip.base = -1;
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spics->chip.request = spics_request;
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spics->chip.free = spics_free;
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spics->chip.direction_input = spics_direction_input;
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spics->chip.direction_output = spics_direction_output;
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spics->chip.get = spics_get_value;
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spics->chip.set = spics_set_value;
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spics->chip.label = dev_name(&pdev->dev);
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spics->chip.parent = &pdev->dev;
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spics->chip.owner = THIS_MODULE;
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spics->last_off = -1;
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ret = devm_gpiochip_add_data(&pdev->dev, &spics->chip, spics);
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if (ret) {
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dev_err(&pdev->dev, "unable to add gpio chip\n");
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return ret;
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}
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dev_info(&pdev->dev, "spear spics registered\n");
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return 0;
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err_dt_data:
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dev_err(&pdev->dev, "DT probe failed\n");
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return -EINVAL;
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}
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static const struct of_device_id spics_gpio_of_match[] = {
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{ .compatible = "st,spear-spics-gpio" },
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{}
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};
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static struct platform_driver spics_gpio_driver = {
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.probe = spics_gpio_probe,
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.driver = {
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.name = "spear-spics-gpio",
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.of_match_table = spics_gpio_of_match,
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},
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};
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static int __init spics_gpio_init(void)
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{
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return platform_driver_register(&spics_gpio_driver);
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}
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subsys_initcall(spics_gpio_init);
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