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![Zhang Qilong](/assets/img/avatar_default.png)
[ Upstream commita247230500
] If the pm_runtime_get_sync failed in q6v5_pds_enable when loop (i), The unroll_pd_votes will start from (i - 1), and it will resulted in following problems: 1) pm_runtime_get_sync will increment pm usage counter even it failed. Forgetting to pm_runtime_put_noidle will result in reference leak. 2) Have not reset pds[i] performance state. Then we fix it. Fixes:4760a896be
("remoteproc: q6v5-mss: Vote for rpmh power domains") Signed-off-by: Zhang Qilong <zhangqilong3@huawei.com> Link: https://lore.kernel.org/r/20201102143433.143996-1-zhangqilong3@huawei.com Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org> Signed-off-by: Sasha Levin <sashal@kernel.org>
1743 lines
41 KiB
C
1743 lines
41 KiB
C
// SPDX-License-Identifier: GPL-2.0-only
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/*
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* Qualcomm self-authenticating modem subsystem remoteproc driver
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*
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* Copyright (C) 2016 Linaro Ltd.
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* Copyright (C) 2014 Sony Mobile Communications AB
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* Copyright (c) 2012-2013, The Linux Foundation. All rights reserved.
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*/
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/dma-mapping.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/module.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/pm_domain.h>
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#include <linux/pm_runtime.h>
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#include <linux/regmap.h>
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#include <linux/regulator/consumer.h>
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#include <linux/remoteproc.h>
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#include <linux/reset.h>
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#include <linux/soc/qcom/mdt_loader.h>
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#include <linux/iopoll.h>
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#include "remoteproc_internal.h"
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#include "qcom_common.h"
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#include "qcom_q6v5.h"
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#include <linux/qcom_scm.h>
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#define MPSS_CRASH_REASON_SMEM 421
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/* RMB Status Register Values */
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#define RMB_PBL_SUCCESS 0x1
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#define RMB_MBA_XPU_UNLOCKED 0x1
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#define RMB_MBA_XPU_UNLOCKED_SCRIBBLED 0x2
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#define RMB_MBA_META_DATA_AUTH_SUCCESS 0x3
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#define RMB_MBA_AUTH_COMPLETE 0x4
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/* PBL/MBA interface registers */
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#define RMB_MBA_IMAGE_REG 0x00
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#define RMB_PBL_STATUS_REG 0x04
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#define RMB_MBA_COMMAND_REG 0x08
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#define RMB_MBA_STATUS_REG 0x0C
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#define RMB_PMI_META_DATA_REG 0x10
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#define RMB_PMI_CODE_START_REG 0x14
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#define RMB_PMI_CODE_LENGTH_REG 0x18
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#define RMB_MBA_MSS_STATUS 0x40
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#define RMB_MBA_ALT_RESET 0x44
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#define RMB_CMD_META_DATA_READY 0x1
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#define RMB_CMD_LOAD_READY 0x2
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/* QDSP6SS Register Offsets */
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#define QDSP6SS_RESET_REG 0x014
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#define QDSP6SS_GFMUX_CTL_REG 0x020
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#define QDSP6SS_PWR_CTL_REG 0x030
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#define QDSP6SS_MEM_PWR_CTL 0x0B0
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#define QDSP6SS_STRAP_ACC 0x110
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/* AXI Halt Register Offsets */
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#define AXI_HALTREQ_REG 0x0
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#define AXI_HALTACK_REG 0x4
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#define AXI_IDLE_REG 0x8
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#define HALT_ACK_TIMEOUT_MS 100
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/* QDSP6SS_RESET */
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#define Q6SS_STOP_CORE BIT(0)
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#define Q6SS_CORE_ARES BIT(1)
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#define Q6SS_BUS_ARES_ENABLE BIT(2)
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/* QDSP6SS_GFMUX_CTL */
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#define Q6SS_CLK_ENABLE BIT(1)
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/* QDSP6SS_PWR_CTL */
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#define Q6SS_L2DATA_SLP_NRET_N_0 BIT(0)
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#define Q6SS_L2DATA_SLP_NRET_N_1 BIT(1)
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#define Q6SS_L2DATA_SLP_NRET_N_2 BIT(2)
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#define Q6SS_L2TAG_SLP_NRET_N BIT(16)
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#define Q6SS_ETB_SLP_NRET_N BIT(17)
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#define Q6SS_L2DATA_STBY_N BIT(18)
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#define Q6SS_SLP_RET_N BIT(19)
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#define Q6SS_CLAMP_IO BIT(20)
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#define QDSS_BHS_ON BIT(21)
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#define QDSS_LDO_BYP BIT(22)
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/* QDSP6v56 parameters */
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#define QDSP6v56_LDO_BYP BIT(25)
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#define QDSP6v56_BHS_ON BIT(24)
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#define QDSP6v56_CLAMP_WL BIT(21)
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#define QDSP6v56_CLAMP_QMC_MEM BIT(22)
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#define HALT_CHECK_MAX_LOOPS 200
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#define QDSP6SS_XO_CBCR 0x0038
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#define QDSP6SS_ACC_OVERRIDE_VAL 0x20
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/* QDSP6v65 parameters */
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#define QDSP6SS_SLEEP 0x3C
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#define QDSP6SS_BOOT_CORE_START 0x400
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#define QDSP6SS_BOOT_CMD 0x404
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#define SLEEP_CHECK_MAX_LOOPS 200
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#define BOOT_FSM_TIMEOUT 10000
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struct reg_info {
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struct regulator *reg;
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int uV;
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int uA;
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};
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struct qcom_mss_reg_res {
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const char *supply;
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int uV;
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int uA;
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};
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struct rproc_hexagon_res {
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const char *hexagon_mba_image;
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struct qcom_mss_reg_res *proxy_supply;
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struct qcom_mss_reg_res *active_supply;
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char **proxy_clk_names;
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char **reset_clk_names;
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char **active_clk_names;
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char **active_pd_names;
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char **proxy_pd_names;
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int version;
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bool need_mem_protection;
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bool has_alt_reset;
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};
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struct q6v5 {
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struct device *dev;
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struct rproc *rproc;
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void __iomem *reg_base;
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void __iomem *rmb_base;
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struct regmap *halt_map;
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u32 halt_q6;
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u32 halt_modem;
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u32 halt_nc;
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struct reset_control *mss_restart;
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struct reset_control *pdc_reset;
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struct qcom_q6v5 q6v5;
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struct clk *active_clks[8];
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struct clk *reset_clks[4];
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struct clk *proxy_clks[4];
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struct device *active_pds[1];
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struct device *proxy_pds[3];
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int active_clk_count;
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int reset_clk_count;
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int proxy_clk_count;
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int active_pd_count;
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int proxy_pd_count;
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struct reg_info active_regs[1];
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struct reg_info proxy_regs[3];
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int active_reg_count;
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int proxy_reg_count;
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bool running;
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bool dump_mba_loaded;
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unsigned long dump_segment_mask;
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unsigned long dump_complete_mask;
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phys_addr_t mba_phys;
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void *mba_region;
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size_t mba_size;
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phys_addr_t mpss_phys;
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phys_addr_t mpss_reloc;
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void *mpss_region;
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size_t mpss_size;
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struct qcom_rproc_glink glink_subdev;
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struct qcom_rproc_subdev smd_subdev;
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struct qcom_rproc_ssr ssr_subdev;
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struct qcom_sysmon *sysmon;
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bool need_mem_protection;
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bool has_alt_reset;
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int mpss_perm;
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int mba_perm;
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const char *hexagon_mdt_image;
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int version;
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};
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enum {
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MSS_MSM8916,
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MSS_MSM8974,
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MSS_MSM8996,
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MSS_SDM845,
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};
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static int q6v5_regulator_init(struct device *dev, struct reg_info *regs,
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const struct qcom_mss_reg_res *reg_res)
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{
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int rc;
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int i;
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if (!reg_res)
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return 0;
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for (i = 0; reg_res[i].supply; i++) {
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regs[i].reg = devm_regulator_get(dev, reg_res[i].supply);
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if (IS_ERR(regs[i].reg)) {
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rc = PTR_ERR(regs[i].reg);
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if (rc != -EPROBE_DEFER)
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dev_err(dev, "Failed to get %s\n regulator",
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reg_res[i].supply);
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return rc;
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}
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regs[i].uV = reg_res[i].uV;
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regs[i].uA = reg_res[i].uA;
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}
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return i;
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}
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static int q6v5_regulator_enable(struct q6v5 *qproc,
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struct reg_info *regs, int count)
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{
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int ret;
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int i;
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for (i = 0; i < count; i++) {
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if (regs[i].uV > 0) {
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ret = regulator_set_voltage(regs[i].reg,
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regs[i].uV, INT_MAX);
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if (ret) {
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dev_err(qproc->dev,
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"Failed to request voltage for %d.\n",
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i);
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goto err;
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}
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}
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if (regs[i].uA > 0) {
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ret = regulator_set_load(regs[i].reg,
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regs[i].uA);
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if (ret < 0) {
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dev_err(qproc->dev,
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"Failed to set regulator mode\n");
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goto err;
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}
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}
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ret = regulator_enable(regs[i].reg);
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if (ret) {
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dev_err(qproc->dev, "Regulator enable failed\n");
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goto err;
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}
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}
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return 0;
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err:
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for (; i >= 0; i--) {
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if (regs[i].uV > 0)
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regulator_set_voltage(regs[i].reg, 0, INT_MAX);
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if (regs[i].uA > 0)
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regulator_set_load(regs[i].reg, 0);
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regulator_disable(regs[i].reg);
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}
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return ret;
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}
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static void q6v5_regulator_disable(struct q6v5 *qproc,
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struct reg_info *regs, int count)
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{
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int i;
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for (i = 0; i < count; i++) {
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if (regs[i].uV > 0)
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regulator_set_voltage(regs[i].reg, 0, INT_MAX);
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if (regs[i].uA > 0)
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regulator_set_load(regs[i].reg, 0);
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regulator_disable(regs[i].reg);
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}
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}
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static int q6v5_clk_enable(struct device *dev,
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struct clk **clks, int count)
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{
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int rc;
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int i;
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for (i = 0; i < count; i++) {
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rc = clk_prepare_enable(clks[i]);
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if (rc) {
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dev_err(dev, "Clock enable failed\n");
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goto err;
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}
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}
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return 0;
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err:
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for (i--; i >= 0; i--)
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clk_disable_unprepare(clks[i]);
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return rc;
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}
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static void q6v5_clk_disable(struct device *dev,
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struct clk **clks, int count)
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{
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int i;
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for (i = 0; i < count; i++)
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clk_disable_unprepare(clks[i]);
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}
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static int q6v5_pds_enable(struct q6v5 *qproc, struct device **pds,
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size_t pd_count)
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{
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int ret;
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int i;
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for (i = 0; i < pd_count; i++) {
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dev_pm_genpd_set_performance_state(pds[i], INT_MAX);
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ret = pm_runtime_get_sync(pds[i]);
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if (ret < 0) {
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pm_runtime_put_noidle(pds[i]);
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dev_pm_genpd_set_performance_state(pds[i], 0);
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goto unroll_pd_votes;
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}
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}
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return 0;
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unroll_pd_votes:
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for (i--; i >= 0; i--) {
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dev_pm_genpd_set_performance_state(pds[i], 0);
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pm_runtime_put(pds[i]);
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}
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return ret;
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};
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static void q6v5_pds_disable(struct q6v5 *qproc, struct device **pds,
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size_t pd_count)
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{
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int i;
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for (i = 0; i < pd_count; i++) {
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dev_pm_genpd_set_performance_state(pds[i], 0);
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pm_runtime_put(pds[i]);
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}
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}
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static int q6v5_xfer_mem_ownership(struct q6v5 *qproc, int *current_perm,
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bool remote_owner, phys_addr_t addr,
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size_t size)
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{
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struct qcom_scm_vmperm next;
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if (!qproc->need_mem_protection)
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return 0;
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if (remote_owner && *current_perm == BIT(QCOM_SCM_VMID_MSS_MSA))
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return 0;
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if (!remote_owner && *current_perm == BIT(QCOM_SCM_VMID_HLOS))
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return 0;
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next.vmid = remote_owner ? QCOM_SCM_VMID_MSS_MSA : QCOM_SCM_VMID_HLOS;
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next.perm = remote_owner ? QCOM_SCM_PERM_RW : QCOM_SCM_PERM_RWX;
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return qcom_scm_assign_mem(addr, ALIGN(size, SZ_4K),
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current_perm, &next, 1);
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}
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static int q6v5_load(struct rproc *rproc, const struct firmware *fw)
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{
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struct q6v5 *qproc = rproc->priv;
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/* MBA is restricted to a maximum size of 1M */
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if (fw->size > qproc->mba_size || fw->size > SZ_1M) {
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dev_err(qproc->dev, "MBA firmware load failed\n");
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return -EINVAL;
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}
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memcpy(qproc->mba_region, fw->data, fw->size);
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return 0;
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}
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static int q6v5_reset_assert(struct q6v5 *qproc)
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{
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int ret;
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if (qproc->has_alt_reset) {
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reset_control_assert(qproc->pdc_reset);
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ret = reset_control_reset(qproc->mss_restart);
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reset_control_deassert(qproc->pdc_reset);
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} else {
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ret = reset_control_assert(qproc->mss_restart);
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}
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return ret;
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}
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static int q6v5_reset_deassert(struct q6v5 *qproc)
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{
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int ret;
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if (qproc->has_alt_reset) {
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reset_control_assert(qproc->pdc_reset);
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writel(1, qproc->rmb_base + RMB_MBA_ALT_RESET);
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ret = reset_control_reset(qproc->mss_restart);
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writel(0, qproc->rmb_base + RMB_MBA_ALT_RESET);
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reset_control_deassert(qproc->pdc_reset);
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} else {
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ret = reset_control_deassert(qproc->mss_restart);
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}
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return ret;
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}
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static int q6v5_rmb_pbl_wait(struct q6v5 *qproc, int ms)
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{
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unsigned long timeout;
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s32 val;
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timeout = jiffies + msecs_to_jiffies(ms);
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for (;;) {
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val = readl(qproc->rmb_base + RMB_PBL_STATUS_REG);
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if (val)
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break;
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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msleep(1);
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}
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return val;
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}
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static int q6v5_rmb_mba_wait(struct q6v5 *qproc, u32 status, int ms)
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{
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unsigned long timeout;
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s32 val;
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timeout = jiffies + msecs_to_jiffies(ms);
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for (;;) {
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val = readl(qproc->rmb_base + RMB_MBA_STATUS_REG);
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if (val < 0)
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break;
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if (!status && val)
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break;
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else if (status && val == status)
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break;
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if (time_after(jiffies, timeout))
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return -ETIMEDOUT;
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msleep(1);
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}
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return val;
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}
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static int q6v5proc_reset(struct q6v5 *qproc)
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{
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u32 val;
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int ret;
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int i;
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if (qproc->version == MSS_SDM845) {
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val = readl(qproc->reg_base + QDSP6SS_SLEEP);
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val |= 0x1;
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writel(val, qproc->reg_base + QDSP6SS_SLEEP);
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ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_SLEEP,
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val, !(val & BIT(31)), 1,
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SLEEP_CHECK_MAX_LOOPS);
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if (ret) {
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dev_err(qproc->dev, "QDSP6SS Sleep clock timed out\n");
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return -ETIMEDOUT;
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}
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/* De-assert QDSP6 stop core */
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writel(1, qproc->reg_base + QDSP6SS_BOOT_CORE_START);
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/* Trigger boot FSM */
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writel(1, qproc->reg_base + QDSP6SS_BOOT_CMD);
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|
|
ret = readl_poll_timeout(qproc->rmb_base + RMB_MBA_MSS_STATUS,
|
|
val, (val & BIT(0)) != 0, 10, BOOT_FSM_TIMEOUT);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "Boot FSM failed to complete.\n");
|
|
/* Reset the modem so that boot FSM is in reset state */
|
|
q6v5_reset_deassert(qproc);
|
|
return ret;
|
|
}
|
|
|
|
goto pbl_wait;
|
|
} else if (qproc->version == MSS_MSM8996) {
|
|
/* Override the ACC value if required */
|
|
writel(QDSP6SS_ACC_OVERRIDE_VAL,
|
|
qproc->reg_base + QDSP6SS_STRAP_ACC);
|
|
|
|
/* Assert resets, stop core */
|
|
val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
|
|
val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
|
|
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
|
|
|
|
/* BHS require xo cbcr to be enabled */
|
|
val = readl(qproc->reg_base + QDSP6SS_XO_CBCR);
|
|
val |= 0x1;
|
|
writel(val, qproc->reg_base + QDSP6SS_XO_CBCR);
|
|
|
|
/* Read CLKOFF bit to go low indicating CLK is enabled */
|
|
ret = readl_poll_timeout(qproc->reg_base + QDSP6SS_XO_CBCR,
|
|
val, !(val & BIT(31)), 1,
|
|
HALT_CHECK_MAX_LOOPS);
|
|
if (ret) {
|
|
dev_err(qproc->dev,
|
|
"xo cbcr enabling timed out (rc:%d)\n", ret);
|
|
return ret;
|
|
}
|
|
/* Enable power block headswitch and wait for it to stabilize */
|
|
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= QDSP6v56_BHS_ON;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
udelay(1);
|
|
|
|
/* Put LDO in bypass mode */
|
|
val |= QDSP6v56_LDO_BYP;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
|
|
/* Deassert QDSP6 compiler memory clamp */
|
|
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val &= ~QDSP6v56_CLAMP_QMC_MEM;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
|
|
/* Deassert memory peripheral sleep and L2 memory standby */
|
|
val |= Q6SS_L2DATA_STBY_N | Q6SS_SLP_RET_N;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
|
|
/* Turn on L1, L2, ETB and JU memories 1 at a time */
|
|
val = readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
|
|
for (i = 19; i >= 0; i--) {
|
|
val |= BIT(i);
|
|
writel(val, qproc->reg_base +
|
|
QDSP6SS_MEM_PWR_CTL);
|
|
/*
|
|
* Read back value to ensure the write is done then
|
|
* wait for 1us for both memory peripheral and data
|
|
* array to turn on.
|
|
*/
|
|
val |= readl(qproc->reg_base + QDSP6SS_MEM_PWR_CTL);
|
|
udelay(1);
|
|
}
|
|
/* Remove word line clamp */
|
|
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val &= ~QDSP6v56_CLAMP_WL;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
} else {
|
|
/* Assert resets, stop core */
|
|
val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
|
|
val |= Q6SS_CORE_ARES | Q6SS_BUS_ARES_ENABLE | Q6SS_STOP_CORE;
|
|
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
|
|
|
|
/* Enable power block headswitch and wait for it to stabilize */
|
|
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= QDSS_BHS_ON | QDSS_LDO_BYP;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
udelay(1);
|
|
/*
|
|
* Turn on memories. L2 banks should be done individually
|
|
* to minimize inrush current.
|
|
*/
|
|
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= Q6SS_SLP_RET_N | Q6SS_L2TAG_SLP_NRET_N |
|
|
Q6SS_ETB_SLP_NRET_N | Q6SS_L2DATA_STBY_N;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= Q6SS_L2DATA_SLP_NRET_N_2;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= Q6SS_L2DATA_SLP_NRET_N_1;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= Q6SS_L2DATA_SLP_NRET_N_0;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
}
|
|
/* Remove IO clamp */
|
|
val &= ~Q6SS_CLAMP_IO;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
|
|
/* Bring core out of reset */
|
|
val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
|
|
val &= ~Q6SS_CORE_ARES;
|
|
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
|
|
|
|
/* Turn on core clock */
|
|
val = readl(qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
|
|
val |= Q6SS_CLK_ENABLE;
|
|
writel(val, qproc->reg_base + QDSP6SS_GFMUX_CTL_REG);
|
|
|
|
/* Start core execution */
|
|
val = readl(qproc->reg_base + QDSP6SS_RESET_REG);
|
|
val &= ~Q6SS_STOP_CORE;
|
|
writel(val, qproc->reg_base + QDSP6SS_RESET_REG);
|
|
|
|
pbl_wait:
|
|
/* Wait for PBL status */
|
|
ret = q6v5_rmb_pbl_wait(qproc, 1000);
|
|
if (ret == -ETIMEDOUT) {
|
|
dev_err(qproc->dev, "PBL boot timed out\n");
|
|
} else if (ret != RMB_PBL_SUCCESS) {
|
|
dev_err(qproc->dev, "PBL returned unexpected status %d\n", ret);
|
|
ret = -EINVAL;
|
|
} else {
|
|
ret = 0;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void q6v5proc_halt_axi_port(struct q6v5 *qproc,
|
|
struct regmap *halt_map,
|
|
u32 offset)
|
|
{
|
|
unsigned long timeout;
|
|
unsigned int val;
|
|
int ret;
|
|
|
|
/* Check if we're already idle */
|
|
ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
|
|
if (!ret && val)
|
|
return;
|
|
|
|
/* Assert halt request */
|
|
regmap_write(halt_map, offset + AXI_HALTREQ_REG, 1);
|
|
|
|
/* Wait for halt */
|
|
timeout = jiffies + msecs_to_jiffies(HALT_ACK_TIMEOUT_MS);
|
|
for (;;) {
|
|
ret = regmap_read(halt_map, offset + AXI_HALTACK_REG, &val);
|
|
if (ret || val || time_after(jiffies, timeout))
|
|
break;
|
|
|
|
msleep(1);
|
|
}
|
|
|
|
ret = regmap_read(halt_map, offset + AXI_IDLE_REG, &val);
|
|
if (ret || !val)
|
|
dev_err(qproc->dev, "port failed halt\n");
|
|
|
|
/* Clear halt request (port will remain halted until reset) */
|
|
regmap_write(halt_map, offset + AXI_HALTREQ_REG, 0);
|
|
}
|
|
|
|
static int q6v5_mpss_init_image(struct q6v5 *qproc, const struct firmware *fw)
|
|
{
|
|
unsigned long dma_attrs = DMA_ATTR_FORCE_CONTIGUOUS;
|
|
dma_addr_t phys;
|
|
void *metadata;
|
|
int mdata_perm;
|
|
int xferop_ret;
|
|
size_t size;
|
|
void *ptr;
|
|
int ret;
|
|
|
|
metadata = qcom_mdt_read_metadata(fw, &size);
|
|
if (IS_ERR(metadata))
|
|
return PTR_ERR(metadata);
|
|
|
|
ptr = dma_alloc_attrs(qproc->dev, size, &phys, GFP_KERNEL, dma_attrs);
|
|
if (!ptr) {
|
|
kfree(metadata);
|
|
dev_err(qproc->dev, "failed to allocate mdt buffer\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
memcpy(ptr, metadata, size);
|
|
|
|
/* Hypervisor mapping to access metadata by modem */
|
|
mdata_perm = BIT(QCOM_SCM_VMID_HLOS);
|
|
ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, true, phys, size);
|
|
if (ret) {
|
|
dev_err(qproc->dev,
|
|
"assigning Q6 access to metadata failed: %d\n", ret);
|
|
ret = -EAGAIN;
|
|
goto free_dma_attrs;
|
|
}
|
|
|
|
writel(phys, qproc->rmb_base + RMB_PMI_META_DATA_REG);
|
|
writel(RMB_CMD_META_DATA_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
|
|
|
|
ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_META_DATA_AUTH_SUCCESS, 1000);
|
|
if (ret == -ETIMEDOUT)
|
|
dev_err(qproc->dev, "MPSS header authentication timed out\n");
|
|
else if (ret < 0)
|
|
dev_err(qproc->dev, "MPSS header authentication failed: %d\n", ret);
|
|
|
|
/* Metadata authentication done, remove modem access */
|
|
xferop_ret = q6v5_xfer_mem_ownership(qproc, &mdata_perm, false, phys, size);
|
|
if (xferop_ret)
|
|
dev_warn(qproc->dev,
|
|
"mdt buffer not reclaimed system may become unstable\n");
|
|
|
|
free_dma_attrs:
|
|
dma_free_attrs(qproc->dev, size, ptr, phys, dma_attrs);
|
|
kfree(metadata);
|
|
|
|
return ret < 0 ? ret : 0;
|
|
}
|
|
|
|
static bool q6v5_phdr_valid(const struct elf32_phdr *phdr)
|
|
{
|
|
if (phdr->p_type != PT_LOAD)
|
|
return false;
|
|
|
|
if ((phdr->p_flags & QCOM_MDT_TYPE_MASK) == QCOM_MDT_TYPE_HASH)
|
|
return false;
|
|
|
|
if (!phdr->p_memsz)
|
|
return false;
|
|
|
|
return true;
|
|
}
|
|
|
|
static int q6v5_mba_load(struct q6v5 *qproc)
|
|
{
|
|
int ret;
|
|
int xfermemop_ret;
|
|
|
|
qcom_q6v5_prepare(&qproc->q6v5);
|
|
|
|
ret = q6v5_pds_enable(qproc, qproc->active_pds, qproc->active_pd_count);
|
|
if (ret < 0) {
|
|
dev_err(qproc->dev, "failed to enable active power domains\n");
|
|
goto disable_irqs;
|
|
}
|
|
|
|
ret = q6v5_pds_enable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
|
|
if (ret < 0) {
|
|
dev_err(qproc->dev, "failed to enable proxy power domains\n");
|
|
goto disable_active_pds;
|
|
}
|
|
|
|
ret = q6v5_regulator_enable(qproc, qproc->proxy_regs,
|
|
qproc->proxy_reg_count);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "failed to enable proxy supplies\n");
|
|
goto disable_proxy_pds;
|
|
}
|
|
|
|
ret = q6v5_clk_enable(qproc->dev, qproc->proxy_clks,
|
|
qproc->proxy_clk_count);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "failed to enable proxy clocks\n");
|
|
goto disable_proxy_reg;
|
|
}
|
|
|
|
ret = q6v5_regulator_enable(qproc, qproc->active_regs,
|
|
qproc->active_reg_count);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "failed to enable supplies\n");
|
|
goto disable_proxy_clk;
|
|
}
|
|
|
|
ret = q6v5_clk_enable(qproc->dev, qproc->reset_clks,
|
|
qproc->reset_clk_count);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "failed to enable reset clocks\n");
|
|
goto disable_vdd;
|
|
}
|
|
|
|
ret = q6v5_reset_deassert(qproc);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "failed to deassert mss restart\n");
|
|
goto disable_reset_clks;
|
|
}
|
|
|
|
ret = q6v5_clk_enable(qproc->dev, qproc->active_clks,
|
|
qproc->active_clk_count);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "failed to enable clocks\n");
|
|
goto assert_reset;
|
|
}
|
|
|
|
/* Assign MBA image access in DDR to q6 */
|
|
ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, true,
|
|
qproc->mba_phys, qproc->mba_size);
|
|
if (ret) {
|
|
dev_err(qproc->dev,
|
|
"assigning Q6 access to mba memory failed: %d\n", ret);
|
|
goto disable_active_clks;
|
|
}
|
|
|
|
writel(qproc->mba_phys, qproc->rmb_base + RMB_MBA_IMAGE_REG);
|
|
|
|
ret = q6v5proc_reset(qproc);
|
|
if (ret)
|
|
goto reclaim_mba;
|
|
|
|
ret = q6v5_rmb_mba_wait(qproc, 0, 5000);
|
|
if (ret == -ETIMEDOUT) {
|
|
dev_err(qproc->dev, "MBA boot timed out\n");
|
|
goto halt_axi_ports;
|
|
} else if (ret != RMB_MBA_XPU_UNLOCKED &&
|
|
ret != RMB_MBA_XPU_UNLOCKED_SCRIBBLED) {
|
|
dev_err(qproc->dev, "MBA returned unexpected status %d\n", ret);
|
|
ret = -EINVAL;
|
|
goto halt_axi_ports;
|
|
}
|
|
|
|
qproc->dump_mba_loaded = true;
|
|
return 0;
|
|
|
|
halt_axi_ports:
|
|
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
|
|
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
|
|
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
|
|
|
|
reclaim_mba:
|
|
xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
|
|
qproc->mba_phys,
|
|
qproc->mba_size);
|
|
if (xfermemop_ret) {
|
|
dev_err(qproc->dev,
|
|
"Failed to reclaim mba buffer, system may become unstable\n");
|
|
}
|
|
|
|
disable_active_clks:
|
|
q6v5_clk_disable(qproc->dev, qproc->active_clks,
|
|
qproc->active_clk_count);
|
|
assert_reset:
|
|
q6v5_reset_assert(qproc);
|
|
disable_reset_clks:
|
|
q6v5_clk_disable(qproc->dev, qproc->reset_clks,
|
|
qproc->reset_clk_count);
|
|
disable_vdd:
|
|
q6v5_regulator_disable(qproc, qproc->active_regs,
|
|
qproc->active_reg_count);
|
|
disable_proxy_clk:
|
|
q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
|
|
qproc->proxy_clk_count);
|
|
disable_proxy_reg:
|
|
q6v5_regulator_disable(qproc, qproc->proxy_regs,
|
|
qproc->proxy_reg_count);
|
|
disable_proxy_pds:
|
|
q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
|
|
disable_active_pds:
|
|
q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
|
|
disable_irqs:
|
|
qcom_q6v5_unprepare(&qproc->q6v5);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void q6v5_mba_reclaim(struct q6v5 *qproc)
|
|
{
|
|
int ret;
|
|
u32 val;
|
|
|
|
qproc->dump_mba_loaded = false;
|
|
|
|
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_q6);
|
|
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_modem);
|
|
q6v5proc_halt_axi_port(qproc, qproc->halt_map, qproc->halt_nc);
|
|
if (qproc->version == MSS_MSM8996) {
|
|
/*
|
|
* To avoid high MX current during LPASS/MSS restart.
|
|
*/
|
|
val = readl(qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
val |= Q6SS_CLAMP_IO | QDSP6v56_CLAMP_WL |
|
|
QDSP6v56_CLAMP_QMC_MEM;
|
|
writel(val, qproc->reg_base + QDSP6SS_PWR_CTL_REG);
|
|
}
|
|
|
|
q6v5_reset_assert(qproc);
|
|
|
|
q6v5_clk_disable(qproc->dev, qproc->reset_clks,
|
|
qproc->reset_clk_count);
|
|
q6v5_clk_disable(qproc->dev, qproc->active_clks,
|
|
qproc->active_clk_count);
|
|
q6v5_regulator_disable(qproc, qproc->active_regs,
|
|
qproc->active_reg_count);
|
|
q6v5_pds_disable(qproc, qproc->active_pds, qproc->active_pd_count);
|
|
|
|
/* In case of failure or coredump scenario where reclaiming MBA memory
|
|
* could not happen reclaim it here.
|
|
*/
|
|
ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
|
|
qproc->mba_phys,
|
|
qproc->mba_size);
|
|
WARN_ON(ret);
|
|
|
|
ret = qcom_q6v5_unprepare(&qproc->q6v5);
|
|
if (ret) {
|
|
q6v5_pds_disable(qproc, qproc->proxy_pds,
|
|
qproc->proxy_pd_count);
|
|
q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
|
|
qproc->proxy_clk_count);
|
|
q6v5_regulator_disable(qproc, qproc->proxy_regs,
|
|
qproc->proxy_reg_count);
|
|
}
|
|
}
|
|
|
|
static int q6v5_reload_mba(struct rproc *rproc)
|
|
{
|
|
struct q6v5 *qproc = rproc->priv;
|
|
const struct firmware *fw;
|
|
int ret;
|
|
|
|
ret = request_firmware(&fw, rproc->firmware, qproc->dev);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
q6v5_load(rproc, fw);
|
|
ret = q6v5_mba_load(qproc);
|
|
release_firmware(fw);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int q6v5_mpss_load(struct q6v5 *qproc)
|
|
{
|
|
const struct elf32_phdr *phdrs;
|
|
const struct elf32_phdr *phdr;
|
|
const struct firmware *seg_fw;
|
|
const struct firmware *fw;
|
|
struct elf32_hdr *ehdr;
|
|
phys_addr_t mpss_reloc;
|
|
phys_addr_t boot_addr;
|
|
phys_addr_t min_addr = PHYS_ADDR_MAX;
|
|
phys_addr_t max_addr = 0;
|
|
bool relocate = false;
|
|
char *fw_name;
|
|
size_t fw_name_len;
|
|
ssize_t offset;
|
|
size_t size = 0;
|
|
void *ptr;
|
|
int ret;
|
|
int i;
|
|
|
|
fw_name_len = strlen(qproc->hexagon_mdt_image);
|
|
if (fw_name_len <= 4)
|
|
return -EINVAL;
|
|
|
|
fw_name = kstrdup(qproc->hexagon_mdt_image, GFP_KERNEL);
|
|
if (!fw_name)
|
|
return -ENOMEM;
|
|
|
|
ret = request_firmware(&fw, fw_name, qproc->dev);
|
|
if (ret < 0) {
|
|
dev_err(qproc->dev, "unable to load %s\n", fw_name);
|
|
goto out;
|
|
}
|
|
|
|
/* Initialize the RMB validator */
|
|
writel(0, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
|
|
|
|
ret = q6v5_mpss_init_image(qproc, fw);
|
|
if (ret)
|
|
goto release_firmware;
|
|
|
|
ehdr = (struct elf32_hdr *)fw->data;
|
|
phdrs = (struct elf32_phdr *)(ehdr + 1);
|
|
|
|
for (i = 0; i < ehdr->e_phnum; i++) {
|
|
phdr = &phdrs[i];
|
|
|
|
if (!q6v5_phdr_valid(phdr))
|
|
continue;
|
|
|
|
if (phdr->p_flags & QCOM_MDT_RELOCATABLE)
|
|
relocate = true;
|
|
|
|
if (phdr->p_paddr < min_addr)
|
|
min_addr = phdr->p_paddr;
|
|
|
|
if (phdr->p_paddr + phdr->p_memsz > max_addr)
|
|
max_addr = ALIGN(phdr->p_paddr + phdr->p_memsz, SZ_4K);
|
|
}
|
|
|
|
/**
|
|
* In case of a modem subsystem restart on secure devices, the modem
|
|
* memory can be reclaimed only after MBA is loaded. For modem cold
|
|
* boot this will be a nop
|
|
*/
|
|
q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, false,
|
|
qproc->mpss_phys, qproc->mpss_size);
|
|
|
|
mpss_reloc = relocate ? min_addr : qproc->mpss_phys;
|
|
qproc->mpss_reloc = mpss_reloc;
|
|
/* Load firmware segments */
|
|
for (i = 0; i < ehdr->e_phnum; i++) {
|
|
phdr = &phdrs[i];
|
|
|
|
if (!q6v5_phdr_valid(phdr))
|
|
continue;
|
|
|
|
offset = phdr->p_paddr - mpss_reloc;
|
|
if (offset < 0 || offset + phdr->p_memsz > qproc->mpss_size) {
|
|
dev_err(qproc->dev, "segment outside memory range\n");
|
|
ret = -EINVAL;
|
|
goto release_firmware;
|
|
}
|
|
|
|
ptr = ioremap_wc(qproc->mpss_phys + offset, phdr->p_memsz);
|
|
if (!ptr) {
|
|
dev_err(qproc->dev,
|
|
"unable to map memory region: %pa+%zx-%x\n",
|
|
&qproc->mpss_phys, offset, phdr->p_memsz);
|
|
goto release_firmware;
|
|
}
|
|
|
|
if (phdr->p_filesz && phdr->p_offset < fw->size) {
|
|
/* Firmware is large enough to be non-split */
|
|
if (phdr->p_offset + phdr->p_filesz > fw->size) {
|
|
dev_err(qproc->dev,
|
|
"failed to load segment %d from truncated file %s\n",
|
|
i, fw_name);
|
|
ret = -EINVAL;
|
|
iounmap(ptr);
|
|
goto release_firmware;
|
|
}
|
|
|
|
memcpy(ptr, fw->data + phdr->p_offset, phdr->p_filesz);
|
|
} else if (phdr->p_filesz) {
|
|
/* Replace "xxx.xxx" with "xxx.bxx" */
|
|
sprintf(fw_name + fw_name_len - 3, "b%02d", i);
|
|
ret = request_firmware_into_buf(&seg_fw, fw_name, qproc->dev,
|
|
ptr, phdr->p_filesz);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "failed to load %s\n", fw_name);
|
|
iounmap(ptr);
|
|
goto release_firmware;
|
|
}
|
|
|
|
release_firmware(seg_fw);
|
|
}
|
|
|
|
if (phdr->p_memsz > phdr->p_filesz) {
|
|
memset(ptr + phdr->p_filesz, 0,
|
|
phdr->p_memsz - phdr->p_filesz);
|
|
}
|
|
iounmap(ptr);
|
|
size += phdr->p_memsz;
|
|
}
|
|
|
|
/* Transfer ownership of modem ddr region to q6 */
|
|
ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm, true,
|
|
qproc->mpss_phys, qproc->mpss_size);
|
|
if (ret) {
|
|
dev_err(qproc->dev,
|
|
"assigning Q6 access to mpss memory failed: %d\n", ret);
|
|
ret = -EAGAIN;
|
|
goto release_firmware;
|
|
}
|
|
|
|
boot_addr = relocate ? qproc->mpss_phys : min_addr;
|
|
writel(boot_addr, qproc->rmb_base + RMB_PMI_CODE_START_REG);
|
|
writel(RMB_CMD_LOAD_READY, qproc->rmb_base + RMB_MBA_COMMAND_REG);
|
|
writel(size, qproc->rmb_base + RMB_PMI_CODE_LENGTH_REG);
|
|
|
|
ret = q6v5_rmb_mba_wait(qproc, RMB_MBA_AUTH_COMPLETE, 10000);
|
|
if (ret == -ETIMEDOUT)
|
|
dev_err(qproc->dev, "MPSS authentication timed out\n");
|
|
else if (ret < 0)
|
|
dev_err(qproc->dev, "MPSS authentication failed: %d\n", ret);
|
|
|
|
release_firmware:
|
|
release_firmware(fw);
|
|
out:
|
|
kfree(fw_name);
|
|
|
|
return ret < 0 ? ret : 0;
|
|
}
|
|
|
|
static void qcom_q6v5_dump_segment(struct rproc *rproc,
|
|
struct rproc_dump_segment *segment,
|
|
void *dest)
|
|
{
|
|
int ret = 0;
|
|
struct q6v5 *qproc = rproc->priv;
|
|
unsigned long mask = BIT((unsigned long)segment->priv);
|
|
int offset = segment->da - qproc->mpss_reloc;
|
|
void *ptr = NULL;
|
|
|
|
/* Unlock mba before copying segments */
|
|
if (!qproc->dump_mba_loaded) {
|
|
ret = q6v5_reload_mba(rproc);
|
|
if (!ret) {
|
|
/* Reset ownership back to Linux to copy segments */
|
|
ret = q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
|
|
false,
|
|
qproc->mpss_phys,
|
|
qproc->mpss_size);
|
|
}
|
|
}
|
|
|
|
if (!ret)
|
|
ptr = ioremap_wc(qproc->mpss_phys + offset, segment->size);
|
|
|
|
if (ptr) {
|
|
memcpy(dest, ptr, segment->size);
|
|
iounmap(ptr);
|
|
} else {
|
|
memset(dest, 0xff, segment->size);
|
|
}
|
|
|
|
qproc->dump_segment_mask |= mask;
|
|
|
|
/* Reclaim mba after copying segments */
|
|
if (qproc->dump_segment_mask == qproc->dump_complete_mask) {
|
|
if (qproc->dump_mba_loaded) {
|
|
/* Try to reset ownership back to Q6 */
|
|
q6v5_xfer_mem_ownership(qproc, &qproc->mpss_perm,
|
|
true,
|
|
qproc->mpss_phys,
|
|
qproc->mpss_size);
|
|
q6v5_mba_reclaim(qproc);
|
|
}
|
|
}
|
|
}
|
|
|
|
static int q6v5_start(struct rproc *rproc)
|
|
{
|
|
struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
|
|
int xfermemop_ret;
|
|
int ret;
|
|
|
|
ret = q6v5_mba_load(qproc);
|
|
if (ret)
|
|
return ret;
|
|
|
|
dev_info(qproc->dev, "MBA booted, loading mpss\n");
|
|
|
|
ret = q6v5_mpss_load(qproc);
|
|
if (ret)
|
|
goto reclaim_mpss;
|
|
|
|
ret = qcom_q6v5_wait_for_start(&qproc->q6v5, msecs_to_jiffies(5000));
|
|
if (ret == -ETIMEDOUT) {
|
|
dev_err(qproc->dev, "start timed out\n");
|
|
goto reclaim_mpss;
|
|
}
|
|
|
|
xfermemop_ret = q6v5_xfer_mem_ownership(qproc, &qproc->mba_perm, false,
|
|
qproc->mba_phys,
|
|
qproc->mba_size);
|
|
if (xfermemop_ret)
|
|
dev_err(qproc->dev,
|
|
"Failed to reclaim mba buffer system may become unstable\n");
|
|
|
|
/* Reset Dump Segment Mask */
|
|
qproc->dump_segment_mask = 0;
|
|
qproc->running = true;
|
|
|
|
return 0;
|
|
|
|
reclaim_mpss:
|
|
q6v5_mba_reclaim(qproc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int q6v5_stop(struct rproc *rproc)
|
|
{
|
|
struct q6v5 *qproc = (struct q6v5 *)rproc->priv;
|
|
int ret;
|
|
|
|
qproc->running = false;
|
|
|
|
ret = qcom_q6v5_request_stop(&qproc->q6v5);
|
|
if (ret == -ETIMEDOUT)
|
|
dev_err(qproc->dev, "timed out on wait\n");
|
|
|
|
q6v5_mba_reclaim(qproc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void *q6v5_da_to_va(struct rproc *rproc, u64 da, int len)
|
|
{
|
|
struct q6v5 *qproc = rproc->priv;
|
|
int offset;
|
|
|
|
offset = da - qproc->mpss_reloc;
|
|
if (offset < 0 || offset + len > qproc->mpss_size)
|
|
return NULL;
|
|
|
|
return qproc->mpss_region + offset;
|
|
}
|
|
|
|
static int qcom_q6v5_register_dump_segments(struct rproc *rproc,
|
|
const struct firmware *mba_fw)
|
|
{
|
|
const struct firmware *fw;
|
|
const struct elf32_phdr *phdrs;
|
|
const struct elf32_phdr *phdr;
|
|
const struct elf32_hdr *ehdr;
|
|
struct q6v5 *qproc = rproc->priv;
|
|
unsigned long i;
|
|
int ret;
|
|
|
|
ret = request_firmware(&fw, qproc->hexagon_mdt_image, qproc->dev);
|
|
if (ret < 0) {
|
|
dev_err(qproc->dev, "unable to load %s\n",
|
|
qproc->hexagon_mdt_image);
|
|
return ret;
|
|
}
|
|
|
|
ehdr = (struct elf32_hdr *)fw->data;
|
|
phdrs = (struct elf32_phdr *)(ehdr + 1);
|
|
qproc->dump_complete_mask = 0;
|
|
|
|
for (i = 0; i < ehdr->e_phnum; i++) {
|
|
phdr = &phdrs[i];
|
|
|
|
if (!q6v5_phdr_valid(phdr))
|
|
continue;
|
|
|
|
ret = rproc_coredump_add_custom_segment(rproc, phdr->p_paddr,
|
|
phdr->p_memsz,
|
|
qcom_q6v5_dump_segment,
|
|
(void *)i);
|
|
if (ret)
|
|
break;
|
|
|
|
qproc->dump_complete_mask |= BIT(i);
|
|
}
|
|
|
|
release_firmware(fw);
|
|
return ret;
|
|
}
|
|
|
|
static const struct rproc_ops q6v5_ops = {
|
|
.start = q6v5_start,
|
|
.stop = q6v5_stop,
|
|
.da_to_va = q6v5_da_to_va,
|
|
.parse_fw = qcom_q6v5_register_dump_segments,
|
|
.load = q6v5_load,
|
|
};
|
|
|
|
static void qcom_msa_handover(struct qcom_q6v5 *q6v5)
|
|
{
|
|
struct q6v5 *qproc = container_of(q6v5, struct q6v5, q6v5);
|
|
|
|
q6v5_clk_disable(qproc->dev, qproc->proxy_clks,
|
|
qproc->proxy_clk_count);
|
|
q6v5_regulator_disable(qproc, qproc->proxy_regs,
|
|
qproc->proxy_reg_count);
|
|
q6v5_pds_disable(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
|
|
}
|
|
|
|
static int q6v5_init_mem(struct q6v5 *qproc, struct platform_device *pdev)
|
|
{
|
|
struct of_phandle_args args;
|
|
struct resource *res;
|
|
int ret;
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "qdsp6");
|
|
qproc->reg_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(qproc->reg_base))
|
|
return PTR_ERR(qproc->reg_base);
|
|
|
|
res = platform_get_resource_byname(pdev, IORESOURCE_MEM, "rmb");
|
|
qproc->rmb_base = devm_ioremap_resource(&pdev->dev, res);
|
|
if (IS_ERR(qproc->rmb_base))
|
|
return PTR_ERR(qproc->rmb_base);
|
|
|
|
ret = of_parse_phandle_with_fixed_args(pdev->dev.of_node,
|
|
"qcom,halt-regs", 3, 0, &args);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "failed to parse qcom,halt-regs\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
qproc->halt_map = syscon_node_to_regmap(args.np);
|
|
of_node_put(args.np);
|
|
if (IS_ERR(qproc->halt_map))
|
|
return PTR_ERR(qproc->halt_map);
|
|
|
|
qproc->halt_q6 = args.args[0];
|
|
qproc->halt_modem = args.args[1];
|
|
qproc->halt_nc = args.args[2];
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int q6v5_init_clocks(struct device *dev, struct clk **clks,
|
|
char **clk_names)
|
|
{
|
|
int i;
|
|
|
|
if (!clk_names)
|
|
return 0;
|
|
|
|
for (i = 0; clk_names[i]; i++) {
|
|
clks[i] = devm_clk_get(dev, clk_names[i]);
|
|
if (IS_ERR(clks[i])) {
|
|
int rc = PTR_ERR(clks[i]);
|
|
|
|
if (rc != -EPROBE_DEFER)
|
|
dev_err(dev, "Failed to get %s clock\n",
|
|
clk_names[i]);
|
|
return rc;
|
|
}
|
|
}
|
|
|
|
return i;
|
|
}
|
|
|
|
static int q6v5_pds_attach(struct device *dev, struct device **devs,
|
|
char **pd_names)
|
|
{
|
|
size_t num_pds = 0;
|
|
int ret;
|
|
int i;
|
|
|
|
if (!pd_names)
|
|
return 0;
|
|
|
|
while (pd_names[num_pds])
|
|
num_pds++;
|
|
|
|
for (i = 0; i < num_pds; i++) {
|
|
devs[i] = dev_pm_domain_attach_by_name(dev, pd_names[i]);
|
|
if (IS_ERR_OR_NULL(devs[i])) {
|
|
ret = PTR_ERR(devs[i]) ? : -ENODATA;
|
|
goto unroll_attach;
|
|
}
|
|
}
|
|
|
|
return num_pds;
|
|
|
|
unroll_attach:
|
|
for (i--; i >= 0; i--)
|
|
dev_pm_domain_detach(devs[i], false);
|
|
|
|
return ret;
|
|
};
|
|
|
|
static void q6v5_pds_detach(struct q6v5 *qproc, struct device **pds,
|
|
size_t pd_count)
|
|
{
|
|
int i;
|
|
|
|
for (i = 0; i < pd_count; i++)
|
|
dev_pm_domain_detach(pds[i], false);
|
|
}
|
|
|
|
static int q6v5_init_reset(struct q6v5 *qproc)
|
|
{
|
|
qproc->mss_restart = devm_reset_control_get_exclusive(qproc->dev,
|
|
"mss_restart");
|
|
if (IS_ERR(qproc->mss_restart)) {
|
|
dev_err(qproc->dev, "failed to acquire mss restart\n");
|
|
return PTR_ERR(qproc->mss_restart);
|
|
}
|
|
|
|
if (qproc->has_alt_reset) {
|
|
qproc->pdc_reset = devm_reset_control_get_exclusive(qproc->dev,
|
|
"pdc_reset");
|
|
if (IS_ERR(qproc->pdc_reset)) {
|
|
dev_err(qproc->dev, "failed to acquire pdc reset\n");
|
|
return PTR_ERR(qproc->pdc_reset);
|
|
}
|
|
}
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int q6v5_alloc_memory_region(struct q6v5 *qproc)
|
|
{
|
|
struct device_node *child;
|
|
struct device_node *node;
|
|
struct resource r;
|
|
int ret;
|
|
|
|
child = of_get_child_by_name(qproc->dev->of_node, "mba");
|
|
node = of_parse_phandle(child, "memory-region", 0);
|
|
ret = of_address_to_resource(node, 0, &r);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "unable to resolve mba region\n");
|
|
return ret;
|
|
}
|
|
of_node_put(node);
|
|
|
|
qproc->mba_phys = r.start;
|
|
qproc->mba_size = resource_size(&r);
|
|
qproc->mba_region = devm_ioremap_wc(qproc->dev, qproc->mba_phys, qproc->mba_size);
|
|
if (!qproc->mba_region) {
|
|
dev_err(qproc->dev, "unable to map memory region: %pa+%zx\n",
|
|
&r.start, qproc->mba_size);
|
|
return -EBUSY;
|
|
}
|
|
|
|
child = of_get_child_by_name(qproc->dev->of_node, "mpss");
|
|
node = of_parse_phandle(child, "memory-region", 0);
|
|
ret = of_address_to_resource(node, 0, &r);
|
|
if (ret) {
|
|
dev_err(qproc->dev, "unable to resolve mpss region\n");
|
|
return ret;
|
|
}
|
|
of_node_put(node);
|
|
|
|
qproc->mpss_phys = qproc->mpss_reloc = r.start;
|
|
qproc->mpss_size = resource_size(&r);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int q6v5_probe(struct platform_device *pdev)
|
|
{
|
|
const struct rproc_hexagon_res *desc;
|
|
struct q6v5 *qproc;
|
|
struct rproc *rproc;
|
|
const char *mba_image;
|
|
int ret;
|
|
|
|
desc = of_device_get_match_data(&pdev->dev);
|
|
if (!desc)
|
|
return -EINVAL;
|
|
|
|
if (desc->need_mem_protection && !qcom_scm_is_available())
|
|
return -EPROBE_DEFER;
|
|
|
|
mba_image = desc->hexagon_mba_image;
|
|
ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
|
|
0, &mba_image);
|
|
if (ret < 0 && ret != -EINVAL)
|
|
return ret;
|
|
|
|
rproc = rproc_alloc(&pdev->dev, pdev->name, &q6v5_ops,
|
|
mba_image, sizeof(*qproc));
|
|
if (!rproc) {
|
|
dev_err(&pdev->dev, "failed to allocate rproc\n");
|
|
return -ENOMEM;
|
|
}
|
|
|
|
rproc->auto_boot = false;
|
|
|
|
qproc = (struct q6v5 *)rproc->priv;
|
|
qproc->dev = &pdev->dev;
|
|
qproc->rproc = rproc;
|
|
qproc->hexagon_mdt_image = "modem.mdt";
|
|
ret = of_property_read_string_index(pdev->dev.of_node, "firmware-name",
|
|
1, &qproc->hexagon_mdt_image);
|
|
if (ret < 0 && ret != -EINVAL)
|
|
goto free_rproc;
|
|
|
|
platform_set_drvdata(pdev, qproc);
|
|
|
|
ret = q6v5_init_mem(qproc, pdev);
|
|
if (ret)
|
|
goto free_rproc;
|
|
|
|
ret = q6v5_alloc_memory_region(qproc);
|
|
if (ret)
|
|
goto free_rproc;
|
|
|
|
ret = q6v5_init_clocks(&pdev->dev, qproc->proxy_clks,
|
|
desc->proxy_clk_names);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to get proxy clocks.\n");
|
|
goto free_rproc;
|
|
}
|
|
qproc->proxy_clk_count = ret;
|
|
|
|
ret = q6v5_init_clocks(&pdev->dev, qproc->reset_clks,
|
|
desc->reset_clk_names);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to get reset clocks.\n");
|
|
goto free_rproc;
|
|
}
|
|
qproc->reset_clk_count = ret;
|
|
|
|
ret = q6v5_init_clocks(&pdev->dev, qproc->active_clks,
|
|
desc->active_clk_names);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to get active clocks.\n");
|
|
goto free_rproc;
|
|
}
|
|
qproc->active_clk_count = ret;
|
|
|
|
ret = q6v5_regulator_init(&pdev->dev, qproc->proxy_regs,
|
|
desc->proxy_supply);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to get proxy regulators.\n");
|
|
goto free_rproc;
|
|
}
|
|
qproc->proxy_reg_count = ret;
|
|
|
|
ret = q6v5_regulator_init(&pdev->dev, qproc->active_regs,
|
|
desc->active_supply);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to get active regulators.\n");
|
|
goto free_rproc;
|
|
}
|
|
qproc->active_reg_count = ret;
|
|
|
|
ret = q6v5_pds_attach(&pdev->dev, qproc->active_pds,
|
|
desc->active_pd_names);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to attach active power domains\n");
|
|
goto free_rproc;
|
|
}
|
|
qproc->active_pd_count = ret;
|
|
|
|
ret = q6v5_pds_attach(&pdev->dev, qproc->proxy_pds,
|
|
desc->proxy_pd_names);
|
|
if (ret < 0) {
|
|
dev_err(&pdev->dev, "Failed to init power domains\n");
|
|
goto detach_active_pds;
|
|
}
|
|
qproc->proxy_pd_count = ret;
|
|
|
|
qproc->has_alt_reset = desc->has_alt_reset;
|
|
ret = q6v5_init_reset(qproc);
|
|
if (ret)
|
|
goto detach_proxy_pds;
|
|
|
|
qproc->version = desc->version;
|
|
qproc->need_mem_protection = desc->need_mem_protection;
|
|
|
|
ret = qcom_q6v5_init(&qproc->q6v5, pdev, rproc, MPSS_CRASH_REASON_SMEM,
|
|
qcom_msa_handover);
|
|
if (ret)
|
|
goto detach_proxy_pds;
|
|
|
|
qproc->mpss_perm = BIT(QCOM_SCM_VMID_HLOS);
|
|
qproc->mba_perm = BIT(QCOM_SCM_VMID_HLOS);
|
|
qcom_add_glink_subdev(rproc, &qproc->glink_subdev);
|
|
qcom_add_smd_subdev(rproc, &qproc->smd_subdev);
|
|
qcom_add_ssr_subdev(rproc, &qproc->ssr_subdev, "mpss");
|
|
qproc->sysmon = qcom_add_sysmon_subdev(rproc, "modem", 0x12);
|
|
if (IS_ERR(qproc->sysmon)) {
|
|
ret = PTR_ERR(qproc->sysmon);
|
|
goto detach_proxy_pds;
|
|
}
|
|
|
|
ret = rproc_add(rproc);
|
|
if (ret)
|
|
goto detach_proxy_pds;
|
|
|
|
return 0;
|
|
|
|
detach_proxy_pds:
|
|
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
|
|
detach_active_pds:
|
|
q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
|
|
free_rproc:
|
|
rproc_free(rproc);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int q6v5_remove(struct platform_device *pdev)
|
|
{
|
|
struct q6v5 *qproc = platform_get_drvdata(pdev);
|
|
|
|
rproc_del(qproc->rproc);
|
|
|
|
qcom_remove_sysmon_subdev(qproc->sysmon);
|
|
qcom_remove_glink_subdev(qproc->rproc, &qproc->glink_subdev);
|
|
qcom_remove_smd_subdev(qproc->rproc, &qproc->smd_subdev);
|
|
qcom_remove_ssr_subdev(qproc->rproc, &qproc->ssr_subdev);
|
|
|
|
q6v5_pds_detach(qproc, qproc->active_pds, qproc->active_pd_count);
|
|
q6v5_pds_detach(qproc, qproc->proxy_pds, qproc->proxy_pd_count);
|
|
|
|
rproc_free(qproc->rproc);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static const struct rproc_hexagon_res sdm845_mss = {
|
|
.hexagon_mba_image = "mba.mbn",
|
|
.proxy_clk_names = (char*[]){
|
|
"xo",
|
|
"prng",
|
|
NULL
|
|
},
|
|
.reset_clk_names = (char*[]){
|
|
"iface",
|
|
"snoc_axi",
|
|
NULL
|
|
},
|
|
.active_clk_names = (char*[]){
|
|
"bus",
|
|
"mem",
|
|
"gpll0_mss",
|
|
"mnoc_axi",
|
|
NULL
|
|
},
|
|
.active_pd_names = (char*[]){
|
|
"load_state",
|
|
NULL
|
|
},
|
|
.proxy_pd_names = (char*[]){
|
|
"cx",
|
|
"mx",
|
|
"mss",
|
|
NULL
|
|
},
|
|
.need_mem_protection = true,
|
|
.has_alt_reset = true,
|
|
.version = MSS_SDM845,
|
|
};
|
|
|
|
static const struct rproc_hexagon_res msm8996_mss = {
|
|
.hexagon_mba_image = "mba.mbn",
|
|
.proxy_supply = (struct qcom_mss_reg_res[]) {
|
|
{
|
|
.supply = "pll",
|
|
.uA = 100000,
|
|
},
|
|
{}
|
|
},
|
|
.proxy_clk_names = (char*[]){
|
|
"xo",
|
|
"pnoc",
|
|
"qdss",
|
|
NULL
|
|
},
|
|
.active_clk_names = (char*[]){
|
|
"iface",
|
|
"bus",
|
|
"mem",
|
|
"gpll0_mss",
|
|
"snoc_axi",
|
|
"mnoc_axi",
|
|
NULL
|
|
},
|
|
.need_mem_protection = true,
|
|
.has_alt_reset = false,
|
|
.version = MSS_MSM8996,
|
|
};
|
|
|
|
static const struct rproc_hexagon_res msm8916_mss = {
|
|
.hexagon_mba_image = "mba.mbn",
|
|
.proxy_supply = (struct qcom_mss_reg_res[]) {
|
|
{
|
|
.supply = "mx",
|
|
.uV = 1050000,
|
|
},
|
|
{
|
|
.supply = "cx",
|
|
.uA = 100000,
|
|
},
|
|
{
|
|
.supply = "pll",
|
|
.uA = 100000,
|
|
},
|
|
{}
|
|
},
|
|
.proxy_clk_names = (char*[]){
|
|
"xo",
|
|
NULL
|
|
},
|
|
.active_clk_names = (char*[]){
|
|
"iface",
|
|
"bus",
|
|
"mem",
|
|
NULL
|
|
},
|
|
.need_mem_protection = false,
|
|
.has_alt_reset = false,
|
|
.version = MSS_MSM8916,
|
|
};
|
|
|
|
static const struct rproc_hexagon_res msm8974_mss = {
|
|
.hexagon_mba_image = "mba.b00",
|
|
.proxy_supply = (struct qcom_mss_reg_res[]) {
|
|
{
|
|
.supply = "mx",
|
|
.uV = 1050000,
|
|
},
|
|
{
|
|
.supply = "cx",
|
|
.uA = 100000,
|
|
},
|
|
{
|
|
.supply = "pll",
|
|
.uA = 100000,
|
|
},
|
|
{}
|
|
},
|
|
.active_supply = (struct qcom_mss_reg_res[]) {
|
|
{
|
|
.supply = "mss",
|
|
.uV = 1050000,
|
|
.uA = 100000,
|
|
},
|
|
{}
|
|
},
|
|
.proxy_clk_names = (char*[]){
|
|
"xo",
|
|
NULL
|
|
},
|
|
.active_clk_names = (char*[]){
|
|
"iface",
|
|
"bus",
|
|
"mem",
|
|
NULL
|
|
},
|
|
.need_mem_protection = false,
|
|
.has_alt_reset = false,
|
|
.version = MSS_MSM8974,
|
|
};
|
|
|
|
static const struct of_device_id q6v5_of_match[] = {
|
|
{ .compatible = "qcom,q6v5-pil", .data = &msm8916_mss},
|
|
{ .compatible = "qcom,msm8916-mss-pil", .data = &msm8916_mss},
|
|
{ .compatible = "qcom,msm8974-mss-pil", .data = &msm8974_mss},
|
|
{ .compatible = "qcom,msm8996-mss-pil", .data = &msm8996_mss},
|
|
{ .compatible = "qcom,sdm845-mss-pil", .data = &sdm845_mss},
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, q6v5_of_match);
|
|
|
|
static struct platform_driver q6v5_driver = {
|
|
.probe = q6v5_probe,
|
|
.remove = q6v5_remove,
|
|
.driver = {
|
|
.name = "qcom-q6v5-mss",
|
|
.of_match_table = q6v5_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(q6v5_driver);
|
|
|
|
MODULE_DESCRIPTION("Qualcomm Self-authenticating modem remoteproc driver");
|
|
MODULE_LICENSE("GPL v2");
|