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![Maximilian Luz](/assets/img/avatar_default.png)
Add device HID AMDI0022 to the AMD UART controller driver match table and create a platform device for it. This controller can be found on Microsoft Surface Laptop 4 devices and seems similar enough that we can just copy the existing AMDI0020 entries. Cc: <stable@vger.kernel.org> # 5.10+ Tested-by: Sachi King <nakato@nakato.io> Acked-by: Andy Shevchenko <andy.shevchenko@gmail.com> # for 8250_dw part Signed-off-by: Maximilian Luz <luzmaximilian@gmail.com> Link: https://lore.kernel.org/r/20210512210413.1982933-1-luzmaximilian@gmail.com Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
740 lines
19 KiB
C
740 lines
19 KiB
C
// SPDX-License-Identifier: GPL-2.0+
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/*
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* Synopsys DesignWare 8250 driver.
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*
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* Copyright 2011 Picochip, Jamie Iles.
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* Copyright 2013 Intel Corporation
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*
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* The Synopsys DesignWare 8250 has an extra feature whereby it detects if the
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* LCR is written whilst busy. If it is, then a busy detect interrupt is
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* raised, the LCR needs to be rewritten and the uart status register read.
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/serial_8250.h>
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#include <linux/serial_reg.h>
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#include <linux/of.h>
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#include <linux/of_irq.h>
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#include <linux/of_platform.h>
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#include <linux/platform_device.h>
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#include <linux/workqueue.h>
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#include <linux/notifier.h>
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#include <linux/slab.h>
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#include <linux/acpi.h>
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#include <linux/clk.h>
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#include <linux/reset.h>
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#include <linux/pm_runtime.h>
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#include <asm/byteorder.h>
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#include "8250_dwlib.h"
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/* Offsets for the DesignWare specific registers */
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#define DW_UART_USR 0x1f /* UART Status Register */
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/* DesignWare specific register fields */
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#define DW_UART_MCR_SIRE BIT(6)
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struct dw8250_data {
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struct dw8250_port_data data;
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u8 usr_reg;
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int msr_mask_on;
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int msr_mask_off;
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struct clk *clk;
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struct clk *pclk;
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struct notifier_block clk_notifier;
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struct work_struct clk_work;
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struct reset_control *rst;
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unsigned int skip_autocfg:1;
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unsigned int uart_16550_compatible:1;
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};
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static inline struct dw8250_data *to_dw8250_data(struct dw8250_port_data *data)
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{
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return container_of(data, struct dw8250_data, data);
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}
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static inline struct dw8250_data *clk_to_dw8250_data(struct notifier_block *nb)
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{
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return container_of(nb, struct dw8250_data, clk_notifier);
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}
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static inline struct dw8250_data *work_to_dw8250_data(struct work_struct *work)
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{
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return container_of(work, struct dw8250_data, clk_work);
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}
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static inline int dw8250_modify_msr(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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/* Override any modem control signals if needed */
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if (offset == UART_MSR) {
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value |= d->msr_mask_on;
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value &= ~d->msr_mask_off;
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}
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return value;
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}
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static void dw8250_force_idle(struct uart_port *p)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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serial8250_clear_and_reinit_fifos(up);
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(void)p->serial_in(p, UART_RX);
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}
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static void dw8250_check_lcr(struct uart_port *p, int value)
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{
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void __iomem *offset = p->membase + (UART_LCR << p->regshift);
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int tries = 1000;
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/* Make sure LCR write wasn't ignored */
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while (tries--) {
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unsigned int lcr = p->serial_in(p, UART_LCR);
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if ((value & ~UART_LCR_SPAR) == (lcr & ~UART_LCR_SPAR))
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return;
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dw8250_force_idle(p);
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#ifdef CONFIG_64BIT
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if (p->type == PORT_OCTEON)
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__raw_writeq(value & 0xff, offset);
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else
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#endif
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if (p->iotype == UPIO_MEM32)
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writel(value, offset);
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else if (p->iotype == UPIO_MEM32BE)
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iowrite32be(value, offset);
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else
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writeb(value, offset);
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}
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/*
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* FIXME: this deadlocks if port->lock is already held
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* dev_err(p->dev, "Couldn't set LCR to %d\n", value);
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*/
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}
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/* Returns once the transmitter is empty or we run out of retries */
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static void dw8250_tx_wait_empty(struct uart_port *p)
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{
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unsigned int tries = 20000;
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unsigned int delay_threshold = tries - 1000;
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unsigned int lsr;
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while (tries--) {
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lsr = readb (p->membase + (UART_LSR << p->regshift));
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if (lsr & UART_LSR_TEMT)
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break;
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/* The device is first given a chance to empty without delay,
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* to avoid slowdowns at high bitrates. If after 1000 tries
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* the buffer has still not emptied, allow more time for low-
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* speed links. */
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if (tries < delay_threshold)
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udelay (1);
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}
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}
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static void dw8250_serial_out38x(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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/* Allow the TX to drain before we reconfigure */
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if (offset == UART_LCR)
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dw8250_tx_wait_empty(p);
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writeb(value, p->membase + (offset << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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static void dw8250_serial_out(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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writeb(value, p->membase + (offset << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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static unsigned int dw8250_serial_in(struct uart_port *p, int offset)
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{
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unsigned int value = readb(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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#ifdef CONFIG_64BIT
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static unsigned int dw8250_serial_inq(struct uart_port *p, int offset)
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{
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unsigned int value;
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value = (u8)__raw_readq(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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static void dw8250_serial_outq(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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value &= 0xff;
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__raw_writeq(value, p->membase + (offset << p->regshift));
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/* Read back to ensure register write ordering. */
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__raw_readq(p->membase + (UART_LCR << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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#endif /* CONFIG_64BIT */
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static void dw8250_serial_out32(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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writel(value, p->membase + (offset << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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static unsigned int dw8250_serial_in32(struct uart_port *p, int offset)
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{
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unsigned int value = readl(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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static void dw8250_serial_out32be(struct uart_port *p, int offset, int value)
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{
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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iowrite32be(value, p->membase + (offset << p->regshift));
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if (offset == UART_LCR && !d->uart_16550_compatible)
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dw8250_check_lcr(p, value);
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}
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static unsigned int dw8250_serial_in32be(struct uart_port *p, int offset)
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{
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unsigned int value = ioread32be(p->membase + (offset << p->regshift));
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return dw8250_modify_msr(p, offset, value);
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}
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static int dw8250_handle_irq(struct uart_port *p)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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unsigned int iir = p->serial_in(p, UART_IIR);
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unsigned int status;
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unsigned long flags;
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/*
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* There are ways to get Designware-based UARTs into a state where
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* they are asserting UART_IIR_RX_TIMEOUT but there is no actual
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* data available. If we see such a case then we'll do a bogus
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* read. If we don't do this then the "RX TIMEOUT" interrupt will
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* fire forever.
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*
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* This problem has only been observed so far when not in DMA mode
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* so we limit the workaround only to non-DMA mode.
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*/
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if (!up->dma && ((iir & 0x3f) == UART_IIR_RX_TIMEOUT)) {
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spin_lock_irqsave(&p->lock, flags);
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status = p->serial_in(p, UART_LSR);
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if (!(status & (UART_LSR_DR | UART_LSR_BI)))
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(void) p->serial_in(p, UART_RX);
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spin_unlock_irqrestore(&p->lock, flags);
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}
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if (serial8250_handle_irq(p, iir))
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return 1;
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if ((iir & UART_IIR_BUSY) == UART_IIR_BUSY) {
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/* Clear the USR */
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(void)p->serial_in(p, d->usr_reg);
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return 1;
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}
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return 0;
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}
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static void dw8250_clk_work_cb(struct work_struct *work)
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{
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struct dw8250_data *d = work_to_dw8250_data(work);
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struct uart_8250_port *up;
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unsigned long rate;
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rate = clk_get_rate(d->clk);
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if (rate <= 0)
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return;
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up = serial8250_get_port(d->data.line);
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serial8250_update_uartclk(&up->port, rate);
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}
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static int dw8250_clk_notifier_cb(struct notifier_block *nb,
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unsigned long event, void *data)
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{
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struct dw8250_data *d = clk_to_dw8250_data(nb);
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/*
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* We have no choice but to defer the uartclk update due to two
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* deadlocks. First one is caused by a recursive mutex lock which
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* happens when clk_set_rate() is called from dw8250_set_termios().
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* Second deadlock is more tricky and is caused by an inverted order of
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* the clk and tty-port mutexes lock. It happens if clock rate change
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* is requested asynchronously while set_termios() is executed between
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* tty-port mutex lock and clk_set_rate() function invocation and
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* vise-versa. Anyway if we didn't have the reference clock alteration
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* in the dw8250_set_termios() method we wouldn't have needed this
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* deferred event handling complication.
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*/
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if (event == POST_RATE_CHANGE) {
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queue_work(system_unbound_wq, &d->clk_work);
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return NOTIFY_OK;
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}
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return NOTIFY_DONE;
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}
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static void
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dw8250_do_pm(struct uart_port *port, unsigned int state, unsigned int old)
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{
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if (!state)
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pm_runtime_get_sync(port->dev);
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serial8250_do_pm(port, state, old);
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if (state)
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pm_runtime_put_sync_suspend(port->dev);
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}
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static void dw8250_set_termios(struct uart_port *p, struct ktermios *termios,
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struct ktermios *old)
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{
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unsigned long newrate = tty_termios_baud_rate(termios) * 16;
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struct dw8250_data *d = to_dw8250_data(p->private_data);
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long rate;
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int ret;
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clk_disable_unprepare(d->clk);
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rate = clk_round_rate(d->clk, newrate);
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if (rate > 0) {
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/*
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* Premilinary set the uartclk to the new clock rate so the
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* clock update event handler caused by the clk_set_rate()
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* calling wouldn't actually update the UART divisor since
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* we about to do this anyway.
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*/
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swap(p->uartclk, rate);
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ret = clk_set_rate(d->clk, newrate);
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if (ret)
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swap(p->uartclk, rate);
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}
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clk_prepare_enable(d->clk);
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p->status &= ~UPSTAT_AUTOCTS;
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if (termios->c_cflag & CRTSCTS)
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p->status |= UPSTAT_AUTOCTS;
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serial8250_do_set_termios(p, termios, old);
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}
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static void dw8250_set_ldisc(struct uart_port *p, struct ktermios *termios)
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{
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struct uart_8250_port *up = up_to_u8250p(p);
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unsigned int mcr = p->serial_in(p, UART_MCR);
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if (up->capabilities & UART_CAP_IRDA) {
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if (termios->c_line == N_IRDA)
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mcr |= DW_UART_MCR_SIRE;
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else
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mcr &= ~DW_UART_MCR_SIRE;
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p->serial_out(p, UART_MCR, mcr);
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}
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serial8250_do_set_ldisc(p, termios);
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}
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/*
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* dw8250_fallback_dma_filter will prevent the UART from getting just any free
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* channel on platforms that have DMA engines, but don't have any channels
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* assigned to the UART.
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*
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* REVISIT: This is a work around for limitation in the DMA Engine API. Once the
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* core problem is fixed, this function is no longer needed.
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*/
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static bool dw8250_fallback_dma_filter(struct dma_chan *chan, void *param)
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{
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return false;
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}
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static bool dw8250_idma_filter(struct dma_chan *chan, void *param)
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{
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return param == chan->device->dev;
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}
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static void dw8250_quirks(struct uart_port *p, struct dw8250_data *data)
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{
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if (p->dev->of_node) {
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struct device_node *np = p->dev->of_node;
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int id;
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/* get index of serial line, if found in DT aliases */
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id = of_alias_get_id(np, "serial");
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if (id >= 0)
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p->line = id;
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#ifdef CONFIG_64BIT
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if (of_device_is_compatible(np, "cavium,octeon-3860-uart")) {
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p->serial_in = dw8250_serial_inq;
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p->serial_out = dw8250_serial_outq;
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p->flags = UPF_SKIP_TEST | UPF_SHARE_IRQ | UPF_FIXED_TYPE;
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p->type = PORT_OCTEON;
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data->usr_reg = 0x27;
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data->skip_autocfg = true;
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}
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#endif
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if (of_device_is_big_endian(p->dev->of_node)) {
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p->iotype = UPIO_MEM32BE;
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p->serial_in = dw8250_serial_in32be;
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p->serial_out = dw8250_serial_out32be;
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}
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if (of_device_is_compatible(np, "marvell,armada-38x-uart"))
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p->serial_out = dw8250_serial_out38x;
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} else if (acpi_dev_present("APMC0D08", NULL, -1)) {
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p->iotype = UPIO_MEM32;
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p->regshift = 2;
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p->serial_in = dw8250_serial_in32;
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data->uart_16550_compatible = true;
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}
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/* Platforms with iDMA 64-bit */
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if (platform_get_resource_byname(to_platform_device(p->dev),
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IORESOURCE_MEM, "lpss_priv")) {
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data->data.dma.rx_param = p->dev->parent;
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data->data.dma.tx_param = p->dev->parent;
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data->data.dma.fn = dw8250_idma_filter;
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}
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}
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static int dw8250_probe(struct platform_device *pdev)
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{
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struct uart_8250_port uart = {}, *up = &uart;
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struct resource *regs = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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struct uart_port *p = &up->port;
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struct device *dev = &pdev->dev;
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struct dw8250_data *data;
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int irq;
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int err;
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u32 val;
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if (!regs) {
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dev_err(dev, "no registers defined\n");
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return -EINVAL;
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}
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irq = platform_get_irq(pdev, 0);
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if (irq < 0)
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return irq;
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spin_lock_init(&p->lock);
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p->mapbase = regs->start;
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p->irq = irq;
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p->handle_irq = dw8250_handle_irq;
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p->pm = dw8250_do_pm;
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p->type = PORT_8250;
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p->flags = UPF_SHARE_IRQ | UPF_FIXED_PORT;
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p->dev = dev;
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p->iotype = UPIO_MEM;
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p->serial_in = dw8250_serial_in;
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p->serial_out = dw8250_serial_out;
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p->set_ldisc = dw8250_set_ldisc;
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p->set_termios = dw8250_set_termios;
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p->membase = devm_ioremap(dev, regs->start, resource_size(regs));
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if (!p->membase)
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return -ENOMEM;
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data = devm_kzalloc(dev, sizeof(*data), GFP_KERNEL);
|
|
if (!data)
|
|
return -ENOMEM;
|
|
|
|
data->data.dma.fn = dw8250_fallback_dma_filter;
|
|
data->usr_reg = DW_UART_USR;
|
|
p->private_data = &data->data;
|
|
|
|
data->uart_16550_compatible = device_property_read_bool(dev,
|
|
"snps,uart-16550-compatible");
|
|
|
|
err = device_property_read_u32(dev, "reg-shift", &val);
|
|
if (!err)
|
|
p->regshift = val;
|
|
|
|
err = device_property_read_u32(dev, "reg-io-width", &val);
|
|
if (!err && val == 4) {
|
|
p->iotype = UPIO_MEM32;
|
|
p->serial_in = dw8250_serial_in32;
|
|
p->serial_out = dw8250_serial_out32;
|
|
}
|
|
|
|
if (device_property_read_bool(dev, "dcd-override")) {
|
|
/* Always report DCD as active */
|
|
data->msr_mask_on |= UART_MSR_DCD;
|
|
data->msr_mask_off |= UART_MSR_DDCD;
|
|
}
|
|
|
|
if (device_property_read_bool(dev, "dsr-override")) {
|
|
/* Always report DSR as active */
|
|
data->msr_mask_on |= UART_MSR_DSR;
|
|
data->msr_mask_off |= UART_MSR_DDSR;
|
|
}
|
|
|
|
if (device_property_read_bool(dev, "cts-override")) {
|
|
/* Always report CTS as active */
|
|
data->msr_mask_on |= UART_MSR_CTS;
|
|
data->msr_mask_off |= UART_MSR_DCTS;
|
|
}
|
|
|
|
if (device_property_read_bool(dev, "ri-override")) {
|
|
/* Always report Ring indicator as inactive */
|
|
data->msr_mask_off |= UART_MSR_RI;
|
|
data->msr_mask_off |= UART_MSR_TERI;
|
|
}
|
|
|
|
/* Always ask for fixed clock rate from a property. */
|
|
device_property_read_u32(dev, "clock-frequency", &p->uartclk);
|
|
|
|
/* If there is separate baudclk, get the rate from it. */
|
|
data->clk = devm_clk_get_optional(dev, "baudclk");
|
|
if (data->clk == NULL)
|
|
data->clk = devm_clk_get_optional(dev, NULL);
|
|
if (IS_ERR(data->clk))
|
|
return PTR_ERR(data->clk);
|
|
|
|
INIT_WORK(&data->clk_work, dw8250_clk_work_cb);
|
|
data->clk_notifier.notifier_call = dw8250_clk_notifier_cb;
|
|
|
|
err = clk_prepare_enable(data->clk);
|
|
if (err)
|
|
dev_warn(dev, "could not enable optional baudclk: %d\n", err);
|
|
|
|
if (data->clk)
|
|
p->uartclk = clk_get_rate(data->clk);
|
|
|
|
/* If no clock rate is defined, fail. */
|
|
if (!p->uartclk) {
|
|
dev_err(dev, "clock rate not defined\n");
|
|
err = -EINVAL;
|
|
goto err_clk;
|
|
}
|
|
|
|
data->pclk = devm_clk_get_optional(dev, "apb_pclk");
|
|
if (IS_ERR(data->pclk)) {
|
|
err = PTR_ERR(data->pclk);
|
|
goto err_clk;
|
|
}
|
|
|
|
err = clk_prepare_enable(data->pclk);
|
|
if (err) {
|
|
dev_err(dev, "could not enable apb_pclk\n");
|
|
goto err_clk;
|
|
}
|
|
|
|
data->rst = devm_reset_control_get_optional_exclusive(dev, NULL);
|
|
if (IS_ERR(data->rst)) {
|
|
err = PTR_ERR(data->rst);
|
|
goto err_pclk;
|
|
}
|
|
reset_control_deassert(data->rst);
|
|
|
|
dw8250_quirks(p, data);
|
|
|
|
/* If the Busy Functionality is not implemented, don't handle it */
|
|
if (data->uart_16550_compatible)
|
|
p->handle_irq = NULL;
|
|
|
|
if (!data->skip_autocfg)
|
|
dw8250_setup_port(p);
|
|
|
|
/* If we have a valid fifosize, try hooking up DMA */
|
|
if (p->fifosize) {
|
|
data->data.dma.rxconf.src_maxburst = p->fifosize / 4;
|
|
data->data.dma.txconf.dst_maxburst = p->fifosize / 4;
|
|
up->dma = &data->data.dma;
|
|
}
|
|
|
|
data->data.line = serial8250_register_8250_port(up);
|
|
if (data->data.line < 0) {
|
|
err = data->data.line;
|
|
goto err_reset;
|
|
}
|
|
|
|
/*
|
|
* Some platforms may provide a reference clock shared between several
|
|
* devices. In this case any clock state change must be known to the
|
|
* UART port at least post factum.
|
|
*/
|
|
if (data->clk) {
|
|
err = clk_notifier_register(data->clk, &data->clk_notifier);
|
|
if (err)
|
|
dev_warn(p->dev, "Failed to set the clock notifier\n");
|
|
else
|
|
queue_work(system_unbound_wq, &data->clk_work);
|
|
}
|
|
|
|
platform_set_drvdata(pdev, data);
|
|
|
|
pm_runtime_set_active(dev);
|
|
pm_runtime_enable(dev);
|
|
|
|
return 0;
|
|
|
|
err_reset:
|
|
reset_control_assert(data->rst);
|
|
|
|
err_pclk:
|
|
clk_disable_unprepare(data->pclk);
|
|
|
|
err_clk:
|
|
clk_disable_unprepare(data->clk);
|
|
|
|
return err;
|
|
}
|
|
|
|
static int dw8250_remove(struct platform_device *pdev)
|
|
{
|
|
struct dw8250_data *data = platform_get_drvdata(pdev);
|
|
struct device *dev = &pdev->dev;
|
|
|
|
pm_runtime_get_sync(dev);
|
|
|
|
if (data->clk) {
|
|
clk_notifier_unregister(data->clk, &data->clk_notifier);
|
|
|
|
flush_work(&data->clk_work);
|
|
}
|
|
|
|
serial8250_unregister_port(data->data.line);
|
|
|
|
reset_control_assert(data->rst);
|
|
|
|
clk_disable_unprepare(data->pclk);
|
|
|
|
clk_disable_unprepare(data->clk);
|
|
|
|
pm_runtime_disable(dev);
|
|
pm_runtime_put_noidle(dev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int dw8250_suspend(struct device *dev)
|
|
{
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
serial8250_suspend_port(data->data.line);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dw8250_resume(struct device *dev)
|
|
{
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
serial8250_resume_port(data->data.line);
|
|
|
|
return 0;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
#ifdef CONFIG_PM
|
|
static int dw8250_runtime_suspend(struct device *dev)
|
|
{
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
clk_disable_unprepare(data->clk);
|
|
|
|
clk_disable_unprepare(data->pclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int dw8250_runtime_resume(struct device *dev)
|
|
{
|
|
struct dw8250_data *data = dev_get_drvdata(dev);
|
|
|
|
clk_prepare_enable(data->pclk);
|
|
|
|
clk_prepare_enable(data->clk);
|
|
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static const struct dev_pm_ops dw8250_pm_ops = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(dw8250_suspend, dw8250_resume)
|
|
SET_RUNTIME_PM_OPS(dw8250_runtime_suspend, dw8250_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct of_device_id dw8250_of_match[] = {
|
|
{ .compatible = "snps,dw-apb-uart" },
|
|
{ .compatible = "cavium,octeon-3860-uart" },
|
|
{ .compatible = "marvell,armada-38x-uart" },
|
|
{ .compatible = "renesas,rzn1-uart" },
|
|
{ /* Sentinel */ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, dw8250_of_match);
|
|
|
|
static const struct acpi_device_id dw8250_acpi_match[] = {
|
|
{ "INT33C4", 0 },
|
|
{ "INT33C5", 0 },
|
|
{ "INT3434", 0 },
|
|
{ "INT3435", 0 },
|
|
{ "80860F0A", 0 },
|
|
{ "8086228A", 0 },
|
|
{ "APMC0D08", 0},
|
|
{ "AMD0020", 0 },
|
|
{ "AMDI0020", 0 },
|
|
{ "AMDI0022", 0 },
|
|
{ "BRCM2032", 0 },
|
|
{ "HISI0031", 0 },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(acpi, dw8250_acpi_match);
|
|
|
|
static struct platform_driver dw8250_platform_driver = {
|
|
.driver = {
|
|
.name = "dw-apb-uart",
|
|
.pm = &dw8250_pm_ops,
|
|
.of_match_table = dw8250_of_match,
|
|
.acpi_match_table = ACPI_PTR(dw8250_acpi_match),
|
|
},
|
|
.probe = dw8250_probe,
|
|
.remove = dw8250_remove,
|
|
};
|
|
|
|
module_platform_driver(dw8250_platform_driver);
|
|
|
|
MODULE_AUTHOR("Jamie Iles");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_DESCRIPTION("Synopsys DesignWare 8250 serial port driver");
|
|
MODULE_ALIAS("platform:dw-apb-uart");
|