mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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ac8786c72e
There are currently no tests for ALU64 shift operations when the shift amount is 0. This adds 6 new tests to make sure they are equivalent to a no-op. The x32 JIT had such bugs that could have been caught by these tests. Cc: Xi Wang <xi.wang@gmail.com> Signed-off-by: Luke Nelson <luke.r.nels@gmail.com> Signed-off-by: Daniel Borkmann <daniel@iogearbox.net>
219 lines
4.5 KiB
C
219 lines
4.5 KiB
C
{
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"add+sub+mul",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_1, 1),
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_1, 2),
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BPF_MOV64_IMM(BPF_REG_2, 3),
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BPF_ALU64_REG(BPF_SUB, BPF_REG_1, BPF_REG_2),
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BPF_ALU64_IMM(BPF_ADD, BPF_REG_1, -1),
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BPF_ALU64_IMM(BPF_MUL, BPF_REG_1, 3),
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BPF_MOV64_REG(BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = -3,
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},
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{
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"xor32 zero extend check",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_2, -1),
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BPF_ALU64_IMM(BPF_LSH, BPF_REG_2, 32),
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BPF_ALU64_IMM(BPF_OR, BPF_REG_2, 0xffff),
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BPF_ALU32_REG(BPF_XOR, BPF_REG_2, BPF_REG_2),
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BPF_MOV32_IMM(BPF_REG_0, 2),
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BPF_JMP_IMM(BPF_JNE, BPF_REG_2, 0, 1),
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BPF_MOV32_IMM(BPF_REG_0, 1),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"arsh32 on imm",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_0, 1),
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BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 5),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 0,
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},
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{
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"arsh32 on imm 2",
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.insns = {
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BPF_LD_IMM64(BPF_REG_0, 0x1122334485667788),
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BPF_ALU32_IMM(BPF_ARSH, BPF_REG_0, 7),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = -16069393,
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},
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{
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"arsh32 on reg",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_0, 1),
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BPF_MOV64_IMM(BPF_REG_1, 5),
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BPF_ALU32_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 0,
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},
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{
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"arsh32 on reg 2",
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.insns = {
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BPF_LD_IMM64(BPF_REG_0, 0xffff55667788),
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BPF_MOV64_IMM(BPF_REG_1, 15),
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BPF_ALU32_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 43724,
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},
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{
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"arsh64 on imm",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_0, 1),
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BPF_ALU64_IMM(BPF_ARSH, BPF_REG_0, 5),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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},
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{
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"arsh64 on reg",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_0, 1),
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BPF_MOV64_IMM(BPF_REG_1, 5),
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BPF_ALU64_REG(BPF_ARSH, BPF_REG_0, BPF_REG_1),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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},
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{
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"lsh64 by 0 imm",
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.insns = {
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BPF_LD_IMM64(BPF_REG_0, 1),
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BPF_LD_IMM64(BPF_REG_1, 1),
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BPF_ALU64_IMM(BPF_LSH, BPF_REG_1, 0),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 1, 1),
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BPF_MOV64_IMM(BPF_REG_0, 2),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"rsh64 by 0 imm",
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.insns = {
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BPF_LD_IMM64(BPF_REG_0, 1),
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BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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BPF_ALU64_IMM(BPF_RSH, BPF_REG_1, 0),
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BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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BPF_MOV64_IMM(BPF_REG_0, 2),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"arsh64 by 0 imm",
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.insns = {
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BPF_LD_IMM64(BPF_REG_0, 1),
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BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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BPF_ALU64_IMM(BPF_ARSH, BPF_REG_1, 0),
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BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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BPF_MOV64_IMM(BPF_REG_0, 2),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"lsh64 by 0 reg",
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.insns = {
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BPF_LD_IMM64(BPF_REG_0, 1),
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BPF_LD_IMM64(BPF_REG_1, 1),
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BPF_LD_IMM64(BPF_REG_2, 0),
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BPF_ALU64_REG(BPF_LSH, BPF_REG_1, BPF_REG_2),
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BPF_JMP_IMM(BPF_JEQ, BPF_REG_1, 1, 1),
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BPF_MOV64_IMM(BPF_REG_0, 2),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"rsh64 by 0 reg",
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.insns = {
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BPF_LD_IMM64(BPF_REG_0, 1),
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BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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BPF_LD_IMM64(BPF_REG_3, 0),
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BPF_ALU64_REG(BPF_RSH, BPF_REG_1, BPF_REG_3),
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BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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BPF_MOV64_IMM(BPF_REG_0, 2),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"arsh64 by 0 reg",
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.insns = {
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BPF_LD_IMM64(BPF_REG_0, 1),
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BPF_LD_IMM64(BPF_REG_1, 0x100000000LL),
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BPF_ALU64_REG(BPF_MOV, BPF_REG_2, BPF_REG_1),
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BPF_LD_IMM64(BPF_REG_3, 0),
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BPF_ALU64_REG(BPF_ARSH, BPF_REG_1, BPF_REG_3),
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BPF_JMP_REG(BPF_JEQ, BPF_REG_1, BPF_REG_2, 1),
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BPF_MOV64_IMM(BPF_REG_0, 2),
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BPF_EXIT_INSN(),
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},
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.result = ACCEPT,
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.retval = 1,
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},
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{
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"invalid 64-bit BPF_END",
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.insns = {
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BPF_MOV32_IMM(BPF_REG_0, 0),
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{
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.code = BPF_ALU64 | BPF_END | BPF_TO_LE,
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.dst_reg = BPF_REG_0,
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.src_reg = 0,
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.off = 0,
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.imm = 32,
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},
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BPF_EXIT_INSN(),
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},
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.errstr = "unknown opcode d7",
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.result = REJECT,
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},
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{
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"mov64 src == dst",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_2, 0),
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BPF_MOV64_REG(BPF_REG_2, BPF_REG_2),
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// Check bounds are OK
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BPF_ALU64_REG(BPF_ADD, BPF_REG_1, BPF_REG_2),
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BPF_MOV64_IMM(BPF_REG_0, 0),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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},
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{
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"mov64 src != dst",
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.insns = {
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BPF_MOV64_IMM(BPF_REG_3, 0),
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BPF_MOV64_REG(BPF_REG_2, BPF_REG_3),
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// Check bounds are OK
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BPF_ALU64_REG(BPF_ADD, BPF_REG_1, BPF_REG_2),
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BPF_MOV64_IMM(BPF_REG_0, 0),
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BPF_EXIT_INSN(),
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},
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.prog_type = BPF_PROG_TYPE_SCHED_CLS,
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.result = ACCEPT,
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},
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