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A cxl_decoder is a child of a cxl_port. It represents a hardware decoder
configuration of an upstream port to one or more of its downstream
ports. The decoder is either represented in CXL standard HDM decoder
registers (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder Capability
Structure), or it is a static decode configuration communicated by
platform firmware (see the CXL Early Discovery Table: Fixed Memory
Window Structure).
The firmware described and hardware described decoders differ slightly
leading to 2 different sub-types of decoders, cxl_decoder_root and
cxl_decoder_switch. At the root level the decode capabilities restrict
what can be mapped beneath them. Mid-level switch decoders are
configured for either acclerator (type-2) or memory-expander (type-3)
operation, but they are otherwise agnostic to the type of memory
(volatile vs persistent) being mapped.
Here is an example topology from a single-ported host-bridge environment
without CFMWS decodes enumerated.
/sys/bus/cxl/devices/root0
├── devtype
├── dport0 -> ../../../LNXSYSTM:00/LNXSYBUS:00/ACPI0016:00
├── port1
│ ├── decoder1.0
│ │ ├── devtype
│ │ ├── locked
│ │ ├── size
│ │ ├── start
│ │ ├── subsystem -> ../../../../../../bus/cxl
│ │ ├── target_list
│ │ ├── target_type
│ │ └── uevent
│ ├── devtype
│ ├── dport0 -> ../../../../pci0000:34/0000:34:00.0
│ ├── subsystem -> ../../../../../bus/cxl
│ ├── uevent
│ └── uport -> ../../../../LNXSYSTM:00/LNXSYBUS:00/ACPI0016:00
├── subsystem -> ../../../../bus/cxl
├── uevent
└── uport -> ../../ACPI0017:00
Reviewed-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
Link: https://lore.kernel.org/r/162325695128.2293823.17519927266014762694.stgit@dwillia2-desk3.amr.corp.intel.com
Signed-off-by: Dan Williams <dan.j.williams@intel.com>
129 lines
4.8 KiB
Text
129 lines
4.8 KiB
Text
What: /sys/bus/cxl/devices/memX/firmware_version
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "FW Revision" string as reported by the Identify
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Memory Device Output Payload in the CXL-2.0
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specification.
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What: /sys/bus/cxl/devices/memX/ram/size
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "Volatile Only Capacity" as bytes. Represents the
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identically named field in the Identify Memory Device Output
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Payload in the CXL-2.0 specification.
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What: /sys/bus/cxl/devices/memX/pmem/size
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Date: December, 2020
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KernelVersion: v5.12
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Contact: linux-cxl@vger.kernel.org
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Description:
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(RO) "Persistent Only Capacity" as bytes. Represents the
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identically named field in the Identify Memory Device Output
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Payload in the CXL-2.0 specification.
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What: /sys/bus/cxl/devices/*/devtype
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL device objects export the devtype attribute which mirrors
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the same value communicated in the DEVTYPE environment variable
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for uevents for devices on the "cxl" bus.
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What: /sys/bus/cxl/devices/portX/uport
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL port objects are enumerated from either a platform firmware
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device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
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CXL component registers. The 'uport' symlink connects the CXL
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portX object to the device that published the CXL port
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capability.
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What: /sys/bus/cxl/devices/portX/dportY
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL port objects are enumerated from either a platform firmware
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device (ACPI0017 and ACPI0016) or PCIe switch upstream port with
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CXL component registers. The 'dportY' symlink identifies one or
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more downstream ports that the upstream port may target in its
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decode of CXL memory resources. The 'Y' integer reflects the
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hardware port unique-id used in the hardware decoder target
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list.
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What: /sys/bus/cxl/devices/decoderX.Y
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL decoder objects are enumerated from either a platform
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firmware description, or a CXL HDM decoder register set in a
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PCIe device (see CXL 2.0 section 8.2.5.12 CXL HDM Decoder
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Capability Structure). The 'X' in decoderX.Y represents the
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cxl_port container of this decoder, and 'Y' represents the
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instance id of a given decoder resource.
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What: /sys/bus/cxl/devices/decoderX.Y/{start,size}
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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The 'start' and 'size' attributes together convey the physical
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address base and number of bytes mapped in the decoder's decode
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window. For decoders of devtype "cxl_decoder_root" the address
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range is fixed. For decoders of devtype "cxl_decoder_switch" the
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address is bounded by the decode range of the cxl_port ancestor
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of the decoder's cxl_port, and dynamically updates based on the
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active memory regions in that address space.
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What: /sys/bus/cxl/devices/decoderX.Y/locked
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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CXL HDM decoders have the capability to lock the configuration
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until the next device reset. For decoders of devtype
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"cxl_decoder_root" there is no standard facility to unlock them.
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For decoders of devtype "cxl_decoder_switch" a secondary bus
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reset, of the PCIe bridge that provides the bus for this
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decoders uport, unlocks / resets the decoder.
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What: /sys/bus/cxl/devices/decoderX.Y/target_list
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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Display a comma separated list of the current decoder target
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configuration. The list is ordered by the current configured
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interleave order of the decoder's dport instances. Each entry in
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the list is a dport id.
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What: /sys/bus/cxl/devices/decoderX.Y/cap_{pmem,ram,type2,type3}
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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When a CXL decoder is of devtype "cxl_decoder_root", it
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represents a fixed memory window identified by platform
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firmware. A fixed window may only support a subset of memory
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types. The 'cap_*' attributes indicate whether persistent
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memory, volatile memory, accelerator memory, and / or expander
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memory may be mapped behind this decoder's memory window.
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What: /sys/bus/cxl/devices/decoderX.Y/target_type
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Date: June, 2021
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KernelVersion: v5.14
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Contact: linux-cxl@vger.kernel.org
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Description:
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When a CXL decoder is of devtype "cxl_decoder_switch", it can
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optionally decode either accelerator memory (type-2) or expander
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memory (type-3). The 'target_type' attribute indicates the
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current setting which may dynamically change based on what
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memory regions are activated in this decode hierarchy.
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