mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-11-01 00:48:50 +00:00
a5f2246fb9
nand-controller.yaml replaced nand.txt however the references to it were
not updated. This change updates these references wherever it appears in
bindings documentation.
Fixes: 212e496935 ("dt-bindings: mtd: Add YAML schemas for the generic NAND options")
Signed-off-by: Kamal Dasu <kdasu.kdev@gmail.com>
Signed-off-by: Rob Herring <robh@kernel.org>
64 lines
2 KiB
Text
64 lines
2 KiB
Text
NVIDIA Tegra NAND Flash controller
|
|
|
|
Required properties:
|
|
- compatible: Must be one of:
|
|
- "nvidia,tegra20-nand"
|
|
- reg: MMIO address range
|
|
- interrupts: interrupt output of the NFC controller
|
|
- clocks: Must contain an entry for each entry in clock-names.
|
|
See ../clocks/clock-bindings.txt for details.
|
|
- clock-names: Must include the following entries:
|
|
- nand
|
|
- resets: Must contain an entry for each entry in reset-names.
|
|
See ../reset/reset.txt for details.
|
|
- reset-names: Must include the following entries:
|
|
- nand
|
|
|
|
Optional children nodes:
|
|
Individual NAND chips are children of the NAND controller node. Currently
|
|
only one NAND chip supported.
|
|
|
|
Required children node properties:
|
|
- reg: An integer ranging from 1 to 6 representing the CS line to use.
|
|
|
|
Optional children node properties:
|
|
- nand-ecc-mode: String, operation mode of the NAND ecc mode. Currently only
|
|
"hw" is supported.
|
|
- nand-ecc-algo: string, algorithm of NAND ECC.
|
|
Supported values with "hw" ECC mode are: "rs", "bch".
|
|
- nand-bus-width : See nand-controller.yaml
|
|
- nand-on-flash-bbt: See nand-controller.yaml
|
|
- nand-ecc-strength: integer representing the number of bits to correct
|
|
per ECC step (always 512). Supported strength using HW ECC
|
|
modes are:
|
|
- RS: 4, 6, 8
|
|
- BCH: 4, 8, 14, 16
|
|
- nand-ecc-maximize: See nand-controller.yaml
|
|
- nand-is-boot-medium: Makes sure only ECC strengths supported by the boot ROM
|
|
are chosen.
|
|
- wp-gpios: GPIO specifier for the write protect pin.
|
|
|
|
Optional child node of NAND chip nodes:
|
|
Partitions: see partition.txt
|
|
|
|
Example:
|
|
nand-controller@70008000 {
|
|
compatible = "nvidia,tegra20-nand";
|
|
reg = <0x70008000 0x100>;
|
|
interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&tegra_car TEGRA20_CLK_NDFLASH>;
|
|
clock-names = "nand";
|
|
resets = <&tegra_car 13>;
|
|
reset-names = "nand";
|
|
|
|
nand@0 {
|
|
reg = <0>;
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
nand-bus-width = <8>;
|
|
nand-on-flash-bbt;
|
|
nand-ecc-algo = "bch";
|
|
nand-ecc-strength = <8>;
|
|
wp-gpios = <&gpio TEGRA_GPIO(S, 0) GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|