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2f92512e1c
Extend dt-bindings for lan966x with ptp interrupt. This is generated when doing 2-step timestamping and the timestamp can be read from the FIFO. Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: David S. Miller <davem@davemloft.net>
171 lines
3.7 KiB
YAML
171 lines
3.7 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/microchip,lan966x-switch.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Microchip Lan966x Ethernet switch controller
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maintainers:
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- Horatiu Vultur <horatiu.vultur@microchip.com>
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description: |
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The lan966x switch is a multi-port Gigabit AVB/TSN Ethernet Switch with
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two integrated 10/100/1000Base-T PHYs. In addition to the integrated PHYs,
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it supports up to 2RGMII/RMII, up to 3BASE-X/SERDES/2.5GBASE-X and up to
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2 Quad-SGMII/Quad-USGMII interfaces.
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properties:
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$nodename:
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pattern: "^switch@[0-9a-f]+$"
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compatible:
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const: microchip,lan966x-switch
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reg:
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items:
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- description: cpu target
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- description: general control block target
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reg-names:
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items:
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- const: cpu
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- const: gcb
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interrupts:
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minItems: 1
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items:
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- description: register based extraction
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- description: frame dma based extraction
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- description: analyzer interrupt
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- description: ptp interrupt
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interrupt-names:
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minItems: 1
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items:
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- const: xtr
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- const: fdma
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- const: ana
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- const: ptp
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resets:
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items:
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- description: Reset controller used for switch core reset (soft reset)
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- description: Reset controller used for releasing the phy from reset
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reset-names:
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items:
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- const: switch
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- const: phy
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ethernet-ports:
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type: object
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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additionalProperties: false
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patternProperties:
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"^port@[0-9a-f]+$":
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type: object
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$ref: "/schemas/net/ethernet-controller.yaml#"
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unevaluatedProperties: false
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properties:
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'#address-cells':
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const: 1
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'#size-cells':
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const: 0
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reg:
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description:
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Switch port number
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phys:
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description:
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Phandle of a Ethernet SerDes PHY
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phy-mode:
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description:
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This specifies the interface used by the Ethernet SerDes towards
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the PHY or SFP.
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enum:
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- gmii
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- sgmii
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- qsgmii
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- 1000base-x
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- 2500base-x
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phy-handle:
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description:
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Phandle of a Ethernet PHY.
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sfp:
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description:
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Phandle of an SFP.
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managed: true
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required:
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- reg
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- phys
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- phy-mode
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oneOf:
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- required:
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- phy-handle
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- required:
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- sfp
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- managed
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required:
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- compatible
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- reg
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- reg-names
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- interrupts
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- interrupt-names
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- resets
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- reset-names
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- ethernet-ports
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additionalProperties: false
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examples:
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- |
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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switch: switch@e0000000 {
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compatible = "microchip,lan966x-switch";
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reg = <0xe0000000 0x0100000>,
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<0xe2000000 0x0800000>;
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reg-names = "cpu", "gcb";
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interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "xtr";
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resets = <&switch_reset 0>, <&phy_reset 0>;
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reset-names = "switch", "phy";
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ethernet-ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port0: port@0 {
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reg = <0>;
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phy-handle = <&phy0>;
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phys = <&serdes 0 0>;
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phy-mode = "gmii";
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};
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port1: port@1 {
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reg = <1>;
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sfp = <&sfp_eth1>;
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managed = "in-band-status";
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phys = <&serdes 2 4>;
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phy-mode = "sgmii";
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};
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};
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};
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...
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