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2a4c32e767
The new added properties resource "reg" is for configuring ethernet LDO in the IPQ5018 chipset, the property "clocks" is for configuring the MDIO clock source frequency. Signed-off-by: Luo Jie <luoj@codeaurora.org> Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: David S. Miller <davem@davemloft.net>
76 lines
1.5 KiB
YAML
76 lines
1.5 KiB
YAML
# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
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%YAML 1.2
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---
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$id: http://devicetree.org/schemas/net/qcom,ipq4019-mdio.yaml#
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$schema: http://devicetree.org/meta-schemas/core.yaml#
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title: Qualcomm IPQ40xx MDIO Controller Device Tree Bindings
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maintainers:
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- Robert Marko <robert.marko@sartura.hr>
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allOf:
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- $ref: "mdio.yaml#"
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properties:
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compatible:
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enum:
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- qcom,ipq4019-mdio
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- qcom,ipq5018-mdio
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"#address-cells":
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const: 1
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"#size-cells":
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const: 0
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reg:
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minItems: 1
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maxItems: 2
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description:
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the first Address and length of the register set for the MDIO controller.
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the second Address and length of the register for ethernet LDO, this second
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address range is only required by the platform IPQ50xx.
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clocks:
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maxItems: 1
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description: |
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MDIO clock source frequency fixed to 100MHZ, this clock should be specified
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by the platform IPQ807x, IPQ60xx and IPQ50xx.
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required:
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- compatible
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- reg
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- "#address-cells"
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- "#size-cells"
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unevaluatedProperties: false
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examples:
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- |
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mdio@90000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "qcom,ipq4019-mdio";
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reg = <0x90000 0x64>;
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ethphy0: ethernet-phy@0 {
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reg = <0>;
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};
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ethphy1: ethernet-phy@1 {
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reg = <1>;
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};
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ethphy2: ethernet-phy@2 {
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reg = <2>;
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};
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ethphy3: ethernet-phy@3 {
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reg = <3>;
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};
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ethphy4: ethernet-phy@4 {
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reg = <4>;
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};
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};
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