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b0d98dc504
The IO access of PCI is not supported in R7780RP and the MS7780SE board now. The support of the IO access mode of e100 and a lot of IDE chips becomes possible by fixing the code. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org> Signed-off-by: Paul Mundt <lethal@linux-sh.org>
96 lines
2.6 KiB
C
96 lines
2.6 KiB
C
/*
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* linux/arch/sh/drivers/pci/ops-se7780.c
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*
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* Copyright (C) 2006 Nobuhiro Iwamatsu
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*
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* PCI initialization for the Hitachi UL Solution Engine 7780SE03
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*
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* May be copied or modified under the terms of the GNU General Public
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* License. See linux/COPYING for more information.
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*/
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#include <linux/kernel.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/pci.h>
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#include <asm/se7780.h>
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#include <asm/io.h>
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#include "pci-sh4.h"
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/*
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* IDSEL = AD16 PCI slot
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* IDSEL = AD17 PCI slot
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* IDSEL = AD18 Serial ATA Controller (Silicon Image SiL3512A)
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* IDSEL = AD19 USB Host Controller (NEC uPD7210100A)
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*/
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/* IDSEL [16][17][18][19][20][21][22][23][24][25][26][27][28][29][30][31] */
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static char se7780_irq_tab[4][16] __initdata = {
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/* INTA */
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{ 65, 68, 67, 68, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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/* INTB */
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{ 66, 65, -1, 65, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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/* INTC */
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{ 67, 66, -1, 66, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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/* INTD */
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{ 68, 67, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1, -1 },
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};
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int __init pcibios_map_platform_irq(struct pci_dev *pdev, u8 slot, u8 pin)
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{
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return se7780_irq_tab[pin-1][slot];
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}
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static struct resource se7780_io_resource = {
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.name = "SH7780_IO",
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.start = SH7780_PCI_IO_BASE,
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.end = SH7780_PCI_IO_BASE + SH7780_PCI_IO_SIZE - 1,
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.flags = IORESOURCE_IO
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};
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static struct resource se7780_mem_resource = {
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.name = "SH7780_mem",
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.start = SH7780_PCI_MEMORY_BASE,
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.end = SH7780_PCI_MEMORY_BASE + SH7780_PCI_MEM_SIZE - 1,
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.flags = IORESOURCE_MEM
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};
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extern struct pci_ops se7780_pci_ops;
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struct pci_channel board_pci_channels[] = {
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{ &sh4_pci_ops, &se7780_io_resource, &se7780_mem_resource, 0, 0xff },
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{ NULL, NULL, NULL, 0, 0 },
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};
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EXPORT_SYMBOL(board_pci_channels);
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static struct sh4_pci_address_map se7780_pci_map = {
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.window0 = {
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.base = SH7780_CS2_BASE_ADDR,
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.size = 0x04000000,
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},
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.flags = SH4_PCIC_NO_RESET,
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};
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int __init pcibios_init_platform(void)
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{
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printk("SH7780 PCI: Finished initialization of the PCI controller\n");
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/*
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* FPGA PCISEL register initialize
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*
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* CPU || SLOT1 | SLOT2 | S-ATA | USB
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* -------------------------------------
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* INTA || INTA | INTD | -- | INTB
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* -------------------------------------
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* INTB || INTB | INTA | -- | INTC
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* -------------------------------------
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* INTC || INTC | INTB | INTA | --
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* -------------------------------------
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* INTD || INTD | INTC | -- | INTA
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* -------------------------------------
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*/
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ctrl_outw(0x0013, FPGA_PCI_INTSEL1);
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ctrl_outw(0xE402, FPGA_PCI_INTSEL2);
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return sh7780_pcic_init(&se7780_pci_map);
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}
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