mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-28 21:33:52 +00:00
af6af87d7e
We continue to see a lot of new material. I've highlighted some of it
below, but there's been more beyond that as well.
One of the sweeping changes is that many boards have seen their ARM Mali
GPU devices added to device trees, since the DRM drivers have now been
merged.
So, with the caveat that I have surely missed several great
contributions, here's a collection of the material this time around:
New SoCs:
- Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53)
- TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA)
- Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53)
New Boards / platforms:
- Aspeed BMC support for a number of new server platforms
- Kontron SMARC SoM (several i.MX6 versions)
- Novtech's Meerkat96 (i.MX7)
- ST Micro Avenger96 board
- Hardkernel ODROID-N2 (Amlogic G12B)
- Purism Librem5 devkit (i.MX8MQ)
- Google Cheza (Qualcomm SDM845)
- Qualcomm Dragonboard 845c (Qualcomm SDM845)
- Hugsun X99 TV Box (Rockchip RK3399)
- Khadas Edge/Edge-V/Captain (Rockchip RK3399)
Updated / expanded boards and platforms:
- Renesas r7s9210 has a lot of new peripherals added
- Polish and fixes for Rockchip-based Chromebooks
- Amlogic G12A has a lot of peripherals added
- Nvidia Jetson Nano sees various fixes and improvements, and is now at
feature parity with TX1
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc
Pull ARM Devicetree updates from Olof Johansson:
"We continue to see a lot of new material. I've highlighted some of it
below, but there's been more beyond that as well.
One of the sweeping changes is that many boards have seen their ARM
Mali GPU devices added to device trees, since the DRM drivers have now
been merged.
So, with the caveat that I have surely missed several great
contributions, here's a collection of the material this time around:
New SoCs:
- Mediatek mt8183 (4x Cortex-A73 + 4x Cortex-A53)
- TI J721E (2x Cortex-A72 + 3x Cortex-R5F + 3 DSPs + MMA)
- Amlogic G12B (4x Cortex-A73 + 2x Cortex-A53)
New Boards / platforms:
- Aspeed BMC support for a number of new server platforms
- Kontron SMARC SoM (several i.MX6 versions)
- Novtech's Meerkat96 (i.MX7)
- ST Micro Avenger96 board
- Hardkernel ODROID-N2 (Amlogic G12B)
- Purism Librem5 devkit (i.MX8MQ)
- Google Cheza (Qualcomm SDM845)
- Qualcomm Dragonboard 845c (Qualcomm SDM845)
- Hugsun X99 TV Box (Rockchip RK3399)
- Khadas Edge/Edge-V/Captain (Rockchip RK3399)
Updated / expanded boards and platforms:
- Renesas r7s9210 has a lot of new peripherals added
- Fixes and polish for Rockchip-based Chromebooks
- Amlogic G12A has a lot of peripherals added
- Nvidia Jetson Nano sees various fixes and improvements, and is now
at feature parity with TX1"
* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (586 commits)
ARM: dts: gemini: Set DIR-685 SPI CS as active low
ARM: dts: exynos: Adjust buck[78] regulators to supported values on Arndale Octa
ARM: dts: exynos: Adjust buck[78] regulators to supported values on Odroid XU3 family
ARM: dts: exynos: Move Mali400 GPU node to "/soc"
ARM: dts: exynos: Fix imprecise abort on Mali GPU probe on Exynos4210
arm64: dts: qcom: qcs404: Add missing space for cooling-cells property
arm64: dts: rockchip: Fix USB3 Type-C on rk3399-sapphire
arm64: dts: rockchip: Update DWC3 modules on RK3399 SoCs
arm64: dts: rockchip: enable rk3328 watchdog clock
ARM: dts: rockchip: add display nodes for rk322x
ARM: dts: rockchip: fix vop iommu-cells on rk322x
arm64: dts: rockchip: Add support for Hugsun X99 TV Box
arm64: dts: rockchip: Define values for the IPA governor for rock960
arm64: dts: rockchip: Fix multiple thermal zones conflict in rk3399.dtsi
arm64: dts: rockchip: add core dtsi file for RK3399Pro SoCs
arm64: dts: rockchip: improve rk3328-roc-cc rgmii performance.
Revert "ARM: dts: rockchip: set PWM delay backlight settings for Minnie"
ARM: dts: rockchip: Configure BT_DEV_WAKE in on rk3288-veyron
arm64: dts: qcom: sdm845-cheza: add initial cheza dt
ARM: dts: msm8974-FP2: Add vibration motor
...
1066 lines
30 KiB
Text
1066 lines
30 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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//
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// Copyright 2015 Freescale Semiconductor, Inc.
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#include <dt-bindings/clock/imx6ul-clock.h>
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/interrupt-controller/arm-gic.h>
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#include "imx6ul-pinfunc.h"
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/ {
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#address-cells = <1>;
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#size-cells = <1>;
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/*
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* The decompressor and also some bootloaders rely on a
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* pre-existing /chosen node to be available to insert the
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* command line and merge other ATAGS info.
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*/
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chosen {};
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aliases {
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ethernet0 = &fec1;
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ethernet1 = &fec2;
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gpio0 = &gpio1;
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gpio1 = &gpio2;
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gpio2 = &gpio3;
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gpio3 = &gpio4;
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gpio4 = &gpio5;
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i2c0 = &i2c1;
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i2c1 = &i2c2;
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i2c2 = &i2c3;
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i2c3 = &i2c4;
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mmc0 = &usdhc1;
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mmc1 = &usdhc2;
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serial0 = &uart1;
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serial1 = &uart2;
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serial2 = &uart3;
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serial3 = &uart4;
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serial4 = &uart5;
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serial5 = &uart6;
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serial6 = &uart7;
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serial7 = &uart8;
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sai1 = &sai1;
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sai2 = &sai2;
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sai3 = &sai3;
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spi0 = &ecspi1;
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spi1 = &ecspi2;
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spi2 = &ecspi3;
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spi3 = &ecspi4;
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usbphy0 = &usbphy1;
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usbphy1 = &usbphy2;
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};
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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compatible = "arm,cortex-a7";
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device_type = "cpu";
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reg = <0>;
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clock-frequency = <696000000>;
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clock-latency = <61036>; /* two CLK32 periods */
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#cooling-cells = <2>;
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operating-points = <
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/* kHz uV */
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696000 1275000
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528000 1175000
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396000 1025000
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198000 950000
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>;
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fsl,soc-operating-points = <
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/* KHz uV */
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696000 1275000
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528000 1175000
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396000 1175000
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198000 1175000
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>;
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clocks = <&clks IMX6UL_CLK_ARM>,
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<&clks IMX6UL_CLK_PLL2_BUS>,
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<&clks IMX6UL_CLK_PLL2_PFD2>,
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<&clks IMX6UL_CA7_SECONDARY_SEL>,
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<&clks IMX6UL_CLK_STEP>,
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<&clks IMX6UL_CLK_PLL1_SW>,
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<&clks IMX6UL_CLK_PLL1_SYS>;
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clock-names = "arm", "pll2_bus", "pll2_pfd2_396m",
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"secondary_sel", "step", "pll1_sw",
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"pll1_sys";
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arm-supply = <®_arm>;
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soc-supply = <®_soc>;
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nvmem-cells = <&cpu_speed_grade>;
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nvmem-cell-names = "speed_grade";
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};
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};
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intc: interrupt-controller@a01000 {
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compatible = "arm,gic-400", "arm,cortex-a7-gic";
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interrupts = <GIC_PPI 9 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_HIGH)>;
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#interrupt-cells = <3>;
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interrupt-controller;
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interrupt-parent = <&intc>;
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reg = <0x00a01000 0x1000>,
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<0x00a02000 0x2000>,
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<0x00a04000 0x2000>,
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<0x00a06000 0x2000>;
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};
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timer {
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compatible = "arm,armv7-timer";
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interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
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<GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>;
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interrupt-parent = <&intc>;
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status = "disabled";
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};
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ckil: clock-cli {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <32768>;
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clock-output-names = "ckil";
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};
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osc: clock-osc {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <24000000>;
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clock-output-names = "osc";
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};
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ipp_di0: clock-di0 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "ipp_di0";
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};
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ipp_di1: clock-di1 {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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clock-frequency = <0>;
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clock-output-names = "ipp_di1";
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};
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tempmon: tempmon {
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compatible = "fsl,imx6ul-tempmon", "fsl,imx6sx-tempmon";
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interrupt-parent = <&gpc>;
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interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>;
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fsl,tempmon = <&anatop>;
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nvmem-cells = <&tempmon_calib>, <&tempmon_temp_grade>;
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nvmem-cell-names = "calib", "temp_grade";
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clocks = <&clks IMX6UL_CLK_PLL3_USB_OTG>;
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};
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pmu {
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compatible = "arm,cortex-a7-pmu";
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interrupt-parent = <&gpc>;
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interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>;
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};
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soc {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "simple-bus";
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interrupt-parent = <&gpc>;
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ranges;
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ocram: sram@900000 {
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compatible = "mmio-sram";
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reg = <0x00900000 0x20000>;
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};
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dma_apbh: dma-apbh@1804000 {
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compatible = "fsl,imx6q-dma-apbh", "fsl,imx28-dma-apbh";
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reg = <0x01804000 0x2000>;
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interrupts = <0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>,
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<0 13 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "gpmi0", "gpmi1", "gpmi2", "gpmi3";
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#dma-cells = <1>;
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dma-channels = <4>;
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clocks = <&clks IMX6UL_CLK_APBHDMA>;
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};
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gpmi: gpmi-nand@1806000 {
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compatible = "fsl,imx6q-gpmi-nand";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x01806000 0x2000>, <0x01808000 0x2000>;
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reg-names = "gpmi-nand", "bch";
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interrupts = <0 15 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "bch";
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clocks = <&clks IMX6UL_CLK_GPMI_IO>,
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<&clks IMX6UL_CLK_GPMI_APB>,
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<&clks IMX6UL_CLK_GPMI_BCH>,
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<&clks IMX6UL_CLK_GPMI_BCH_APB>,
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<&clks IMX6UL_CLK_PER_BCH>;
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clock-names = "gpmi_io", "gpmi_apb", "gpmi_bch",
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"gpmi_bch_apb", "per1_bch";
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dmas = <&dma_apbh 0>;
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dma-names = "rx-tx";
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status = "disabled";
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};
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aips1: aips-bus@2000000 {
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compatible = "fsl,aips-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x100000>;
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ranges;
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spba-bus@2000000 {
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compatible = "fsl,spba-bus", "simple-bus";
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#address-cells = <1>;
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#size-cells = <1>;
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reg = <0x02000000 0x40000>;
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ranges;
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ecspi1: spi@2008000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
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reg = <0x02008000 0x4000>;
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interrupts = <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ECSPI1>,
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<&clks IMX6UL_CLK_ECSPI1>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi2: spi@200c000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
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reg = <0x0200c000 0x4000>;
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interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ECSPI2>,
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<&clks IMX6UL_CLK_ECSPI2>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi3: spi@2010000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
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reg = <0x02010000 0x4000>;
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interrupts = <GIC_SPI 33 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ECSPI3>,
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<&clks IMX6UL_CLK_ECSPI3>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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ecspi4: spi@2014000 {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "fsl,imx6ul-ecspi", "fsl,imx51-ecspi";
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reg = <0x02014000 0x4000>;
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interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_ECSPI4>,
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<&clks IMX6UL_CLK_ECSPI4>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart7: serial@2018000 {
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compatible = "fsl,imx6ul-uart",
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"fsl,imx6q-uart";
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reg = <0x02018000 0x4000>;
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interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_UART7_IPG>,
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<&clks IMX6UL_CLK_UART7_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart1: serial@2020000 {
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compatible = "fsl,imx6ul-uart",
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"fsl,imx6q-uart";
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reg = <0x02020000 0x4000>;
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interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_UART1_IPG>,
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<&clks IMX6UL_CLK_UART1_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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uart8: serial@2024000 {
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compatible = "fsl,imx6ul-uart",
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"fsl,imx6q-uart";
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reg = <0x02024000 0x4000>;
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interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_UART8_IPG>,
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<&clks IMX6UL_CLK_UART8_SERIAL>;
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clock-names = "ipg", "per";
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status = "disabled";
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};
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sai1: sai@2028000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
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reg = <0x02028000 0x4000>;
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interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_SAI1_IPG>,
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<&clks IMX6UL_CLK_SAI1>,
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<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma 35 24 0>,
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<&sdma 36 24 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai2: sai@202c000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
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reg = <0x0202c000 0x4000>;
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interrupts = <GIC_SPI 98 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&clks IMX6UL_CLK_SAI2_IPG>,
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<&clks IMX6UL_CLK_SAI2>,
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<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
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clock-names = "bus", "mclk1", "mclk2", "mclk3";
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dmas = <&sdma 37 24 0>,
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<&sdma 38 24 0>;
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dma-names = "rx", "tx";
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status = "disabled";
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};
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sai3: sai@2030000 {
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#sound-dai-cells = <0>;
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compatible = "fsl,imx6ul-sai", "fsl,imx6sx-sai";
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reg = <0x02030000 0x4000>;
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interrupts = <GIC_SPI 24 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_SAI3_IPG>,
|
|
<&clks IMX6UL_CLK_SAI3>,
|
|
<&clks IMX6UL_CLK_DUMMY>, <&clks IMX6UL_CLK_DUMMY>;
|
|
clock-names = "bus", "mclk1", "mclk2", "mclk3";
|
|
dmas = <&sdma 39 24 0>,
|
|
<&sdma 40 24 0>;
|
|
dma-names = "rx", "tx";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
tsc: tsc@2040000 {
|
|
compatible = "fsl,imx6ul-tsc";
|
|
reg = <0x02040000 0x4000>, <0x0219c000 0x4000>;
|
|
interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_IPG>,
|
|
<&clks IMX6UL_CLK_ADC2>;
|
|
clock-names = "tsc", "adc";
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm1: pwm@2080000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02080000 0x4000>;
|
|
interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM1>,
|
|
<&clks IMX6UL_CLK_PWM1>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm2: pwm@2084000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02084000 0x4000>;
|
|
interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM2>,
|
|
<&clks IMX6UL_CLK_PWM2>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm3: pwm@2088000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x02088000 0x4000>;
|
|
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM3>,
|
|
<&clks IMX6UL_CLK_PWM3>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm4: pwm@208c000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x0208c000 0x4000>;
|
|
interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM4>,
|
|
<&clks IMX6UL_CLK_PWM4>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can1: flexcan@2090000 {
|
|
compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
|
|
reg = <0x02090000 0x4000>;
|
|
interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_CAN1_IPG>,
|
|
<&clks IMX6UL_CLK_CAN1_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
fsl,stop-mode = <&gpr 0x10 1 0x10 17>;
|
|
status = "disabled";
|
|
};
|
|
|
|
can2: flexcan@2094000 {
|
|
compatible = "fsl,imx6ul-flexcan", "fsl,imx6q-flexcan";
|
|
reg = <0x02094000 0x4000>;
|
|
interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_CAN2_IPG>,
|
|
<&clks IMX6UL_CLK_CAN2_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
fsl,stop-mode = <&gpr 0x10 2 0x10 18>;
|
|
status = "disabled";
|
|
};
|
|
|
|
gpt1: gpt@2098000 {
|
|
compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
|
|
reg = <0x02098000 0x4000>;
|
|
interrupts = <GIC_SPI 55 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_GPT1_BUS>,
|
|
<&clks IMX6UL_CLK_GPT1_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
gpio1: gpio@209c000 {
|
|
compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
|
|
reg = <0x0209c000 0x4000>;
|
|
interrupts = <GIC_SPI 66 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 67 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_GPIO1>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 23 10>, <&iomuxc 10 17 6>,
|
|
<&iomuxc 16 33 16>;
|
|
};
|
|
|
|
gpio2: gpio@20a0000 {
|
|
compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a0000 0x4000>;
|
|
interrupts = <GIC_SPI 68 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 69 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_GPIO2>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 49 16>, <&iomuxc 16 111 6>;
|
|
};
|
|
|
|
gpio3: gpio@20a4000 {
|
|
compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a4000 0x4000>;
|
|
interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_GPIO3>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 65 29>;
|
|
};
|
|
|
|
gpio4: gpio@20a8000 {
|
|
compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020a8000 0x4000>;
|
|
interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_GPIO4>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 94 17>, <&iomuxc 17 117 12>;
|
|
};
|
|
|
|
gpio5: gpio@20ac000 {
|
|
compatible = "fsl,imx6ul-gpio", "fsl,imx35-gpio";
|
|
reg = <0x020ac000 0x4000>;
|
|
interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_GPIO5>;
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <2>;
|
|
gpio-ranges = <&iomuxc 0 7 10>, <&iomuxc 10 5 2>;
|
|
};
|
|
|
|
fec2: ethernet@20b4000 {
|
|
compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
|
|
reg = <0x020b4000 0x4000>;
|
|
interrupt-names = "int0", "pps";
|
|
interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 121 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_ENET>,
|
|
<&clks IMX6UL_CLK_ENET_AHB>,
|
|
<&clks IMX6UL_CLK_ENET_PTP>,
|
|
<&clks IMX6UL_CLK_ENET2_REF_125M>,
|
|
<&clks IMX6UL_CLK_ENET2_REF_125M>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
fsl,num-tx-queues=<1>;
|
|
fsl,num-rx-queues=<1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
kpp: kpp@20b8000 {
|
|
compatible = "fsl,imx6ul-kpp", "fsl,imx6q-kpp", "fsl,imx21-kpp";
|
|
reg = <0x020b8000 0x4000>;
|
|
interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_KPP>;
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog1: wdog@20bc000 {
|
|
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020bc000 0x4000>;
|
|
interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_WDOG1>;
|
|
};
|
|
|
|
wdog2: wdog@20c0000 {
|
|
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
|
|
reg = <0x020c0000 0x4000>;
|
|
interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_WDOG2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
clks: ccm@20c4000 {
|
|
compatible = "fsl,imx6ul-ccm";
|
|
reg = <0x020c4000 0x4000>;
|
|
interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
|
|
#clock-cells = <1>;
|
|
clocks = <&ckil>, <&osc>, <&ipp_di0>, <&ipp_di1>;
|
|
clock-names = "ckil", "osc", "ipp_di0", "ipp_di1";
|
|
};
|
|
|
|
anatop: anatop@20c8000 {
|
|
compatible = "fsl,imx6ul-anatop", "fsl,imx6q-anatop",
|
|
"syscon", "simple-bus";
|
|
reg = <0x020c8000 0x1000>;
|
|
interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 54 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 127 IRQ_TYPE_LEVEL_HIGH>;
|
|
|
|
reg_3p0: regulator-3p0 {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vdd3p0";
|
|
regulator-min-microvolt = <2625000>;
|
|
regulator-max-microvolt = <3400000>;
|
|
anatop-reg-offset = <0x120>;
|
|
anatop-vol-bit-shift = <8>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-min-bit-val = <0>;
|
|
anatop-min-voltage = <2625000>;
|
|
anatop-max-voltage = <3400000>;
|
|
anatop-enable-bit = <0>;
|
|
};
|
|
|
|
reg_arm: regulator-vddcore {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "cpu";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <0>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <24>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
|
|
reg_soc: regulator-vddsoc {
|
|
compatible = "fsl,anatop-regulator";
|
|
regulator-name = "vddsoc";
|
|
regulator-min-microvolt = <725000>;
|
|
regulator-max-microvolt = <1450000>;
|
|
regulator-always-on;
|
|
anatop-reg-offset = <0x140>;
|
|
anatop-vol-bit-shift = <18>;
|
|
anatop-vol-bit-width = <5>;
|
|
anatop-delay-reg-offset = <0x170>;
|
|
anatop-delay-bit-shift = <28>;
|
|
anatop-delay-bit-width = <2>;
|
|
anatop-min-bit-val = <1>;
|
|
anatop-min-voltage = <725000>;
|
|
anatop-max-voltage = <1450000>;
|
|
};
|
|
};
|
|
|
|
usbphy1: usbphy@20c9000 {
|
|
compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020c9000 0x1000>;
|
|
interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USBPHY1>;
|
|
phy-3p0-supply = <®_3p0>;
|
|
fsl,anatop = <&anatop>;
|
|
};
|
|
|
|
usbphy2: usbphy@20ca000 {
|
|
compatible = "fsl,imx6ul-usbphy", "fsl,imx23-usbphy";
|
|
reg = <0x020ca000 0x1000>;
|
|
interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USBPHY2>;
|
|
phy-3p0-supply = <®_3p0>;
|
|
fsl,anatop = <&anatop>;
|
|
};
|
|
|
|
snvs: snvs@20cc000 {
|
|
compatible = "fsl,sec-v4.0-mon", "syscon", "simple-mfd";
|
|
reg = <0x020cc000 0x4000>;
|
|
|
|
snvs_rtc: snvs-rtc-lp {
|
|
compatible = "fsl,sec-v4.0-mon-rtc-lp";
|
|
regmap = <&snvs>;
|
|
offset = <0x34>;
|
|
interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
snvs_poweroff: snvs-poweroff {
|
|
compatible = "syscon-poweroff";
|
|
regmap = <&snvs>;
|
|
offset = <0x38>;
|
|
value = <0x60>;
|
|
mask = <0x60>;
|
|
status = "disabled";
|
|
};
|
|
|
|
snvs_pwrkey: snvs-powerkey {
|
|
compatible = "fsl,sec-v4.0-pwrkey";
|
|
regmap = <&snvs>;
|
|
interrupts = <GIC_SPI 4 IRQ_TYPE_LEVEL_HIGH>;
|
|
linux,keycode = <KEY_POWER>;
|
|
wakeup-source;
|
|
status = "disabled";
|
|
};
|
|
|
|
snvs_lpgpr: snvs-lpgpr {
|
|
compatible = "fsl,imx6ul-snvs-lpgpr";
|
|
};
|
|
};
|
|
|
|
epit1: epit@20d0000 {
|
|
reg = <0x020d0000 0x4000>;
|
|
interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
epit2: epit@20d4000 {
|
|
reg = <0x020d4000 0x4000>;
|
|
interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
src: src@20d8000 {
|
|
compatible = "fsl,imx6ul-src", "fsl,imx51-src";
|
|
reg = <0x020d8000 0x4000>;
|
|
interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
|
|
#reset-cells = <1>;
|
|
};
|
|
|
|
gpc: gpc@20dc000 {
|
|
compatible = "fsl,imx6ul-gpc", "fsl,imx6q-gpc";
|
|
reg = <0x020dc000 0x4000>;
|
|
interrupt-controller;
|
|
#interrupt-cells = <3>;
|
|
interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
|
|
interrupt-parent = <&intc>;
|
|
};
|
|
|
|
iomuxc: iomuxc@20e0000 {
|
|
compatible = "fsl,imx6ul-iomuxc";
|
|
reg = <0x020e0000 0x4000>;
|
|
};
|
|
|
|
gpr: iomuxc-gpr@20e4000 {
|
|
compatible = "fsl,imx6ul-iomuxc-gpr",
|
|
"fsl,imx6q-iomuxc-gpr", "syscon";
|
|
reg = <0x020e4000 0x4000>;
|
|
};
|
|
|
|
gpt2: gpt@20e8000 {
|
|
compatible = "fsl,imx6ul-gpt", "fsl,imx6sx-gpt";
|
|
reg = <0x020e8000 0x4000>;
|
|
interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_GPT2_BUS>,
|
|
<&clks IMX6UL_CLK_GPT2_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
};
|
|
|
|
sdma: sdma@20ec000 {
|
|
compatible = "fsl,imx6ul-sdma", "fsl,imx6q-sdma",
|
|
"fsl,imx35-sdma";
|
|
reg = <0x020ec000 0x4000>;
|
|
interrupts = <GIC_SPI 2 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_IPG>,
|
|
<&clks IMX6UL_CLK_SDMA>;
|
|
clock-names = "ipg", "ahb";
|
|
#dma-cells = <3>;
|
|
fsl,sdma-ram-script-name = "imx/sdma/sdma-imx6q.bin";
|
|
};
|
|
|
|
pwm5: pwm@20f0000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x020f0000 0x4000>;
|
|
interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM5>,
|
|
<&clks IMX6UL_CLK_PWM5>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm6: pwm@20f4000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x020f4000 0x4000>;
|
|
interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM6>,
|
|
<&clks IMX6UL_CLK_PWM6>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm7: pwm@20f8000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x020f8000 0x4000>;
|
|
interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM7>,
|
|
<&clks IMX6UL_CLK_PWM7>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
pwm8: pwm@20fc000 {
|
|
compatible = "fsl,imx6ul-pwm", "fsl,imx27-pwm";
|
|
reg = <0x020fc000 0x4000>;
|
|
interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PWM8>,
|
|
<&clks IMX6UL_CLK_PWM8>;
|
|
clock-names = "ipg", "per";
|
|
#pwm-cells = <2>;
|
|
status = "disabled";
|
|
};
|
|
};
|
|
|
|
aips2: aips-bus@2100000 {
|
|
compatible = "fsl,aips-bus", "simple-bus";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x02100000 0x100000>;
|
|
ranges;
|
|
|
|
crypto: caam@2140000 {
|
|
compatible = "fsl,imx6ul-caam", "fsl,sec-v4.0";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
reg = <0x2140000 0x3c000>;
|
|
ranges = <0 0x2140000 0x3c000>;
|
|
interrupts = <GIC_SPI 48 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_CAAM_IPG>, <&clks IMX6UL_CLK_CAAM_ACLK>,
|
|
<&clks IMX6UL_CLK_CAAM_MEM>;
|
|
clock-names = "ipg", "aclk", "mem";
|
|
|
|
sec_jr0: jr0@1000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x1000 0x1000>;
|
|
interrupts = <GIC_SPI 105 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr1: jr1@2000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x2000 0x1000>;
|
|
interrupts = <GIC_SPI 106 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
|
|
sec_jr2: jr2@3000 {
|
|
compatible = "fsl,sec-v4.0-job-ring";
|
|
reg = <0x3000 0x1000>;
|
|
interrupts = <GIC_SPI 46 IRQ_TYPE_LEVEL_HIGH>;
|
|
};
|
|
};
|
|
|
|
usbotg1: usb@2184000 {
|
|
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
|
|
reg = <0x02184000 0x200>;
|
|
interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy1>;
|
|
fsl,usbmisc = <&usbmisc 0>;
|
|
fsl,anatop = <&anatop>;
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbotg2: usb@2184200 {
|
|
compatible = "fsl,imx6ul-usb", "fsl,imx27-usb";
|
|
reg = <0x02184200 0x200>;
|
|
interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USBOH3>;
|
|
fsl,usbphy = <&usbphy2>;
|
|
fsl,usbmisc = <&usbmisc 1>;
|
|
ahb-burst-config = <0x0>;
|
|
tx-burst-size-dword = <0x10>;
|
|
rx-burst-size-dword = <0x10>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usbmisc: usbmisc@2184800 {
|
|
#index-cells = <1>;
|
|
compatible = "fsl,imx6ul-usbmisc", "fsl,imx6q-usbmisc";
|
|
reg = <0x02184800 0x200>;
|
|
};
|
|
|
|
fec1: ethernet@2188000 {
|
|
compatible = "fsl,imx6ul-fec", "fsl,imx6q-fec";
|
|
reg = <0x02188000 0x4000>;
|
|
interrupt-names = "int0", "pps";
|
|
interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>,
|
|
<GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_ENET>,
|
|
<&clks IMX6UL_CLK_ENET_AHB>,
|
|
<&clks IMX6UL_CLK_ENET_PTP>,
|
|
<&clks IMX6UL_CLK_ENET_REF>,
|
|
<&clks IMX6UL_CLK_ENET_REF>;
|
|
clock-names = "ipg", "ahb", "ptp",
|
|
"enet_clk_ref", "enet_out";
|
|
fsl,num-tx-queues=<1>;
|
|
fsl,num-rx-queues=<1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc1: usdhc@2190000 {
|
|
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
|
|
reg = <0x02190000 0x4000>;
|
|
interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USDHC1>,
|
|
<&clks IMX6UL_CLK_USDHC1>,
|
|
<&clks IMX6UL_CLK_USDHC1>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
fsl,tuning-step= <2>;
|
|
fsl,tuning-start-tap = <20>;
|
|
bus-width = <4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
usdhc2: usdhc@2194000 {
|
|
compatible = "fsl,imx6ul-usdhc", "fsl,imx6sx-usdhc";
|
|
reg = <0x02194000 0x4000>;
|
|
interrupts = <GIC_SPI 23 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_USDHC2>,
|
|
<&clks IMX6UL_CLK_USDHC2>,
|
|
<&clks IMX6UL_CLK_USDHC2>;
|
|
clock-names = "ipg", "ahb", "per";
|
|
bus-width = <4>;
|
|
fsl,tuning-step= <2>;
|
|
fsl,tuning-start-tap = <20>;
|
|
status = "disabled";
|
|
};
|
|
|
|
adc1: adc@2198000 {
|
|
compatible = "fsl,imx6ul-adc", "fsl,vf610-adc";
|
|
reg = <0x02198000 0x4000>;
|
|
interrupts = <GIC_SPI 100 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_ADC1>;
|
|
num-channels = <2>;
|
|
clock-names = "adc";
|
|
fsl,adck-max-frequency = <30000000>, <40000000>,
|
|
<20000000>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c1: i2c@21a0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a0000 0x4000>;
|
|
interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_I2C1>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c2: i2c@21a4000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a4000 0x4000>;
|
|
interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_I2C2>;
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c3: i2c@21a8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021a8000 0x4000>;
|
|
interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_I2C3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
memory-controller@21b0000 {
|
|
compatible = "fsl,imx6ul-mmdc", "fsl,imx6q-mmdc";
|
|
reg = <0x021b0000 0x4000>;
|
|
clocks = <&clks IMX6UL_CLK_MMDC_P0_IPG>;
|
|
};
|
|
|
|
weim: weim@21b8000 {
|
|
#address-cells = <2>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx6ul-weim", "fsl,imx6q-weim";
|
|
reg = <0x021b8000 0x4000>;
|
|
interrupts = <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_EIM>;
|
|
fsl,weim-cs-gpr = <&gpr>;
|
|
status = "disabled";
|
|
};
|
|
|
|
ocotp: ocotp-ctrl@21bc000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
compatible = "fsl,imx6ul-ocotp", "syscon";
|
|
reg = <0x021bc000 0x4000>;
|
|
clocks = <&clks IMX6UL_CLK_OCOTP>;
|
|
|
|
tempmon_calib: calib@38 {
|
|
reg = <0x38 4>;
|
|
};
|
|
|
|
tempmon_temp_grade: temp-grade@20 {
|
|
reg = <0x20 4>;
|
|
};
|
|
|
|
cpu_speed_grade: speed-grade@10 {
|
|
reg = <0x10 4>;
|
|
};
|
|
};
|
|
|
|
lcdif: lcdif@21c8000 {
|
|
compatible = "fsl,imx6ul-lcdif", "fsl,imx28-lcdif";
|
|
reg = <0x021c8000 0x4000>;
|
|
interrupts = <GIC_SPI 5 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_LCDIF_PIX>,
|
|
<&clks IMX6UL_CLK_LCDIF_APB>,
|
|
<&clks IMX6UL_CLK_DUMMY>;
|
|
clock-names = "pix", "axi", "disp_axi";
|
|
status = "disabled";
|
|
};
|
|
|
|
pxp: pxp@21cc000 {
|
|
compatible = "fsl,imx6ul-pxp";
|
|
reg = <0x021cc000 0x4000>;
|
|
interrupts = <GIC_SPI 8 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_PXP>;
|
|
clock-names = "axi";
|
|
};
|
|
|
|
qspi: spi@21e0000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-qspi", "fsl,imx6sx-qspi";
|
|
reg = <0x021e0000 0x4000>, <0x60000000 0x10000000>;
|
|
reg-names = "QuadSPI", "QuadSPI-memory";
|
|
interrupts = <GIC_SPI 107 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_QSPI>,
|
|
<&clks IMX6UL_CLK_QSPI>;
|
|
clock-names = "qspi_en", "qspi";
|
|
status = "disabled";
|
|
};
|
|
|
|
wdog3: wdog@21e4000 {
|
|
compatible = "fsl,imx6ul-wdt", "fsl,imx21-wdt";
|
|
reg = <0x021e4000 0x4000>;
|
|
interrupts = <GIC_SPI 11 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_WDOG3>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart2: serial@21e8000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021e8000 0x4000>;
|
|
interrupts = <GIC_SPI 27 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART2_IPG>,
|
|
<&clks IMX6UL_CLK_UART2_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart3: serial@21ec000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021ec000 0x4000>;
|
|
interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART3_IPG>,
|
|
<&clks IMX6UL_CLK_UART3_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart4: serial@21f0000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021f0000 0x4000>;
|
|
interrupts = <GIC_SPI 29 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART4_IPG>,
|
|
<&clks IMX6UL_CLK_UART4_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
uart5: serial@21f4000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021f4000 0x4000>;
|
|
interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART5_IPG>,
|
|
<&clks IMX6UL_CLK_UART5_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
|
|
i2c4: i2c@21f8000 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
compatible = "fsl,imx6ul-i2c", "fsl,imx21-i2c";
|
|
reg = <0x021f8000 0x4000>;
|
|
interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_I2C4>;
|
|
status = "disabled";
|
|
};
|
|
|
|
uart6: serial@21fc000 {
|
|
compatible = "fsl,imx6ul-uart",
|
|
"fsl,imx6q-uart";
|
|
reg = <0x021fc000 0x4000>;
|
|
interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>;
|
|
clocks = <&clks IMX6UL_CLK_UART6_IPG>,
|
|
<&clks IMX6UL_CLK_UART6_SERIAL>;
|
|
clock-names = "ipg", "per";
|
|
status = "disabled";
|
|
};
|
|
};
|
|
};
|
|
};
|