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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-28 21:33:52 +00:00
00e3ff8b98
The devicetree specification recommends using generic node names. Some Zii dts files already follow such recommendation, but some don't, so use generic node names for consistency among the Zii dts files. Signed-off-by: Fabio Estevam <festevam@gmail.com> Signed-off-by: Shawn Guo <shawnguo@kernel.org>
855 lines
15 KiB
Text
855 lines
15 KiB
Text
// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
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//
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// Copyright (C) 2016-2018 Zodiac Inflight Innovations
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/dts-v1/;
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#include "vf610.dtsi"
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/ {
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model = "ZII VF610 SCU4 AIB";
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compatible = "zii,vf610scu4-aib", "zii,vf610dev", "fsl,vf610";
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chosen {
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stdout-path = &uart0;
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};
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memory@80000000 {
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device_type = "memory";
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reg = <0x80000000 0x20000000>;
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};
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gpio-leds {
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compatible = "gpio-leds";
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pinctrl-0 = <&pinctrl_leds_debug>;
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pinctrl-names = "default";
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debug {
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label = "zii:green:debug1";
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gpios = <&gpio3 0 GPIO_ACTIVE_HIGH>;
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linux,default-trigger = "heartbeat";
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};
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};
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mdio-mux {
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compatible = "mdio-mux-gpio";
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pinctrl-0 = <&pinctrl_mdio_mux>;
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pinctrl-names = "default";
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gpios = <&gpio4 4 GPIO_ACTIVE_HIGH
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&gpio4 5 GPIO_ACTIVE_HIGH
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&gpio3 30 GPIO_ACTIVE_HIGH
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&gpio3 31 GPIO_ACTIVE_HIGH>;
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mdio-parent-bus = <&mdio1>;
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#address-cells = <1>;
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#size-cells = <0>;
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mdio_mux_1: mdio@1 {
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reg = <1>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch0: switch0@0 {
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compatible = "marvell,mv88e6190";
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reg = <0>;
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dsa,member = <0 0>;
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eeprom-length = <65536>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@0 {
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reg = <0>;
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label = "cpu";
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ethernet = <&fec1>;
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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port@1 {
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reg = <1>;
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label = "aib2main_1";
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};
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port@2 {
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reg = <2>;
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label = "aib2main_2";
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};
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port@3 {
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reg = <3>;
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label = "eth_cu_1000_5";
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};
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port@4 {
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reg = <4>;
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label = "eth_cu_1000_6";
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};
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port@5 {
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reg = <5>;
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label = "eth_cu_1000_4";
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};
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port@6 {
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reg = <6>;
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label = "eth_cu_1000_7";
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};
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port@7 {
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reg = <7>;
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label = "modem_pic";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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};
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switch0port10: port@10 {
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reg = <10>;
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label = "dsa";
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phy-mode = "xgmii";
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link = <&switch1port10
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&switch3port10
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&switch2port10>;
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};
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};
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};
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};
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mdio_mux_2: mdio@2 {
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reg = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch1: switch1@0 {
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compatible = "marvell,mv88e6190";
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reg = <0>;
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dsa,member = <0 1>;
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eeprom-length = <65536>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "eth_cu_1000_3";
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};
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port@2 {
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reg = <2>;
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label = "eth_cu_100_2";
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};
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port@3 {
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reg = <3>;
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label = "eth_cu_100_3";
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};
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switch1port9: port@9 {
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reg = <9>;
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label = "dsa";
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phy-mode = "xgmii";
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link = <&switch3port10
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&switch2port10>;
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};
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switch1port10: port@10 {
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reg = <10>;
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label = "dsa";
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phy-mode = "xgmii";
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link = <&switch0port10>;
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};
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};
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};
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};
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mdio_mux_4: mdio@4 {
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reg = <4>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch2: switch2@0 {
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compatible = "marvell,mv88e6190";
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reg = <0>;
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dsa,member = <0 2>;
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eeprom-length = <65536>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "internal_j9";
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};
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port@2 {
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reg = <2>;
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label = "eth_fc_1000_2";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff1>;
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};
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port@3 {
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reg = <3>;
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label = "eth_fc_1000_3";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff2>;
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};
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port@4 {
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reg = <4>;
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label = "eth_fc_1000_4";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff3>;
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};
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port@5 {
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reg = <5>;
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label = "eth_fc_1000_5";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff4>;
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};
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port@6 {
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reg = <6>;
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label = "eth_fc_1000_6";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff5>;
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};
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port@7 {
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reg = <7>;
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label = "eth_fc_1000_7";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff6>;
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};
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port@9 {
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reg = <9>;
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label = "eth_fc_1000_1";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff0>;
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};
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switch2port10: port@10 {
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reg = <10>;
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label = "dsa";
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phy-mode = "2500base-x";
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link = <&switch3port9
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&switch1port9
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&switch0port10>;
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};
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};
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};
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};
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mdio_mux_8: mdio@8 {
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reg = <8>;
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#address-cells = <1>;
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#size-cells = <0>;
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switch3: switch3@0 {
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compatible = "marvell,mv88e6190";
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reg = <0>;
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dsa,member = <0 3>;
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eeprom-length = <65536>;
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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port@1 {
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reg = <1>;
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label = "internal_j8";
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};
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port@2 {
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reg = <2>;
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label = "eth_fc_1000_8";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff7>;
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};
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port@3 {
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reg = <3>;
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label = "eth_fc_1000_9";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff8>;
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};
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port@4 {
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reg = <4>;
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label = "eth_fc_1000_10";
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phy-mode = "sgmii";
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managed = "in-band-status";
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sfp = <&sff9>;
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};
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switch3port9: port@9 {
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reg = <9>;
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label = "dsa";
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phy-mode = "2500base-x";
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link = <&switch2port10>;
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};
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switch3port10: port@10 {
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reg = <10>;
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label = "dsa";
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phy-mode = "xgmii";
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link = <&switch1port9
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&switch0port10>;
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};
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};
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};
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};
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};
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sff0: sff0 {
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compatible = "sff,sff";
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i2c-bus = <&sff0_i2c>;
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los-gpios = <&gpio9 0 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 0 GPIO_ACTIVE_HIGH>;
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};
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sff1: sff1 {
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compatible = "sff,sff";
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i2c-bus = <&sff1_i2c>;
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los-gpios = <&gpio9 1 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 1 GPIO_ACTIVE_HIGH>;
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};
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sff2: sff2 {
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compatible = "sff,sff";
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i2c-bus = <&sff2_i2c>;
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los-gpios = <&gpio9 2 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 2 GPIO_ACTIVE_HIGH>;
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};
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sff3: sff3 {
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compatible = "sff,sff";
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i2c-bus = <&sff3_i2c>;
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los-gpios = <&gpio9 3 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 3 GPIO_ACTIVE_HIGH>;
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};
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sff4: sff4 {
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compatible = "sff,sff";
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i2c-bus = <&sff4_i2c>;
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los-gpios = <&gpio9 4 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 4 GPIO_ACTIVE_HIGH>;
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};
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sff5: sff5 {
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compatible = "sff,sff";
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i2c-bus = <&sff5_i2c>;
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los-gpios = <&gpio9 5 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 5 GPIO_ACTIVE_HIGH>;
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};
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sff6: sff6 {
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compatible = "sff,sff";
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i2c-bus = <&sff6_i2c>;
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los-gpios = <&gpio9 6 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 6 GPIO_ACTIVE_HIGH>;
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};
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sff7: sff7 {
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compatible = "sff,sff";
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i2c-bus = <&sff7_i2c>;
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los-gpios = <&gpio9 7 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 7 GPIO_ACTIVE_HIGH>;
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};
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sff8: sff8 {
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compatible = "sff,sff";
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i2c-bus = <&sff8_i2c>;
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los-gpios = <&gpio9 8 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 8 GPIO_ACTIVE_HIGH>;
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};
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sff9: sff9 {
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compatible = "sff,sff";
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i2c-bus = <&sff9_i2c>;
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los-gpios = <&gpio9 9 GPIO_ACTIVE_HIGH>;
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tx-disable-gpios = <&gpio7 9 GPIO_ACTIVE_HIGH>;
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};
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reg_vcc_3v3_mcu: regulator-vcc-3v3-mcu {
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compatible = "regulator-fixed";
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regulator-name = "vcc_3v3_mcu";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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};
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};
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&dspi0 {
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pinctrl-0 = <&pinctrl_dspi0>;
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pinctrl-names = "default";
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bus-num = <0>;
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status = "okay";
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adc@5 {
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compatible = "holt,hi8435";
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reg = <5>;
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gpios = <&gpio5 3 GPIO_ACTIVE_HIGH>;
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spi-max-frequency = <1000000>;
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};
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};
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&dspi1 {
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bus-num = <1>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_dspi1>;
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status = "okay";
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spi-flash@0 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <50000000>;
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partition@0 {
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label = "m25p128-0";
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reg = <0x0 0x01000000>;
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};
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};
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spi-flash@1 {
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#address-cells = <1>;
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#size-cells = <1>;
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compatible = "jedec,spi-nor";
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reg = <1>;
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spi-max-frequency = <50000000>;
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partition@0 {
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label = "m25p128-1";
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reg = <0x0 0x01000000>;
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};
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};
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};
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&adc0 {
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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&adc1 {
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vref-supply = <®_vcc_3v3_mcu>;
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status = "okay";
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};
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&edma0 {
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status = "okay";
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};
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&edma1 {
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status = "okay";
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};
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&esdhc0 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc0>;
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bus-width = <8>;
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non-removable;
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no-1-8-v;
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no-sd;
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no-sdio;
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keep-power-in-suspend;
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status = "okay";
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};
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&esdhc1 {
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_esdhc1>;
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bus-width = <4>;
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no-sdio;
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status = "okay";
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};
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&fec1 {
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phy-mode = "rmii";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_fec1>;
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status = "okay";
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fixed-link {
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speed = <100>;
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full-duplex;
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};
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mdio1: mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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};
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};
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&i2c0 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c0>;
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status = "okay";
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gpio5: io-expander@20 {
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compatible = "nxp,pca9554";
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reg = <0x20>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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gpio6: io-expander@22 {
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compatible = "nxp,pca9554";
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reg = <0x22>;
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gpio-controller;
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#gpio-cells = <2>;
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};
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lm75@48 {
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compatible = "national,lm75";
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reg = <0x48>;
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};
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eeprom@50 {
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compatible = "atmel,24c04";
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reg = <0x50>;
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};
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eeprom@52 {
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compatible = "atmel,24c04";
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reg = <0x52>;
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};
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ds1682@6b {
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compatible = "dallas,ds1682";
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reg = <0x6b>;
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};
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};
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&i2c1 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c1>;
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status = "okay";
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adt7411@4a {
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compatible = "adi,adt7411";
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reg = <0x4a>;
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};
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};
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&i2c2 {
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clock-frequency = <100000>;
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_i2c2>;
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status = "okay";
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gpio9: sx1503q@20 {
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compatible = "semtech,sx1503q";
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pinctrl-names = "default";
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pinctrl-0 = <&pinctrl_sx1503_20>;
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#gpio-cells = <2>;
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reg = <0x20>;
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gpio-controller;
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};
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lm75@4e {
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compatible = "national,lm75";
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reg = <0x4e>;
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};
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|
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lm75@4f {
|
|
compatible = "national,lm75";
|
|
reg = <0x4f>;
|
|
};
|
|
|
|
gpio7: io-expander@23 {
|
|
compatible = "nxp,pca9555";
|
|
gpio-controller;
|
|
#gpio-cells = <2>;
|
|
reg = <0x23>;
|
|
};
|
|
|
|
adt7411@4a {
|
|
compatible = "adi,adt7411";
|
|
reg = <0x4a>;
|
|
};
|
|
|
|
at24c08@54 {
|
|
compatible = "atmel,24c08";
|
|
reg = <0x54>;
|
|
};
|
|
|
|
tca9548@70 {
|
|
compatible = "nxp,pca9548";
|
|
pinctrl-names = "default";
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <0x70>;
|
|
|
|
sff0_i2c: i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
};
|
|
|
|
sff1_i2c: i2c@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
};
|
|
|
|
sff2_i2c: i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
};
|
|
|
|
sff3_i2c: i2c@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
};
|
|
|
|
sff4_i2c: i2c@5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <5>;
|
|
};
|
|
};
|
|
|
|
tca9548@71 {
|
|
compatible = "nxp,pca9548";
|
|
pinctrl-names = "default";
|
|
reg = <0x71>;
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
|
|
sff5_i2c: i2c@1 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <1>;
|
|
};
|
|
|
|
sff6_i2c: i2c@2 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <2>;
|
|
};
|
|
|
|
sff7_i2c: i2c@3 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <3>;
|
|
};
|
|
|
|
sff8_i2c: i2c@4 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <4>;
|
|
};
|
|
|
|
sff9_i2c: i2c@5 {
|
|
#address-cells = <1>;
|
|
#size-cells = <0>;
|
|
reg = <5>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&snvsrtc {
|
|
status = "disabled";
|
|
};
|
|
|
|
&uart0 {
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart0>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart1 {
|
|
linux,rs485-enabled-at-boot-time;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart1>;
|
|
rs485-rts-delay = <0 200>;
|
|
status = "okay";
|
|
};
|
|
|
|
&uart2 {
|
|
linux,rs485-enabled-at-boot-time;
|
|
pinctrl-names = "default";
|
|
pinctrl-0 = <&pinctrl_uart2>;
|
|
rs485-rts-delay = <0 200>;
|
|
status = "okay";
|
|
};
|
|
|
|
&iomuxc {
|
|
pinctrl_dspi0: dspi0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB19__DSPI0_CS0 0x1182
|
|
VF610_PAD_PTB18__DSPI0_CS1 0x1182
|
|
VF610_PAD_PTB13__DSPI0_CS4 0x1182
|
|
VF610_PAD_PTB12__DSPI0_CS5 0x1182
|
|
VF610_PAD_PTB20__DSPI0_SIN 0x1181
|
|
VF610_PAD_PTB21__DSPI0_SOUT 0x1182
|
|
VF610_PAD_PTB22__DSPI0_SCK 0x1182
|
|
>;
|
|
};
|
|
|
|
pinctrl_dspi1: dspi1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD5__DSPI1_CS0 0x1182
|
|
VF610_PAD_PTD4__DSPI1_CS1 0x1182
|
|
VF610_PAD_PTC6__DSPI1_SIN 0x1181
|
|
VF610_PAD_PTC7__DSPI1_SOUT 0x1182
|
|
VF610_PAD_PTC8__DSPI1_SCK 0x1182
|
|
>;
|
|
};
|
|
|
|
pinctrl_dspi2: dspi2gpio {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD30__GPIO_64 0x33e2
|
|
VF610_PAD_PTD29__GPIO_65 0x33e1
|
|
VF610_PAD_PTD28__GPIO_66 0x33e2
|
|
VF610_PAD_PTD27__GPIO_67 0x33e2
|
|
VF610_PAD_PTD26__GPIO_68 0x31c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_esdhc0: esdhc0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTC0__ESDHC0_CLK 0x31ef
|
|
VF610_PAD_PTC1__ESDHC0_CMD 0x31ef
|
|
VF610_PAD_PTC2__ESDHC0_DAT0 0x31ef
|
|
VF610_PAD_PTC3__ESDHC0_DAT1 0x31ef
|
|
VF610_PAD_PTC4__ESDHC0_DAT2 0x31ef
|
|
VF610_PAD_PTC5__ESDHC0_DAT3 0x31ef
|
|
VF610_PAD_PTD23__ESDHC0_DAT4 0x31ef
|
|
VF610_PAD_PTD22__ESDHC0_DAT5 0x31ef
|
|
VF610_PAD_PTD21__ESDHC0_DAT6 0x31ef
|
|
VF610_PAD_PTD20__ESDHC0_DAT7 0x31ef
|
|
>;
|
|
};
|
|
|
|
pinctrl_esdhc1: esdhc1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA24__ESDHC1_CLK 0x31ef
|
|
VF610_PAD_PTA25__ESDHC1_CMD 0x31ef
|
|
VF610_PAD_PTA26__ESDHC1_DAT0 0x31ef
|
|
VF610_PAD_PTA27__ESDHC1_DAT1 0x31ef
|
|
VF610_PAD_PTA28__ESDHC1_DATA2 0x31ef
|
|
VF610_PAD_PTA29__ESDHC1_DAT3 0x31ef
|
|
>;
|
|
};
|
|
|
|
pinctrl_fec1: fec1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA6__RMII_CLKIN 0x30d1
|
|
VF610_PAD_PTC9__ENET_RMII1_MDC 0x30d2
|
|
VF610_PAD_PTC10__ENET_RMII1_MDIO 0x30d3
|
|
VF610_PAD_PTC11__ENET_RMII1_CRS 0x30d1
|
|
VF610_PAD_PTC12__ENET_RMII1_RXD1 0x30d1
|
|
VF610_PAD_PTC13__ENET_RMII1_RXD0 0x30d1
|
|
VF610_PAD_PTC14__ENET_RMII1_RXER 0x30d1
|
|
VF610_PAD_PTC15__ENET_RMII1_TXD1 0x30d2
|
|
VF610_PAD_PTC16__ENET_RMII1_TXD0 0x30d2
|
|
VF610_PAD_PTC17__ENET_RMII1_TXEN 0x30d2
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c0: i2c0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB14__I2C0_SCL 0x37ff
|
|
VF610_PAD_PTB15__I2C0_SDA 0x37ff
|
|
>;
|
|
};
|
|
pinctrl_i2c1: i2c1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB16__I2C1_SCL 0x37ff
|
|
VF610_PAD_PTB17__I2C1_SDA 0x37ff
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c2: i2c2grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA22__I2C2_SCL 0x37ff
|
|
VF610_PAD_PTA23__I2C2_SDA 0x37ff
|
|
>;
|
|
};
|
|
|
|
pinctrl_i2c3: i2c3grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTA30__I2C3_SCL 0x37ff
|
|
VF610_PAD_PTA31__I2C3_SDA 0x37ff
|
|
>;
|
|
};
|
|
|
|
pinctrl_leds_debug: pinctrl-leds-debug {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB26__GPIO_96 0x31c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_mdio_mux: pinctrl-mdio-mux {
|
|
fsl,pins = <
|
|
VF610_PAD_PTE27__GPIO_132 0x31c2
|
|
VF610_PAD_PTE28__GPIO_133 0x31c2
|
|
VF610_PAD_PTE21__GPIO_126 0x31c2
|
|
VF610_PAD_PTE22__GPIO_127 0x31c2
|
|
>;
|
|
};
|
|
|
|
pinctrl_qspi0: qspi0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD7__QSPI0_B_QSCK 0x31c3
|
|
VF610_PAD_PTD8__QSPI0_B_CS0 0x31ff
|
|
VF610_PAD_PTD9__QSPI0_B_DATA3 0x31c3
|
|
VF610_PAD_PTD10__QSPI0_B_DATA2 0x31c3
|
|
VF610_PAD_PTD11__QSPI0_B_DATA1 0x31c3
|
|
VF610_PAD_PTD12__QSPI0_B_DATA0 0x31c3
|
|
>;
|
|
};
|
|
|
|
pinctrl_sx1503_20: pinctrl-sx1503-20 {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD31__GPIO_63 0x219d
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart0: uart0grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB10__UART0_TX 0x21a2
|
|
VF610_PAD_PTB11__UART0_RX 0x21a1
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart1: uart1grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTB23__UART1_TX 0x21a2
|
|
VF610_PAD_PTB24__UART1_RX 0x21a1
|
|
VF610_PAD_PTB25__UART1_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
|
|
>;
|
|
};
|
|
|
|
pinctrl_uart2: uart2grp {
|
|
fsl,pins = <
|
|
VF610_PAD_PTD0__UART2_TX 0x21a2
|
|
VF610_PAD_PTD1__UART2_RX 0x21a1
|
|
VF610_PAD_PTD2__UART2_RTS 0x21a2 /* Used as DE signal for the RS-485 transceiver */
|
|
>;
|
|
};
|
|
};
|