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![Ville Syrjälä](/assets/img/avatar_default.png)
drm_vblank_count() returns the software counter. We should not pretend it's the hw counter since we use the hw counter to figuere out what the software counter value should be. So instead provide a new function drm_vblank_no_hw_counter() for drivers that don't have a real hw counter. The new function simply returns 0, which is about the only thing it can do. Cc: Vincent Abriou <vincent.abriou@st.com> Cc: Thierry Reding <treding@nvidia.com> Signed-off-by: Ville Syrjälä <ville.syrjala@linux.intel.com> Reviewed-by: Vincent Abriou <vincent.abriou@st.com> [danvet: s/int pipe/unsigned int pipe/ to follow Thierry's interface change.] Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
833 lines
19 KiB
C
833 lines
19 KiB
C
/*
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* Copyright (C) 2014 Traphandler
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* Copyright (C) 2014 Free Electrons
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* Copyright (C) 2014 Atmel
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*
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* Author: Jean-Jacques Hiblot <jjhiblot@traphandler.com>
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* Author: Boris BREZILLON <boris.brezillon@free-electrons.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License version 2 as published by
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* the Free Software Foundation.
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*
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* This program is distributed in the hope that it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program. If not, see <http://www.gnu.org/licenses/>.
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*/
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#include <linux/clk.h>
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#include <linux/irq.h>
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#include <linux/irqchip.h>
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#include <linux/module.h>
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#include <linux/pm_runtime.h>
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#include "atmel_hlcdc_dc.h"
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#define ATMEL_HLCDC_LAYER_IRQS_OFFSET 8
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static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9n12_layers[] = {
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{
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.name = "base",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x40,
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.id = 0,
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.type = ATMEL_HLCDC_BASE_LAYER,
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.nconfigs = 5,
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.layout = {
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.xstride = { 2 },
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.default_color = 3,
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.general_config = 4,
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},
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},
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};
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static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9n12 = {
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.min_width = 0,
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.min_height = 0,
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.max_width = 1280,
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.max_height = 860,
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.nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9n12_layers),
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.layers = atmel_hlcdc_at91sam9n12_layers,
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};
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static const struct atmel_hlcdc_layer_desc atmel_hlcdc_at91sam9x5_layers[] = {
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{
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.name = "base",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x40,
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.id = 0,
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.type = ATMEL_HLCDC_BASE_LAYER,
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.nconfigs = 5,
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.layout = {
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.xstride = { 2 },
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.default_color = 3,
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.general_config = 4,
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.disc_pos = 5,
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.disc_size = 6,
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},
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},
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{
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.name = "overlay1",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x100,
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.id = 1,
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.type = ATMEL_HLCDC_OVERLAY_LAYER,
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.nconfigs = 10,
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.layout = {
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.pos = 2,
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.size = 3,
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.xstride = { 4 },
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.pstride = { 5 },
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.default_color = 6,
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.chroma_key = 7,
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.chroma_key_mask = 8,
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.general_config = 9,
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},
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},
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{
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.name = "high-end-overlay",
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.formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
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.regs_offset = 0x280,
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.id = 2,
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.type = ATMEL_HLCDC_OVERLAY_LAYER,
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.nconfigs = 17,
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.layout = {
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.pos = 2,
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.size = 3,
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.memsize = 4,
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.xstride = { 5, 7 },
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.pstride = { 6, 8 },
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.default_color = 9,
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.chroma_key = 10,
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.chroma_key_mask = 11,
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.general_config = 12,
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.csc = 14,
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},
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},
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{
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.name = "cursor",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x340,
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.id = 3,
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.type = ATMEL_HLCDC_CURSOR_LAYER,
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.nconfigs = 10,
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.max_width = 128,
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.max_height = 128,
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.layout = {
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.pos = 2,
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.size = 3,
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.xstride = { 4 },
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.default_color = 6,
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.chroma_key = 7,
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.chroma_key_mask = 8,
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.general_config = 9,
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},
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},
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};
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static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_at91sam9x5 = {
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.min_width = 0,
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.min_height = 0,
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.max_width = 800,
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.max_height = 600,
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.nlayers = ARRAY_SIZE(atmel_hlcdc_at91sam9x5_layers),
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.layers = atmel_hlcdc_at91sam9x5_layers,
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};
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static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d3_layers[] = {
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{
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.name = "base",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x40,
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.id = 0,
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.type = ATMEL_HLCDC_BASE_LAYER,
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.nconfigs = 7,
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.layout = {
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.xstride = { 2 },
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.default_color = 3,
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.general_config = 4,
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.disc_pos = 5,
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.disc_size = 6,
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},
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},
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{
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.name = "overlay1",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x140,
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.id = 1,
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.type = ATMEL_HLCDC_OVERLAY_LAYER,
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.nconfigs = 10,
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.layout = {
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.pos = 2,
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.size = 3,
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.xstride = { 4 },
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.pstride = { 5 },
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.default_color = 6,
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.chroma_key = 7,
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.chroma_key_mask = 8,
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.general_config = 9,
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},
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},
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{
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.name = "overlay2",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x240,
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.id = 2,
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.type = ATMEL_HLCDC_OVERLAY_LAYER,
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.nconfigs = 10,
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.layout = {
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.pos = 2,
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.size = 3,
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.xstride = { 4 },
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.pstride = { 5 },
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.default_color = 6,
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.chroma_key = 7,
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.chroma_key_mask = 8,
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.general_config = 9,
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},
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},
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{
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.name = "high-end-overlay",
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.formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
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.regs_offset = 0x340,
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.id = 3,
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.type = ATMEL_HLCDC_OVERLAY_LAYER,
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.nconfigs = 42,
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.layout = {
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.pos = 2,
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.size = 3,
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.memsize = 4,
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.xstride = { 5, 7 },
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.pstride = { 6, 8 },
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.default_color = 9,
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.chroma_key = 10,
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.chroma_key_mask = 11,
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.general_config = 12,
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.csc = 14,
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},
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},
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{
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.name = "cursor",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x440,
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.id = 4,
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.type = ATMEL_HLCDC_CURSOR_LAYER,
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.nconfigs = 10,
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.max_width = 128,
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.max_height = 128,
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.layout = {
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.pos = 2,
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.size = 3,
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.xstride = { 4 },
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.pstride = { 5 },
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.default_color = 6,
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.chroma_key = 7,
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.chroma_key_mask = 8,
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.general_config = 9,
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},
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},
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};
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static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d3 = {
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.min_width = 0,
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.min_height = 0,
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.max_width = 2048,
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.max_height = 2048,
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.nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d3_layers),
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.layers = atmel_hlcdc_sama5d3_layers,
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};
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static const struct atmel_hlcdc_layer_desc atmel_hlcdc_sama5d4_layers[] = {
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{
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.name = "base",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x40,
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.id = 0,
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.type = ATMEL_HLCDC_BASE_LAYER,
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.nconfigs = 7,
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.layout = {
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.xstride = { 2 },
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.default_color = 3,
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.general_config = 4,
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.disc_pos = 5,
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.disc_size = 6,
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},
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},
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{
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.name = "overlay1",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x140,
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.id = 1,
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.type = ATMEL_HLCDC_OVERLAY_LAYER,
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.nconfigs = 10,
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.layout = {
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.pos = 2,
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.size = 3,
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.xstride = { 4 },
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.pstride = { 5 },
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.default_color = 6,
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.chroma_key = 7,
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.chroma_key_mask = 8,
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.general_config = 9,
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},
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},
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{
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.name = "overlay2",
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.formats = &atmel_hlcdc_plane_rgb_formats,
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.regs_offset = 0x240,
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.id = 2,
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.type = ATMEL_HLCDC_OVERLAY_LAYER,
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.nconfigs = 10,
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.layout = {
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.pos = 2,
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.size = 3,
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.xstride = { 4 },
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.pstride = { 5 },
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.default_color = 6,
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.chroma_key = 7,
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.chroma_key_mask = 8,
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.general_config = 9,
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},
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},
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{
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.name = "high-end-overlay",
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.formats = &atmel_hlcdc_plane_rgb_and_yuv_formats,
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.regs_offset = 0x340,
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.id = 3,
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.type = ATMEL_HLCDC_OVERLAY_LAYER,
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.nconfigs = 42,
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.layout = {
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.pos = 2,
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.size = 3,
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.memsize = 4,
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.xstride = { 5, 7 },
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.pstride = { 6, 8 },
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.default_color = 9,
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.chroma_key = 10,
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.chroma_key_mask = 11,
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.general_config = 12,
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.csc = 14,
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},
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},
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};
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static const struct atmel_hlcdc_dc_desc atmel_hlcdc_dc_sama5d4 = {
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.min_width = 0,
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.min_height = 0,
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.max_width = 2048,
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.max_height = 2048,
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.nlayers = ARRAY_SIZE(atmel_hlcdc_sama5d4_layers),
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.layers = atmel_hlcdc_sama5d4_layers,
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};
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static const struct of_device_id atmel_hlcdc_of_match[] = {
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{
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.compatible = "atmel,at91sam9n12-hlcdc",
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.data = &atmel_hlcdc_dc_at91sam9n12,
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},
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{
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.compatible = "atmel,at91sam9x5-hlcdc",
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.data = &atmel_hlcdc_dc_at91sam9x5,
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},
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{
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.compatible = "atmel,sama5d3-hlcdc",
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.data = &atmel_hlcdc_dc_sama5d3,
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},
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{
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.compatible = "atmel,sama5d4-hlcdc",
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.data = &atmel_hlcdc_dc_sama5d4,
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},
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{ /* sentinel */ },
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};
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int atmel_hlcdc_dc_mode_valid(struct atmel_hlcdc_dc *dc,
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struct drm_display_mode *mode)
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{
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int vfront_porch = mode->vsync_start - mode->vdisplay;
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int vback_porch = mode->vtotal - mode->vsync_end;
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int vsync_len = mode->vsync_end - mode->vsync_start;
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int hfront_porch = mode->hsync_start - mode->hdisplay;
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int hback_porch = mode->htotal - mode->hsync_end;
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int hsync_len = mode->hsync_end - mode->hsync_start;
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if (hsync_len > 0x40 || hsync_len < 1)
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return MODE_HSYNC;
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if (vsync_len > 0x40 || vsync_len < 1)
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return MODE_VSYNC;
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if (hfront_porch > 0x200 || hfront_porch < 1 ||
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hback_porch > 0x200 || hback_porch < 1 ||
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mode->hdisplay < 1)
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return MODE_H_ILLEGAL;
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if (vfront_porch > 0x40 || vfront_porch < 1 ||
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vback_porch > 0x40 || vback_porch < 0 ||
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mode->vdisplay < 1)
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return MODE_V_ILLEGAL;
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return MODE_OK;
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}
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static irqreturn_t atmel_hlcdc_dc_irq_handler(int irq, void *data)
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{
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struct drm_device *dev = data;
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struct atmel_hlcdc_dc *dc = dev->dev_private;
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unsigned long status;
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unsigned int imr, isr;
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int i;
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regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_IMR, &imr);
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regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
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status = imr & isr;
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if (!status)
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return IRQ_NONE;
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if (status & ATMEL_HLCDC_SOF)
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atmel_hlcdc_crtc_irq(dc->crtc);
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for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
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struct atmel_hlcdc_layer *layer = dc->layers[i];
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if (!(ATMEL_HLCDC_LAYER_STATUS(i) & status) || !layer)
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continue;
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atmel_hlcdc_layer_irq(layer);
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}
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return IRQ_HANDLED;
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}
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static struct drm_framebuffer *atmel_hlcdc_fb_create(struct drm_device *dev,
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struct drm_file *file_priv, struct drm_mode_fb_cmd2 *mode_cmd)
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{
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return drm_fb_cma_create(dev, file_priv, mode_cmd);
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}
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static void atmel_hlcdc_fb_output_poll_changed(struct drm_device *dev)
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{
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struct atmel_hlcdc_dc *dc = dev->dev_private;
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if (dc->fbdev) {
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drm_fbdev_cma_hotplug_event(dc->fbdev);
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} else {
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dc->fbdev = drm_fbdev_cma_init(dev, 24,
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dev->mode_config.num_crtc,
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dev->mode_config.num_connector);
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if (IS_ERR(dc->fbdev))
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dc->fbdev = NULL;
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}
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}
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static const struct drm_mode_config_funcs mode_config_funcs = {
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.fb_create = atmel_hlcdc_fb_create,
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.output_poll_changed = atmel_hlcdc_fb_output_poll_changed,
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.atomic_check = drm_atomic_helper_check,
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.atomic_commit = drm_atomic_helper_commit,
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};
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static int atmel_hlcdc_dc_modeset_init(struct drm_device *dev)
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{
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struct atmel_hlcdc_dc *dc = dev->dev_private;
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struct atmel_hlcdc_planes *planes;
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int ret;
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int i;
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drm_mode_config_init(dev);
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ret = atmel_hlcdc_create_outputs(dev);
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if (ret) {
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dev_err(dev->dev, "failed to create panel: %d\n", ret);
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return ret;
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}
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planes = atmel_hlcdc_create_planes(dev);
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if (IS_ERR(planes)) {
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dev_err(dev->dev, "failed to create planes\n");
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return PTR_ERR(planes);
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}
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dc->planes = planes;
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dc->layers[planes->primary->layer.desc->id] =
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&planes->primary->layer;
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if (planes->cursor)
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dc->layers[planes->cursor->layer.desc->id] =
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&planes->cursor->layer;
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for (i = 0; i < planes->noverlays; i++)
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dc->layers[planes->overlays[i]->layer.desc->id] =
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&planes->overlays[i]->layer;
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ret = atmel_hlcdc_crtc_create(dev);
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if (ret) {
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dev_err(dev->dev, "failed to create crtc\n");
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return ret;
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}
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dev->mode_config.min_width = dc->desc->min_width;
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dev->mode_config.min_height = dc->desc->min_height;
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dev->mode_config.max_width = dc->desc->max_width;
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dev->mode_config.max_height = dc->desc->max_height;
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dev->mode_config.funcs = &mode_config_funcs;
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return 0;
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}
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static int atmel_hlcdc_dc_load(struct drm_device *dev)
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{
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struct platform_device *pdev = to_platform_device(dev->dev);
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const struct of_device_id *match;
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struct atmel_hlcdc_dc *dc;
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int ret;
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|
|
match = of_match_node(atmel_hlcdc_of_match, dev->dev->parent->of_node);
|
|
if (!match) {
|
|
dev_err(&pdev->dev, "invalid compatible string\n");
|
|
return -ENODEV;
|
|
}
|
|
|
|
if (!match->data) {
|
|
dev_err(&pdev->dev, "invalid hlcdc description\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
dc = devm_kzalloc(dev->dev, sizeof(*dc), GFP_KERNEL);
|
|
if (!dc)
|
|
return -ENOMEM;
|
|
|
|
dc->wq = alloc_ordered_workqueue("atmel-hlcdc-dc", 0);
|
|
if (!dc->wq)
|
|
return -ENOMEM;
|
|
|
|
dc->desc = match->data;
|
|
dc->hlcdc = dev_get_drvdata(dev->dev->parent);
|
|
dev->dev_private = dc;
|
|
|
|
ret = clk_prepare_enable(dc->hlcdc->periph_clk);
|
|
if (ret) {
|
|
dev_err(dev->dev, "failed to enable periph_clk\n");
|
|
goto err_destroy_wq;
|
|
}
|
|
|
|
pm_runtime_enable(dev->dev);
|
|
|
|
ret = drm_vblank_init(dev, 1);
|
|
if (ret < 0) {
|
|
dev_err(dev->dev, "failed to initialize vblank\n");
|
|
goto err_periph_clk_disable;
|
|
}
|
|
|
|
ret = atmel_hlcdc_dc_modeset_init(dev);
|
|
if (ret < 0) {
|
|
dev_err(dev->dev, "failed to initialize mode setting\n");
|
|
goto err_periph_clk_disable;
|
|
}
|
|
|
|
drm_mode_config_reset(dev);
|
|
|
|
pm_runtime_get_sync(dev->dev);
|
|
ret = drm_irq_install(dev, dc->hlcdc->irq);
|
|
pm_runtime_put_sync(dev->dev);
|
|
if (ret < 0) {
|
|
dev_err(dev->dev, "failed to install IRQ handler\n");
|
|
goto err_periph_clk_disable;
|
|
}
|
|
|
|
platform_set_drvdata(pdev, dev);
|
|
|
|
drm_kms_helper_poll_init(dev);
|
|
|
|
/* force connectors detection */
|
|
drm_helper_hpd_irq_event(dev);
|
|
|
|
return 0;
|
|
|
|
err_periph_clk_disable:
|
|
pm_runtime_disable(dev->dev);
|
|
clk_disable_unprepare(dc->hlcdc->periph_clk);
|
|
|
|
err_destroy_wq:
|
|
destroy_workqueue(dc->wq);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void atmel_hlcdc_dc_unload(struct drm_device *dev)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
|
|
if (dc->fbdev)
|
|
drm_fbdev_cma_fini(dc->fbdev);
|
|
flush_workqueue(dc->wq);
|
|
drm_kms_helper_poll_fini(dev);
|
|
drm_mode_config_cleanup(dev);
|
|
drm_vblank_cleanup(dev);
|
|
|
|
pm_runtime_get_sync(dev->dev);
|
|
drm_irq_uninstall(dev);
|
|
pm_runtime_put_sync(dev->dev);
|
|
|
|
dev->dev_private = NULL;
|
|
|
|
pm_runtime_disable(dev->dev);
|
|
clk_disable_unprepare(dc->hlcdc->periph_clk);
|
|
destroy_workqueue(dc->wq);
|
|
}
|
|
|
|
static int atmel_hlcdc_dc_connector_plug_all(struct drm_device *dev)
|
|
{
|
|
struct drm_connector *connector, *failed;
|
|
int ret;
|
|
|
|
mutex_lock(&dev->mode_config.mutex);
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
ret = drm_connector_register(connector);
|
|
if (ret) {
|
|
failed = connector;
|
|
goto err;
|
|
}
|
|
}
|
|
mutex_unlock(&dev->mode_config.mutex);
|
|
return 0;
|
|
|
|
err:
|
|
list_for_each_entry(connector, &dev->mode_config.connector_list, head) {
|
|
if (failed == connector)
|
|
break;
|
|
|
|
drm_connector_unregister(connector);
|
|
}
|
|
mutex_unlock(&dev->mode_config.mutex);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static void atmel_hlcdc_dc_connector_unplug_all(struct drm_device *dev)
|
|
{
|
|
mutex_lock(&dev->mode_config.mutex);
|
|
drm_connector_unplug_all(dev);
|
|
mutex_unlock(&dev->mode_config.mutex);
|
|
}
|
|
|
|
static void atmel_hlcdc_dc_preclose(struct drm_device *dev,
|
|
struct drm_file *file)
|
|
{
|
|
struct drm_crtc *crtc;
|
|
|
|
list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
|
|
atmel_hlcdc_crtc_cancel_page_flip(crtc, file);
|
|
}
|
|
|
|
static void atmel_hlcdc_dc_lastclose(struct drm_device *dev)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
|
|
drm_fbdev_cma_restore_mode(dc->fbdev);
|
|
}
|
|
|
|
static int atmel_hlcdc_dc_irq_postinstall(struct drm_device *dev)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
unsigned int cfg = 0;
|
|
int i;
|
|
|
|
/* Enable interrupts on activated layers */
|
|
for (i = 0; i < ATMEL_HLCDC_MAX_LAYERS; i++) {
|
|
if (dc->layers[i])
|
|
cfg |= ATMEL_HLCDC_LAYER_STATUS(i);
|
|
}
|
|
|
|
regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, cfg);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_hlcdc_dc_irq_uninstall(struct drm_device *dev)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
unsigned int isr;
|
|
|
|
regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, 0xffffffff);
|
|
regmap_read(dc->hlcdc->regmap, ATMEL_HLCDC_ISR, &isr);
|
|
}
|
|
|
|
static int atmel_hlcdc_dc_enable_vblank(struct drm_device *dev,
|
|
unsigned int pipe)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
|
|
/* Enable SOF (Start Of Frame) interrupt for vblank counting */
|
|
regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IER, ATMEL_HLCDC_SOF);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void atmel_hlcdc_dc_disable_vblank(struct drm_device *dev,
|
|
unsigned int pipe)
|
|
{
|
|
struct atmel_hlcdc_dc *dc = dev->dev_private;
|
|
|
|
regmap_write(dc->hlcdc->regmap, ATMEL_HLCDC_IDR, ATMEL_HLCDC_SOF);
|
|
}
|
|
|
|
static const struct file_operations fops = {
|
|
.owner = THIS_MODULE,
|
|
.open = drm_open,
|
|
.release = drm_release,
|
|
.unlocked_ioctl = drm_ioctl,
|
|
#ifdef CONFIG_COMPAT
|
|
.compat_ioctl = drm_compat_ioctl,
|
|
#endif
|
|
.poll = drm_poll,
|
|
.read = drm_read,
|
|
.llseek = no_llseek,
|
|
.mmap = drm_gem_cma_mmap,
|
|
};
|
|
|
|
static struct drm_driver atmel_hlcdc_dc_driver = {
|
|
.driver_features = DRIVER_HAVE_IRQ | DRIVER_GEM |
|
|
DRIVER_MODESET | DRIVER_PRIME |
|
|
DRIVER_ATOMIC,
|
|
.preclose = atmel_hlcdc_dc_preclose,
|
|
.lastclose = atmel_hlcdc_dc_lastclose,
|
|
.irq_handler = atmel_hlcdc_dc_irq_handler,
|
|
.irq_preinstall = atmel_hlcdc_dc_irq_uninstall,
|
|
.irq_postinstall = atmel_hlcdc_dc_irq_postinstall,
|
|
.irq_uninstall = atmel_hlcdc_dc_irq_uninstall,
|
|
.get_vblank_counter = drm_vblank_no_hw_counter,
|
|
.enable_vblank = atmel_hlcdc_dc_enable_vblank,
|
|
.disable_vblank = atmel_hlcdc_dc_disable_vblank,
|
|
.gem_free_object = drm_gem_cma_free_object,
|
|
.gem_vm_ops = &drm_gem_cma_vm_ops,
|
|
.prime_handle_to_fd = drm_gem_prime_handle_to_fd,
|
|
.prime_fd_to_handle = drm_gem_prime_fd_to_handle,
|
|
.gem_prime_import = drm_gem_prime_import,
|
|
.gem_prime_export = drm_gem_prime_export,
|
|
.gem_prime_get_sg_table = drm_gem_cma_prime_get_sg_table,
|
|
.gem_prime_import_sg_table = drm_gem_cma_prime_import_sg_table,
|
|
.gem_prime_vmap = drm_gem_cma_prime_vmap,
|
|
.gem_prime_vunmap = drm_gem_cma_prime_vunmap,
|
|
.gem_prime_mmap = drm_gem_cma_prime_mmap,
|
|
.dumb_create = drm_gem_cma_dumb_create,
|
|
.dumb_map_offset = drm_gem_cma_dumb_map_offset,
|
|
.dumb_destroy = drm_gem_dumb_destroy,
|
|
.fops = &fops,
|
|
.name = "atmel-hlcdc",
|
|
.desc = "Atmel HLCD Controller DRM",
|
|
.date = "20141504",
|
|
.major = 1,
|
|
.minor = 0,
|
|
};
|
|
|
|
static int atmel_hlcdc_dc_drm_probe(struct platform_device *pdev)
|
|
{
|
|
struct drm_device *ddev;
|
|
int ret;
|
|
|
|
ddev = drm_dev_alloc(&atmel_hlcdc_dc_driver, &pdev->dev);
|
|
if (!ddev)
|
|
return -ENOMEM;
|
|
|
|
ret = drm_dev_set_unique(ddev, dev_name(ddev->dev));
|
|
if (ret)
|
|
goto err_unref;
|
|
|
|
ret = atmel_hlcdc_dc_load(ddev);
|
|
if (ret)
|
|
goto err_unref;
|
|
|
|
ret = drm_dev_register(ddev, 0);
|
|
if (ret)
|
|
goto err_unload;
|
|
|
|
ret = atmel_hlcdc_dc_connector_plug_all(ddev);
|
|
if (ret)
|
|
goto err_unregister;
|
|
|
|
return 0;
|
|
|
|
err_unregister:
|
|
drm_dev_unregister(ddev);
|
|
|
|
err_unload:
|
|
atmel_hlcdc_dc_unload(ddev);
|
|
|
|
err_unref:
|
|
drm_dev_unref(ddev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int atmel_hlcdc_dc_drm_remove(struct platform_device *pdev)
|
|
{
|
|
struct drm_device *ddev = platform_get_drvdata(pdev);
|
|
|
|
atmel_hlcdc_dc_connector_unplug_all(ddev);
|
|
drm_dev_unregister(ddev);
|
|
atmel_hlcdc_dc_unload(ddev);
|
|
drm_dev_unref(ddev);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int atmel_hlcdc_dc_drm_suspend(struct device *dev)
|
|
{
|
|
struct drm_device *drm_dev = dev_get_drvdata(dev);
|
|
struct drm_crtc *crtc;
|
|
|
|
if (pm_runtime_suspended(dev))
|
|
return 0;
|
|
|
|
drm_modeset_lock_all(drm_dev);
|
|
list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
|
|
atmel_hlcdc_crtc_suspend(crtc);
|
|
drm_modeset_unlock_all(drm_dev);
|
|
return 0;
|
|
}
|
|
|
|
static int atmel_hlcdc_dc_drm_resume(struct device *dev)
|
|
{
|
|
struct drm_device *drm_dev = dev_get_drvdata(dev);
|
|
struct drm_crtc *crtc;
|
|
|
|
if (pm_runtime_suspended(dev))
|
|
return 0;
|
|
|
|
drm_modeset_lock_all(drm_dev);
|
|
list_for_each_entry(crtc, &drm_dev->mode_config.crtc_list, head)
|
|
atmel_hlcdc_crtc_resume(crtc);
|
|
drm_modeset_unlock_all(drm_dev);
|
|
return 0;
|
|
}
|
|
#endif
|
|
|
|
static SIMPLE_DEV_PM_OPS(atmel_hlcdc_dc_drm_pm_ops,
|
|
atmel_hlcdc_dc_drm_suspend, atmel_hlcdc_dc_drm_resume);
|
|
|
|
static const struct of_device_id atmel_hlcdc_dc_of_match[] = {
|
|
{ .compatible = "atmel,hlcdc-display-controller" },
|
|
{ },
|
|
};
|
|
|
|
static struct platform_driver atmel_hlcdc_dc_platform_driver = {
|
|
.probe = atmel_hlcdc_dc_drm_probe,
|
|
.remove = atmel_hlcdc_dc_drm_remove,
|
|
.driver = {
|
|
.name = "atmel-hlcdc-display-controller",
|
|
.pm = &atmel_hlcdc_dc_drm_pm_ops,
|
|
.of_match_table = atmel_hlcdc_dc_of_match,
|
|
},
|
|
};
|
|
module_platform_driver(atmel_hlcdc_dc_platform_driver);
|
|
|
|
MODULE_AUTHOR("Jean-Jacques Hiblot <jjhiblot@traphandler.com>");
|
|
MODULE_AUTHOR("Boris Brezillon <boris.brezillon@free-electrons.com>");
|
|
MODULE_DESCRIPTION("Atmel HLCDC Display Controller DRM Driver");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:atmel-hlcdc-dc");
|