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![Philipp Zabel](/assets/img/avatar_default.png)
This patch makes the fsl,data-width and fsl,data-mapping device tree properties optional if a panel is connected to the ldb output port via the of_graph bindings. The data mapping is determined from the display_info.bus_format field provided by the panel. Signed-off-by: Philipp Zabel <p.zabel@pengutronix.de>
690 lines
18 KiB
C
690 lines
18 KiB
C
/*
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* i.MX drm driver - LVDS display bridge
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*
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* Copyright (C) 2012 Sascha Hauer, Pengutronix
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version 2
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* of the License, or (at your option) any later version.
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/component.h>
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#include <drm/drmP.h>
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#include <drm/drm_fb_helper.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_panel.h>
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#include <linux/mfd/syscon.h>
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#include <linux/mfd/syscon/imx6q-iomuxc-gpr.h>
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#include <linux/of_device.h>
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#include <linux/of_graph.h>
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#include <video/of_videomode.h>
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#include <linux/regmap.h>
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#include <linux/videodev2.h>
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#include "imx-drm.h"
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#define DRIVER_NAME "imx-ldb"
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#define LDB_CH0_MODE_EN_TO_DI0 (1 << 0)
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#define LDB_CH0_MODE_EN_TO_DI1 (3 << 0)
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#define LDB_CH0_MODE_EN_MASK (3 << 0)
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#define LDB_CH1_MODE_EN_TO_DI0 (1 << 2)
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#define LDB_CH1_MODE_EN_TO_DI1 (3 << 2)
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#define LDB_CH1_MODE_EN_MASK (3 << 2)
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#define LDB_SPLIT_MODE_EN (1 << 4)
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#define LDB_DATA_WIDTH_CH0_24 (1 << 5)
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#define LDB_BIT_MAP_CH0_JEIDA (1 << 6)
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#define LDB_DATA_WIDTH_CH1_24 (1 << 7)
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#define LDB_BIT_MAP_CH1_JEIDA (1 << 8)
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#define LDB_DI0_VS_POL_ACT_LOW (1 << 9)
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#define LDB_DI1_VS_POL_ACT_LOW (1 << 10)
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#define LDB_BGREF_RMODE_INT (1 << 15)
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#define con_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, connector)
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#define enc_to_imx_ldb_ch(x) container_of(x, struct imx_ldb_channel, encoder)
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struct imx_ldb;
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struct imx_ldb_channel {
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struct imx_ldb *ldb;
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struct drm_connector connector;
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struct drm_encoder encoder;
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struct drm_panel *panel;
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struct device_node *child;
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int chno;
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void *edid;
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int edid_len;
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struct drm_display_mode mode;
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int mode_valid;
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int bus_format;
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};
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struct bus_mux {
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int reg;
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int shift;
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int mask;
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};
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struct imx_ldb {
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struct regmap *regmap;
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struct device *dev;
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struct imx_ldb_channel channel[2];
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struct clk *clk[2]; /* our own clock */
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struct clk *clk_sel[4]; /* parent of display clock */
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struct clk *clk_parent[4]; /* original parent of clk_sel */
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struct clk *clk_pll[2]; /* upstream clock we can adjust */
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u32 ldb_ctrl;
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const struct bus_mux *lvds_mux;
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};
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static enum drm_connector_status imx_ldb_connector_detect(
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struct drm_connector *connector, bool force)
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{
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return connector_status_connected;
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}
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static int imx_ldb_connector_get_modes(struct drm_connector *connector)
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{
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struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
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int num_modes = 0;
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if (imx_ldb_ch->panel && imx_ldb_ch->panel->funcs &&
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imx_ldb_ch->panel->funcs->get_modes) {
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struct drm_display_info *di = &connector->display_info;
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num_modes = imx_ldb_ch->panel->funcs->get_modes(imx_ldb_ch->panel);
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if (!imx_ldb_ch->bus_format && di->num_bus_formats)
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imx_ldb_ch->bus_format = di->bus_formats[0];
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if (num_modes > 0)
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return num_modes;
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}
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if (imx_ldb_ch->edid) {
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drm_mode_connector_update_edid_property(connector,
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imx_ldb_ch->edid);
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num_modes = drm_add_edid_modes(connector, imx_ldb_ch->edid);
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}
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if (imx_ldb_ch->mode_valid) {
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struct drm_display_mode *mode;
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mode = drm_mode_create(connector->dev);
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if (!mode)
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return -EINVAL;
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drm_mode_copy(mode, &imx_ldb_ch->mode);
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mode->type |= DRM_MODE_TYPE_DRIVER | DRM_MODE_TYPE_PREFERRED;
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drm_mode_probed_add(connector, mode);
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num_modes++;
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}
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return num_modes;
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}
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static struct drm_encoder *imx_ldb_connector_best_encoder(
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struct drm_connector *connector)
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{
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struct imx_ldb_channel *imx_ldb_ch = con_to_imx_ldb_ch(connector);
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return &imx_ldb_ch->encoder;
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}
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static void imx_ldb_encoder_dpms(struct drm_encoder *encoder, int mode)
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{
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}
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static bool imx_ldb_encoder_mode_fixup(struct drm_encoder *encoder,
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const struct drm_display_mode *mode,
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struct drm_display_mode *adjusted_mode)
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{
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return true;
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}
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static void imx_ldb_set_clock(struct imx_ldb *ldb, int mux, int chno,
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unsigned long serial_clk, unsigned long di_clk)
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{
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int ret;
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dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
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clk_get_rate(ldb->clk_pll[chno]), serial_clk);
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clk_set_rate(ldb->clk_pll[chno], serial_clk);
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dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
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clk_get_rate(ldb->clk_pll[chno]));
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dev_dbg(ldb->dev, "%s: now: %ld want: %ld\n", __func__,
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clk_get_rate(ldb->clk[chno]),
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(long int)di_clk);
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clk_set_rate(ldb->clk[chno], di_clk);
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dev_dbg(ldb->dev, "%s after: %ld\n", __func__,
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clk_get_rate(ldb->clk[chno]));
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/* set display clock mux to LDB input clock */
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ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk[chno]);
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if (ret)
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dev_err(ldb->dev,
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"unable to set di%d parent clock to ldb_di%d\n", mux,
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chno);
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}
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static void imx_ldb_encoder_prepare(struct drm_encoder *encoder)
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{
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struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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u32 bus_format;
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switch (imx_ldb_ch->bus_format) {
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default:
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dev_warn(ldb->dev,
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"could not determine data mapping, default to 18-bit \"spwg\"\n");
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/* fallthrough */
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case MEDIA_BUS_FMT_RGB666_1X7X3_SPWG:
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bus_format = MEDIA_BUS_FMT_RGB666_1X18;
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_SPWG:
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bus_format = MEDIA_BUS_FMT_RGB888_1X24;
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if (imx_ldb_ch->chno == 0 || dual)
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ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24;
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if (imx_ldb_ch->chno == 1 || dual)
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ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24;
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break;
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case MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA:
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bus_format = MEDIA_BUS_FMT_RGB888_1X24;
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if (imx_ldb_ch->chno == 0 || dual)
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ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH0_24 |
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LDB_BIT_MAP_CH0_JEIDA;
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if (imx_ldb_ch->chno == 1 || dual)
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ldb->ldb_ctrl |= LDB_DATA_WIDTH_CH1_24 |
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LDB_BIT_MAP_CH1_JEIDA;
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break;
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}
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imx_drm_set_bus_format(encoder, bus_format);
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}
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static void imx_ldb_encoder_commit(struct drm_encoder *encoder)
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{
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struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
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drm_panel_prepare(imx_ldb_ch->panel);
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if (dual) {
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clk_prepare_enable(ldb->clk[0]);
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clk_prepare_enable(ldb->clk[1]);
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}
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if (imx_ldb_ch == &ldb->channel[0] || dual) {
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ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
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if (mux == 0 || ldb->lvds_mux)
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ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI0;
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else if (mux == 1)
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ldb->ldb_ctrl |= LDB_CH0_MODE_EN_TO_DI1;
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}
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if (imx_ldb_ch == &ldb->channel[1] || dual) {
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ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
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if (mux == 1 || ldb->lvds_mux)
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ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI1;
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else if (mux == 0)
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ldb->ldb_ctrl |= LDB_CH1_MODE_EN_TO_DI0;
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}
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if (ldb->lvds_mux) {
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const struct bus_mux *lvds_mux = NULL;
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if (imx_ldb_ch == &ldb->channel[0])
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lvds_mux = &ldb->lvds_mux[0];
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else if (imx_ldb_ch == &ldb->channel[1])
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lvds_mux = &ldb->lvds_mux[1];
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regmap_update_bits(ldb->regmap, lvds_mux->reg, lvds_mux->mask,
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mux << lvds_mux->shift);
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}
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regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
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drm_panel_enable(imx_ldb_ch->panel);
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}
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static void imx_ldb_encoder_mode_set(struct drm_encoder *encoder,
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struct drm_display_mode *orig_mode,
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struct drm_display_mode *mode)
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{
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struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int dual = ldb->ldb_ctrl & LDB_SPLIT_MODE_EN;
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unsigned long serial_clk;
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unsigned long di_clk = mode->clock * 1000;
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int mux = imx_drm_encoder_get_mux_id(imx_ldb_ch->child, encoder);
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if (mode->clock > 170000) {
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dev_warn(ldb->dev,
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"%s: mode exceeds 170 MHz pixel clock\n", __func__);
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}
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if (mode->clock > 85000 && !dual) {
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dev_warn(ldb->dev,
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"%s: mode exceeds 85 MHz pixel clock\n", __func__);
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}
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if (dual) {
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serial_clk = 3500UL * mode->clock;
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imx_ldb_set_clock(ldb, mux, 0, serial_clk, di_clk);
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imx_ldb_set_clock(ldb, mux, 1, serial_clk, di_clk);
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} else {
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serial_clk = 7000UL * mode->clock;
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imx_ldb_set_clock(ldb, mux, imx_ldb_ch->chno, serial_clk,
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di_clk);
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}
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/* FIXME - assumes straight connections DI0 --> CH0, DI1 --> CH1 */
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if (imx_ldb_ch == &ldb->channel[0]) {
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ldb->ldb_ctrl |= LDB_DI0_VS_POL_ACT_LOW;
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else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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ldb->ldb_ctrl &= ~LDB_DI0_VS_POL_ACT_LOW;
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}
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if (imx_ldb_ch == &ldb->channel[1]) {
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if (mode->flags & DRM_MODE_FLAG_NVSYNC)
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ldb->ldb_ctrl |= LDB_DI1_VS_POL_ACT_LOW;
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else if (mode->flags & DRM_MODE_FLAG_PVSYNC)
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ldb->ldb_ctrl &= ~LDB_DI1_VS_POL_ACT_LOW;
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}
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}
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static void imx_ldb_encoder_disable(struct drm_encoder *encoder)
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{
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struct imx_ldb_channel *imx_ldb_ch = enc_to_imx_ldb_ch(encoder);
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int mux, ret;
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/*
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* imx_ldb_encoder_disable is called by
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* drm_helper_disable_unused_functions without
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* the encoder being enabled before.
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*/
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if (imx_ldb_ch == &ldb->channel[0] &&
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(ldb->ldb_ctrl & LDB_CH0_MODE_EN_MASK) == 0)
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return;
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else if (imx_ldb_ch == &ldb->channel[1] &&
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(ldb->ldb_ctrl & LDB_CH1_MODE_EN_MASK) == 0)
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return;
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drm_panel_disable(imx_ldb_ch->panel);
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if (imx_ldb_ch == &ldb->channel[0])
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ldb->ldb_ctrl &= ~LDB_CH0_MODE_EN_MASK;
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else if (imx_ldb_ch == &ldb->channel[1])
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ldb->ldb_ctrl &= ~LDB_CH1_MODE_EN_MASK;
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regmap_write(ldb->regmap, IOMUXC_GPR2, ldb->ldb_ctrl);
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if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
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clk_disable_unprepare(ldb->clk[0]);
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clk_disable_unprepare(ldb->clk[1]);
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}
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if (ldb->lvds_mux) {
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const struct bus_mux *lvds_mux = NULL;
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if (imx_ldb_ch == &ldb->channel[0])
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lvds_mux = &ldb->lvds_mux[0];
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else if (imx_ldb_ch == &ldb->channel[1])
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lvds_mux = &ldb->lvds_mux[1];
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regmap_read(ldb->regmap, lvds_mux->reg, &mux);
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mux &= lvds_mux->mask;
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mux >>= lvds_mux->shift;
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} else {
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mux = (imx_ldb_ch == &ldb->channel[0]) ? 0 : 1;
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}
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/* set display clock mux back to original input clock */
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ret = clk_set_parent(ldb->clk_sel[mux], ldb->clk_parent[mux]);
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if (ret)
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dev_err(ldb->dev,
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"unable to set di%d parent clock to original parent\n",
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mux);
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drm_panel_unprepare(imx_ldb_ch->panel);
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}
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static struct drm_connector_funcs imx_ldb_connector_funcs = {
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.dpms = drm_helper_connector_dpms,
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.fill_modes = drm_helper_probe_single_connector_modes,
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.detect = imx_ldb_connector_detect,
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.destroy = imx_drm_connector_destroy,
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};
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static struct drm_connector_helper_funcs imx_ldb_connector_helper_funcs = {
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.get_modes = imx_ldb_connector_get_modes,
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.best_encoder = imx_ldb_connector_best_encoder,
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};
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static struct drm_encoder_funcs imx_ldb_encoder_funcs = {
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.destroy = imx_drm_encoder_destroy,
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};
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static struct drm_encoder_helper_funcs imx_ldb_encoder_helper_funcs = {
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.dpms = imx_ldb_encoder_dpms,
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.mode_fixup = imx_ldb_encoder_mode_fixup,
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.prepare = imx_ldb_encoder_prepare,
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.commit = imx_ldb_encoder_commit,
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.mode_set = imx_ldb_encoder_mode_set,
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.disable = imx_ldb_encoder_disable,
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};
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static int imx_ldb_get_clk(struct imx_ldb *ldb, int chno)
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{
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char clkname[16];
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snprintf(clkname, sizeof(clkname), "di%d", chno);
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ldb->clk[chno] = devm_clk_get(ldb->dev, clkname);
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if (IS_ERR(ldb->clk[chno]))
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return PTR_ERR(ldb->clk[chno]);
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snprintf(clkname, sizeof(clkname), "di%d_pll", chno);
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ldb->clk_pll[chno] = devm_clk_get(ldb->dev, clkname);
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return PTR_ERR_OR_ZERO(ldb->clk_pll[chno]);
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}
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static int imx_ldb_register(struct drm_device *drm,
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struct imx_ldb_channel *imx_ldb_ch)
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{
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struct imx_ldb *ldb = imx_ldb_ch->ldb;
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int ret;
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ret = imx_drm_encoder_parse_of(drm, &imx_ldb_ch->encoder,
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imx_ldb_ch->child);
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if (ret)
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return ret;
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ret = imx_ldb_get_clk(ldb, imx_ldb_ch->chno);
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if (ret)
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return ret;
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if (ldb->ldb_ctrl & LDB_SPLIT_MODE_EN) {
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ret = imx_ldb_get_clk(ldb, 1);
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if (ret)
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return ret;
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}
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drm_encoder_helper_add(&imx_ldb_ch->encoder,
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&imx_ldb_encoder_helper_funcs);
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drm_encoder_init(drm, &imx_ldb_ch->encoder, &imx_ldb_encoder_funcs,
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DRM_MODE_ENCODER_LVDS);
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drm_connector_helper_add(&imx_ldb_ch->connector,
|
|
&imx_ldb_connector_helper_funcs);
|
|
drm_connector_init(drm, &imx_ldb_ch->connector,
|
|
&imx_ldb_connector_funcs, DRM_MODE_CONNECTOR_LVDS);
|
|
|
|
if (imx_ldb_ch->panel)
|
|
drm_panel_attach(imx_ldb_ch->panel, &imx_ldb_ch->connector);
|
|
|
|
drm_mode_connector_attach_encoder(&imx_ldb_ch->connector,
|
|
&imx_ldb_ch->encoder);
|
|
|
|
return 0;
|
|
}
|
|
|
|
enum {
|
|
LVDS_BIT_MAP_SPWG,
|
|
LVDS_BIT_MAP_JEIDA
|
|
};
|
|
|
|
struct imx_ldb_bit_mapping {
|
|
u32 bus_format;
|
|
u32 datawidth;
|
|
const char * const mapping;
|
|
};
|
|
|
|
static const struct imx_ldb_bit_mapping imx_ldb_bit_mappings[] = {
|
|
{ MEDIA_BUS_FMT_RGB666_1X7X3_SPWG, 18, "spwg" },
|
|
{ MEDIA_BUS_FMT_RGB888_1X7X4_SPWG, 24, "spwg" },
|
|
{ MEDIA_BUS_FMT_RGB888_1X7X4_JEIDA, 24, "jeida" },
|
|
};
|
|
|
|
static u32 of_get_bus_format(struct device *dev, struct device_node *np)
|
|
{
|
|
const char *bm;
|
|
u32 datawidth = 0;
|
|
int ret, i;
|
|
|
|
ret = of_property_read_string(np, "fsl,data-mapping", &bm);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
of_property_read_u32(np, "fsl,data-width", &datawidth);
|
|
|
|
for (i = 0; i < ARRAY_SIZE(imx_ldb_bit_mappings); i++) {
|
|
if (!strcasecmp(bm, imx_ldb_bit_mappings[i].mapping) &&
|
|
datawidth == imx_ldb_bit_mappings[i].datawidth)
|
|
return imx_ldb_bit_mappings[i].bus_format;
|
|
}
|
|
|
|
dev_err(dev, "invalid data mapping: %d-bit \"%s\"\n", datawidth, bm);
|
|
|
|
return -ENOENT;
|
|
}
|
|
|
|
static struct bus_mux imx6q_lvds_mux[2] = {
|
|
{
|
|
.reg = IOMUXC_GPR3,
|
|
.shift = 6,
|
|
.mask = IMX6Q_GPR3_LVDS0_MUX_CTL_MASK,
|
|
}, {
|
|
.reg = IOMUXC_GPR3,
|
|
.shift = 8,
|
|
.mask = IMX6Q_GPR3_LVDS1_MUX_CTL_MASK,
|
|
}
|
|
};
|
|
|
|
/*
|
|
* For a device declaring compatible = "fsl,imx6q-ldb", "fsl,imx53-ldb",
|
|
* of_match_device will walk through this list and take the first entry
|
|
* matching any of its compatible values. Therefore, the more generic
|
|
* entries (in this case fsl,imx53-ldb) need to be ordered last.
|
|
*/
|
|
static const struct of_device_id imx_ldb_dt_ids[] = {
|
|
{ .compatible = "fsl,imx6q-ldb", .data = imx6q_lvds_mux, },
|
|
{ .compatible = "fsl,imx53-ldb", .data = NULL, },
|
|
{ }
|
|
};
|
|
MODULE_DEVICE_TABLE(of, imx_ldb_dt_ids);
|
|
|
|
static int imx_ldb_bind(struct device *dev, struct device *master, void *data)
|
|
{
|
|
struct drm_device *drm = data;
|
|
struct device_node *np = dev->of_node;
|
|
const struct of_device_id *of_id =
|
|
of_match_device(imx_ldb_dt_ids, dev);
|
|
struct device_node *child;
|
|
const u8 *edidp;
|
|
struct imx_ldb *imx_ldb;
|
|
int dual;
|
|
int ret;
|
|
int i;
|
|
|
|
imx_ldb = devm_kzalloc(dev, sizeof(*imx_ldb), GFP_KERNEL);
|
|
if (!imx_ldb)
|
|
return -ENOMEM;
|
|
|
|
imx_ldb->regmap = syscon_regmap_lookup_by_phandle(np, "gpr");
|
|
if (IS_ERR(imx_ldb->regmap)) {
|
|
dev_err(dev, "failed to get parent regmap\n");
|
|
return PTR_ERR(imx_ldb->regmap);
|
|
}
|
|
|
|
imx_ldb->dev = dev;
|
|
|
|
if (of_id)
|
|
imx_ldb->lvds_mux = of_id->data;
|
|
|
|
dual = of_property_read_bool(np, "fsl,dual-channel");
|
|
if (dual)
|
|
imx_ldb->ldb_ctrl |= LDB_SPLIT_MODE_EN;
|
|
|
|
/*
|
|
* There are three different possible clock mux configurations:
|
|
* i.MX53: ipu1_di0_sel, ipu1_di1_sel
|
|
* i.MX6q: ipu1_di0_sel, ipu1_di1_sel, ipu2_di0_sel, ipu2_di1_sel
|
|
* i.MX6dl: ipu1_di0_sel, ipu1_di1_sel, lcdif_sel
|
|
* Map them all to di0_sel...di3_sel.
|
|
*/
|
|
for (i = 0; i < 4; i++) {
|
|
char clkname[16];
|
|
|
|
sprintf(clkname, "di%d_sel", i);
|
|
imx_ldb->clk_sel[i] = devm_clk_get(imx_ldb->dev, clkname);
|
|
if (IS_ERR(imx_ldb->clk_sel[i])) {
|
|
ret = PTR_ERR(imx_ldb->clk_sel[i]);
|
|
imx_ldb->clk_sel[i] = NULL;
|
|
break;
|
|
}
|
|
|
|
imx_ldb->clk_parent[i] = clk_get_parent(imx_ldb->clk_sel[i]);
|
|
}
|
|
if (i == 0)
|
|
return ret;
|
|
|
|
for_each_child_of_node(np, child) {
|
|
struct imx_ldb_channel *channel;
|
|
struct device_node *port;
|
|
|
|
ret = of_property_read_u32(child, "reg", &i);
|
|
if (ret || i < 0 || i > 1)
|
|
return -EINVAL;
|
|
|
|
if (dual && i > 0) {
|
|
dev_warn(dev, "dual-channel mode, ignoring second output\n");
|
|
continue;
|
|
}
|
|
|
|
if (!of_device_is_available(child))
|
|
continue;
|
|
|
|
channel = &imx_ldb->channel[i];
|
|
channel->ldb = imx_ldb;
|
|
channel->chno = i;
|
|
channel->child = child;
|
|
|
|
/*
|
|
* The output port is port@4 with an external 4-port mux or
|
|
* port@2 with the internal 2-port mux.
|
|
*/
|
|
port = of_graph_get_port_by_id(child, imx_ldb->lvds_mux ? 4 : 2);
|
|
if (port) {
|
|
struct device_node *endpoint, *remote;
|
|
|
|
endpoint = of_get_child_by_name(port, "endpoint");
|
|
if (endpoint) {
|
|
remote = of_graph_get_remote_port_parent(endpoint);
|
|
if (remote)
|
|
channel->panel = of_drm_find_panel(remote);
|
|
else
|
|
return -EPROBE_DEFER;
|
|
if (!channel->panel) {
|
|
dev_err(dev, "panel not found: %s\n",
|
|
remote->full_name);
|
|
return -EPROBE_DEFER;
|
|
}
|
|
}
|
|
}
|
|
|
|
edidp = of_get_property(child, "edid", &channel->edid_len);
|
|
if (edidp) {
|
|
channel->edid = kmemdup(edidp, channel->edid_len,
|
|
GFP_KERNEL);
|
|
} else if (!channel->panel) {
|
|
ret = of_get_drm_display_mode(child, &channel->mode, 0);
|
|
if (!ret)
|
|
channel->mode_valid = 1;
|
|
}
|
|
|
|
channel->bus_format = of_get_bus_format(dev, child);
|
|
if (channel->bus_format == -EINVAL) {
|
|
/*
|
|
* If no bus format was specified in the device tree,
|
|
* we can still get it from the connected panel later.
|
|
*/
|
|
if (channel->panel && channel->panel->funcs &&
|
|
channel->panel->funcs->get_modes)
|
|
channel->bus_format = 0;
|
|
}
|
|
if (channel->bus_format < 0) {
|
|
dev_err(dev, "could not determine data mapping: %d\n",
|
|
channel->bus_format);
|
|
return channel->bus_format;
|
|
}
|
|
|
|
ret = imx_ldb_register(drm, channel);
|
|
if (ret)
|
|
return ret;
|
|
}
|
|
|
|
dev_set_drvdata(dev, imx_ldb);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static void imx_ldb_unbind(struct device *dev, struct device *master,
|
|
void *data)
|
|
{
|
|
struct imx_ldb *imx_ldb = dev_get_drvdata(dev);
|
|
int i;
|
|
|
|
for (i = 0; i < 2; i++) {
|
|
struct imx_ldb_channel *channel = &imx_ldb->channel[i];
|
|
|
|
if (!channel->connector.funcs)
|
|
continue;
|
|
|
|
channel->connector.funcs->destroy(&channel->connector);
|
|
channel->encoder.funcs->destroy(&channel->encoder);
|
|
|
|
kfree(channel->edid);
|
|
}
|
|
}
|
|
|
|
static const struct component_ops imx_ldb_ops = {
|
|
.bind = imx_ldb_bind,
|
|
.unbind = imx_ldb_unbind,
|
|
};
|
|
|
|
static int imx_ldb_probe(struct platform_device *pdev)
|
|
{
|
|
return component_add(&pdev->dev, &imx_ldb_ops);
|
|
}
|
|
|
|
static int imx_ldb_remove(struct platform_device *pdev)
|
|
{
|
|
component_del(&pdev->dev, &imx_ldb_ops);
|
|
return 0;
|
|
}
|
|
|
|
static struct platform_driver imx_ldb_driver = {
|
|
.probe = imx_ldb_probe,
|
|
.remove = imx_ldb_remove,
|
|
.driver = {
|
|
.of_match_table = imx_ldb_dt_ids,
|
|
.name = DRIVER_NAME,
|
|
},
|
|
};
|
|
|
|
module_platform_driver(imx_ldb_driver);
|
|
|
|
MODULE_DESCRIPTION("i.MX LVDS driver");
|
|
MODULE_AUTHOR("Sascha Hauer, Pengutronix");
|
|
MODULE_LICENSE("GPL");
|
|
MODULE_ALIAS("platform:" DRIVER_NAME);
|