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![Alex Deucher](/assets/img/avatar_default.png)
Noticed by Rashika Kheria and cherry-picked from her larger patch set. Signed-off-by: Alex Deucher <alexander.deucher@amd.com> Cc: Rashika Kheria <rashika.kheria@gmail.com>
221 lines
5.5 KiB
C
221 lines
5.5 KiB
C
/*
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* Copyright 2012 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#include "drmP.h"
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#include "radeon.h"
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#include "sumod.h"
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#include "sumo_dpm.h"
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#include "ppsmc.h"
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#define SUMO_SMU_SERVICE_ROUTINE_PG_INIT 1
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#define SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY 27
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#define SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20 20
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struct sumo_power_info *sumo_get_pi(struct radeon_device *rdev);
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static void sumo_send_msg_to_smu(struct radeon_device *rdev, u32 id)
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{
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u32 gfx_int_req;
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int i;
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(GFX_INT_STATUS) & INT_DONE)
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break;
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udelay(1);
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}
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gfx_int_req = SERV_INDEX(id) | INT_REQ;
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WREG32(GFX_INT_REQ, gfx_int_req);
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(GFX_INT_REQ) & INT_REQ)
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break;
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udelay(1);
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(GFX_INT_STATUS) & INT_ACK)
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break;
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udelay(1);
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}
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for (i = 0; i < rdev->usec_timeout; i++) {
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if (RREG32(GFX_INT_STATUS) & INT_DONE)
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break;
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udelay(1);
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}
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gfx_int_req &= ~INT_REQ;
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WREG32(GFX_INT_REQ, gfx_int_req);
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}
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void sumo_initialize_m3_arb(struct radeon_device *rdev)
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{
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struct sumo_power_info *pi = sumo_get_pi(rdev);
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u32 i;
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if (!pi->enable_dynamic_m3_arbiter)
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return;
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for (i = 0; i < NUMBER_OF_M3ARB_PARAM_SETS; i++)
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WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
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pi->sys_info.csr_m3_arb_cntl_default[i]);
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for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 2; i++)
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WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
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pi->sys_info.csr_m3_arb_cntl_uvd[i % NUMBER_OF_M3ARB_PARAM_SETS]);
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for (; i < NUMBER_OF_M3ARB_PARAM_SETS * 3; i++)
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WREG32_RCU(MCU_M3ARB_PARAMS + (i * 4),
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pi->sys_info.csr_m3_arb_cntl_fs3d[i % NUMBER_OF_M3ARB_PARAM_SETS]);
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}
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static bool sumo_is_alt_vddnb_supported(struct radeon_device *rdev)
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{
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struct sumo_power_info *pi = sumo_get_pi(rdev);
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bool return_code = false;
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if (!pi->enable_alt_vddnb)
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return return_code;
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if ((rdev->family == CHIP_SUMO) || (rdev->family == CHIP_SUMO2)) {
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if (pi->fw_version >= 0x00010C00)
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return_code = true;
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}
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return return_code;
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}
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void sumo_smu_notify_alt_vddnb_change(struct radeon_device *rdev,
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bool powersaving, bool force_nbps1)
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{
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u32 param = 0;
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if (!sumo_is_alt_vddnb_supported(rdev))
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return;
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if (powersaving)
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param |= 1;
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if (force_nbps1)
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param |= 2;
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WREG32_RCU(RCU_ALTVDDNB_NOTIFY, param);
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sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_ALTVDDNB_NOTIFY);
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}
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void sumo_smu_pg_init(struct radeon_device *rdev)
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{
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sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_PG_INIT);
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}
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static u32 sumo_power_of_4(u32 unit)
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{
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u32 ret = 1;
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u32 i;
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for (i = 0; i < unit; i++)
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ret *= 4;
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return ret;
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}
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void sumo_enable_boost_timer(struct radeon_device *rdev)
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{
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struct sumo_power_info *pi = sumo_get_pi(rdev);
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u32 period, unit, timer_value;
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u32 xclk = radeon_get_xclk(rdev);
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unit = (RREG32_RCU(RCU_LCLK_SCALING_CNTL) & LCLK_SCALING_TIMER_PRESCALER_MASK)
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>> LCLK_SCALING_TIMER_PRESCALER_SHIFT;
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period = 100 * (xclk / 100 / sumo_power_of_4(unit));
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timer_value = (period << 16) | (unit << 4);
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WREG32_RCU(RCU_GNB_PWR_REP_TIMER_CNTL, timer_value);
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WREG32_RCU(RCU_BOOST_MARGIN, pi->sys_info.sclk_dpm_boost_margin);
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WREG32_RCU(RCU_THROTTLE_MARGIN, pi->sys_info.sclk_dpm_throttle_margin);
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WREG32_RCU(GNB_TDP_LIMIT, pi->sys_info.gnb_tdp_limit);
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WREG32_RCU(RCU_SclkDpmTdpLimitPG, pi->sys_info.sclk_dpm_tdp_limit_pg);
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sumo_send_msg_to_smu(rdev, SUMO_SMU_SERVICE_ROUTINE_GFX_SRV_ID_20);
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}
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void sumo_set_tdp_limit(struct radeon_device *rdev, u32 index, u32 tdp_limit)
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{
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u32 regoffset = 0;
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u32 shift = 0;
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u32 mask = 0xFFF;
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u32 sclk_dpm_tdp_limit;
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switch (index) {
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case 0:
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regoffset = RCU_SclkDpmTdpLimit01;
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shift = 16;
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break;
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case 1:
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regoffset = RCU_SclkDpmTdpLimit01;
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shift = 0;
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break;
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case 2:
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regoffset = RCU_SclkDpmTdpLimit23;
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shift = 16;
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break;
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case 3:
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regoffset = RCU_SclkDpmTdpLimit23;
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shift = 0;
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break;
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case 4:
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regoffset = RCU_SclkDpmTdpLimit47;
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shift = 16;
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break;
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case 7:
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regoffset = RCU_SclkDpmTdpLimit47;
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shift = 0;
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break;
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default:
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break;
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}
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sclk_dpm_tdp_limit = RREG32_RCU(regoffset);
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sclk_dpm_tdp_limit &= ~(mask << shift);
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sclk_dpm_tdp_limit |= (tdp_limit << shift);
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WREG32_RCU(regoffset, sclk_dpm_tdp_limit);
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}
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void sumo_boost_state_enable(struct radeon_device *rdev, bool enable)
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{
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u32 boost_disable = RREG32_RCU(RCU_GPU_BOOST_DISABLE);
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boost_disable &= 0xFFFFFFFE;
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boost_disable |= (enable ? 0 : 1);
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WREG32_RCU(RCU_GPU_BOOST_DISABLE, boost_disable);
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}
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u32 sumo_get_running_fw_version(struct radeon_device *rdev)
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{
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return RREG32_RCU(RCU_FW_VERSION);
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}
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