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![Jianwei Wang](/assets/img/avatar_default.png)
This patch add support for Two Dimensional Animation and Compositing Engine (2D-ACE) on the Freescale SoCs. 2D-ACE is a Freescale display controller. 2D-ACE describes the functionality of the module extremely well its name is a value that cannot be used as a token in programming languages. Instead the valid token "DCU" is used to tag the register names and function names. The Display Controller Unit (DCU) module is a system master that fetches graphics stored in internal or external memory and displays them on a TFT LCD panel. A wide range of panel sizes is supported and the timing of the interface signals is highly configurable. Graphics are read directly from memory and then blended in real-time, which allows for dynamic content creation with minimal CPU intervention. The features: (1) Full RGB888 output to TFT LCD panel. (2) Blending of each pixel using up to 4 source layers dependent on size of panel. (3) Each graphic layer can be placed with one pixel resolution in either axis. (4) Each graphic layer support RGB565 and RGB888 direct colors without alpha channel and BGRA8888 BGRA4444 ARGB1555 direct colors with an alpha channel and YUV422 format. (5) Each graphic layer support alpha blending with 8-bit resolution. This is a simplified version, only one primary plane, one framebuffer, one crtc, one connector and one encoder for TFT LCD panel. Signed-off-by: Alison Wang <b18965@freescale.com> Signed-off-by: Xiubo Li <lixiubo@cmss.chinamobile.com> Signed-off-by: Jianwei Wang <jianwei.wang.chn@gmail.com> Acked-by: Daniel Vetter <daniel.vetter@ffwll.ch>
261 lines
6.7 KiB
C
261 lines
6.7 KiB
C
/*
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* Copyright 2015 Freescale Semiconductor, Inc.
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*
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* Freescale DCU drm device driver
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; either version 2 of the License, or
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* (at your option) any later version.
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*/
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#include <linux/regmap.h>
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#include <drm/drmP.h>
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#include <drm/drm_atomic_helper.h>
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#include <drm/drm_crtc.h>
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#include <drm/drm_crtc_helper.h>
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#include <drm/drm_fb_cma_helper.h>
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#include <drm/drm_gem_cma_helper.h>
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#include <drm/drm_plane_helper.h>
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#include "fsl_dcu_drm_drv.h"
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#include "fsl_dcu_drm_plane.h"
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static int fsl_dcu_drm_plane_index(struct drm_plane *plane)
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{
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struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
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unsigned int total_layer = fsl_dev->soc->total_layer;
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unsigned int index;
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index = drm_plane_index(plane);
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if (index < total_layer)
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return total_layer - index - 1;
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dev_err(fsl_dev->dev, "No more layer left\n");
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return -EINVAL;
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}
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static int fsl_dcu_drm_plane_atomic_check(struct drm_plane *plane,
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struct drm_plane_state *state)
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{
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struct drm_framebuffer *fb = state->fb;
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switch (fb->pixel_format) {
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case DRM_FORMAT_RGB565:
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case DRM_FORMAT_RGB888:
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case DRM_FORMAT_ARGB8888:
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case DRM_FORMAT_BGRA4444:
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case DRM_FORMAT_ARGB1555:
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case DRM_FORMAT_YUV422:
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return 0;
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default:
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return -EINVAL;
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}
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}
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static void fsl_dcu_drm_plane_atomic_disable(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
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unsigned int index, value, ret;
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index = fsl_dcu_drm_plane_index(plane);
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if (index < 0)
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return;
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ret = regmap_read(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), &value);
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if (ret)
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dev_err(fsl_dev->dev, "read DCU_INT_MASK failed\n");
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value &= ~DCU_LAYER_EN;
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4), value);
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if (ret)
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dev_err(fsl_dev->dev, "set DCU register failed\n");
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}
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static void fsl_dcu_drm_plane_atomic_update(struct drm_plane *plane,
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struct drm_plane_state *old_state)
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{
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struct fsl_dcu_drm_device *fsl_dev = plane->dev->dev_private;
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struct drm_plane_state *state = plane->state;
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struct drm_framebuffer *fb = plane->state->fb;
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struct drm_gem_cma_object *gem;
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unsigned int alpha, bpp;
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int index, ret;
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if (!fb)
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return;
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index = fsl_dcu_drm_plane_index(plane);
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if (index < 0)
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return;
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gem = drm_fb_cma_get_gem_obj(fb, 0);
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switch (fb->pixel_format) {
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case DRM_FORMAT_RGB565:
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bpp = FSL_DCU_RGB565;
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alpha = 0xff;
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break;
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case DRM_FORMAT_RGB888:
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bpp = FSL_DCU_RGB888;
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alpha = 0xff;
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break;
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case DRM_FORMAT_ARGB8888:
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bpp = FSL_DCU_ARGB8888;
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alpha = 0xff;
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break;
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case DRM_FORMAT_BGRA4444:
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bpp = FSL_DCU_ARGB4444;
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alpha = 0xff;
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break;
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case DRM_FORMAT_ARGB1555:
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bpp = FSL_DCU_ARGB1555;
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alpha = 0xff;
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break;
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case DRM_FORMAT_YUV422:
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bpp = FSL_DCU_YUV422;
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alpha = 0xff;
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break;
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default:
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return;
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}
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 1),
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DCU_LAYER_HEIGHT(state->crtc_h) |
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DCU_LAYER_WIDTH(state->crtc_w));
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 2),
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DCU_LAYER_POSY(state->crtc_y) |
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DCU_LAYER_POSX(state->crtc_x));
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap,
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DCU_CTRLDESCLN(index, 3), gem->paddr);
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 4),
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DCU_LAYER_EN |
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DCU_LAYER_TRANS(alpha) |
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DCU_LAYER_BPP(bpp) |
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DCU_LAYER_AB(0));
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 5),
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DCU_LAYER_CKMAX_R(0xFF) |
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DCU_LAYER_CKMAX_G(0xFF) |
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DCU_LAYER_CKMAX_B(0xFF));
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 6),
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DCU_LAYER_CKMIN_R(0) |
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DCU_LAYER_CKMIN_G(0) |
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DCU_LAYER_CKMIN_B(0));
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 7), 0);
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 8),
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DCU_LAYER_FG_FCOLOR(0));
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 9),
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DCU_LAYER_BG_BCOLOR(0));
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if (ret)
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goto set_failed;
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if (!strcmp(fsl_dev->soc->name, "ls1021a")) {
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ret = regmap_write(fsl_dev->regmap, DCU_CTRLDESCLN(index, 10),
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DCU_LAYER_POST_SKIP(0) |
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DCU_LAYER_PRE_SKIP(0));
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if (ret)
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goto set_failed;
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}
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ret = regmap_update_bits(fsl_dev->regmap, DCU_DCU_MODE,
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DCU_MODE_DCU_MODE_MASK,
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DCU_MODE_DCU_MODE(DCU_MODE_NORMAL));
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if (ret)
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goto set_failed;
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ret = regmap_write(fsl_dev->regmap,
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DCU_UPDATE_MODE, DCU_UPDATE_MODE_READREG);
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if (ret)
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goto set_failed;
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return;
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set_failed:
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dev_err(fsl_dev->dev, "set DCU register failed\n");
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}
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static void
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fsl_dcu_drm_plane_cleanup_fb(struct drm_plane *plane,
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struct drm_framebuffer *fb,
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const struct drm_plane_state *new_state)
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{
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}
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static int
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fsl_dcu_drm_plane_prepare_fb(struct drm_plane *plane,
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struct drm_framebuffer *fb,
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const struct drm_plane_state *new_state)
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{
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return 0;
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}
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static const struct drm_plane_helper_funcs fsl_dcu_drm_plane_helper_funcs = {
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.atomic_check = fsl_dcu_drm_plane_atomic_check,
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.atomic_disable = fsl_dcu_drm_plane_atomic_disable,
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.atomic_update = fsl_dcu_drm_plane_atomic_update,
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.cleanup_fb = fsl_dcu_drm_plane_cleanup_fb,
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.prepare_fb = fsl_dcu_drm_plane_prepare_fb,
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};
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static void fsl_dcu_drm_plane_destroy(struct drm_plane *plane)
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{
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drm_plane_cleanup(plane);
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}
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static const struct drm_plane_funcs fsl_dcu_drm_plane_funcs = {
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.atomic_duplicate_state = drm_atomic_helper_plane_duplicate_state,
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.atomic_destroy_state = drm_atomic_helper_plane_destroy_state,
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.destroy = fsl_dcu_drm_plane_destroy,
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.disable_plane = drm_atomic_helper_disable_plane,
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.reset = drm_atomic_helper_plane_reset,
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.update_plane = drm_atomic_helper_update_plane,
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};
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static const u32 fsl_dcu_drm_plane_formats[] = {
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DRM_FORMAT_RGB565,
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DRM_FORMAT_RGB888,
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DRM_FORMAT_ARGB8888,
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DRM_FORMAT_ARGB4444,
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DRM_FORMAT_ARGB1555,
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DRM_FORMAT_YUV422,
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};
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struct drm_plane *fsl_dcu_drm_primary_create_plane(struct drm_device *dev)
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{
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struct drm_plane *primary;
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int ret;
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primary = kzalloc(sizeof(*primary), GFP_KERNEL);
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if (!primary) {
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DRM_DEBUG_KMS("Failed to allocate primary plane\n");
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return NULL;
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}
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/* possible_crtc's will be filled in later by crtc_init */
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ret = drm_universal_plane_init(dev, primary, 0,
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&fsl_dcu_drm_plane_funcs,
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fsl_dcu_drm_plane_formats,
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ARRAY_SIZE(fsl_dcu_drm_plane_formats),
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DRM_PLANE_TYPE_PRIMARY);
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if (ret) {
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kfree(primary);
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primary = NULL;
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}
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drm_plane_helper_add(primary, &fsl_dcu_drm_plane_helper_funcs);
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return primary;
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}
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