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https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
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![Jani Nikula](/assets/img/avatar_default.png)
They are not to be modified. Generated using the semantic patch: @@ @@ ( const struct drm_crtc_helper_funcs * | - struct drm_crtc_helper_funcs * + const struct drm_crtc_helper_funcs * ) @@ @@ ( const struct drm_encoder_helper_funcs * | - struct drm_encoder_helper_funcs * + const struct drm_encoder_helper_funcs * ) @@ @@ ( const struct drm_connector_helper_funcs * | - struct drm_connector_helper_funcs * + const struct drm_connector_helper_funcs * ) @@ @@ ( const struct drm_plane_helper_funcs * | - struct drm_plane_helper_funcs * + const struct drm_plane_helper_funcs * ) Signed-off-by: Jani Nikula <jani.nikula@intel.com> Reviewed-by: Patrik Jakobsson <patrik.r.jakobsson@gmail.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
791 lines
21 KiB
C
791 lines
21 KiB
C
/*
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* Copyright © 2006-2011 Intel Corporation
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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* You should have received a copy of the GNU General Public License along with
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* this program; if not, write to the Free Software Foundation, Inc.,
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* 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Patrik Jakobsson <patrik.r.jakobsson@gmail.com>
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*/
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#include <drm/drmP.h>
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#include "gma_display.h"
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#include "psb_intel_drv.h"
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#include "psb_intel_reg.h"
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#include "psb_drv.h"
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#include "framebuffer.h"
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/**
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* Returns whether any output on the specified pipe is of the specified type
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*/
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bool gma_pipe_has_type(struct drm_crtc *crtc, int type)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_mode_config *mode_config = &dev->mode_config;
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struct drm_connector *l_entry;
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list_for_each_entry(l_entry, &mode_config->connector_list, head) {
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if (l_entry->encoder && l_entry->encoder->crtc == crtc) {
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struct gma_encoder *gma_encoder =
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gma_attached_encoder(l_entry);
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if (gma_encoder->type == type)
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return true;
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}
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}
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return false;
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}
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void gma_wait_for_vblank(struct drm_device *dev)
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{
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/* Wait for 20ms, i.e. one cycle at 50hz. */
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mdelay(20);
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}
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int gma_pipe_set_base(struct drm_crtc *crtc, int x, int y,
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struct drm_framebuffer *old_fb)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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struct psb_framebuffer *psbfb = to_psb_fb(crtc->primary->fb);
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int pipe = gma_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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unsigned long start, offset;
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u32 dspcntr;
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int ret = 0;
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if (!gma_power_begin(dev, true))
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return 0;
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/* no fb bound */
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if (!crtc->primary->fb) {
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dev_err(dev->dev, "No FB bound\n");
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goto gma_pipe_cleaner;
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}
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/* We are displaying this buffer, make sure it is actually loaded
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into the GTT */
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ret = psb_gtt_pin(psbfb->gtt);
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if (ret < 0)
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goto gma_pipe_set_base_exit;
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start = psbfb->gtt->offset;
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offset = y * crtc->primary->fb->pitches[0] + x * (crtc->primary->fb->bits_per_pixel / 8);
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REG_WRITE(map->stride, crtc->primary->fb->pitches[0]);
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dspcntr = REG_READ(map->cntr);
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dspcntr &= ~DISPPLANE_PIXFORMAT_MASK;
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switch (crtc->primary->fb->bits_per_pixel) {
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case 8:
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dspcntr |= DISPPLANE_8BPP;
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break;
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case 16:
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if (crtc->primary->fb->depth == 15)
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dspcntr |= DISPPLANE_15_16BPP;
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else
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dspcntr |= DISPPLANE_16BPP;
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break;
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case 24:
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case 32:
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dspcntr |= DISPPLANE_32BPP_NO_ALPHA;
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break;
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default:
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dev_err(dev->dev, "Unknown color depth\n");
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ret = -EINVAL;
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goto gma_pipe_set_base_exit;
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}
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REG_WRITE(map->cntr, dspcntr);
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dev_dbg(dev->dev,
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"Writing base %08lX %08lX %d %d\n", start, offset, x, y);
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/* FIXME: Investigate whether this really is the base for psb and why
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the linear offset is named base for the other chips. map->surf
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should be the base and map->linoff the offset for all chips */
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if (IS_PSB(dev)) {
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REG_WRITE(map->base, offset + start);
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REG_READ(map->base);
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} else {
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REG_WRITE(map->base, offset);
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REG_READ(map->base);
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REG_WRITE(map->surf, start);
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REG_READ(map->surf);
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}
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gma_pipe_cleaner:
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/* If there was a previous display we can now unpin it */
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if (old_fb)
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psb_gtt_unpin(to_psb_fb(old_fb)->gtt);
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gma_pipe_set_base_exit:
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gma_power_end(dev);
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return ret;
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}
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/* Loads the palette/gamma unit for the CRTC with the prepared values */
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void gma_crtc_load_lut(struct drm_crtc *crtc)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
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int palreg = map->palette;
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int i;
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/* The clocks have to be on to load the palette. */
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if (!crtc->enabled)
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return;
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if (gma_power_begin(dev, false)) {
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for (i = 0; i < 256; i++) {
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REG_WRITE(palreg + 4 * i,
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((gma_crtc->lut_r[i] +
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gma_crtc->lut_adj[i]) << 16) |
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((gma_crtc->lut_g[i] +
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gma_crtc->lut_adj[i]) << 8) |
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(gma_crtc->lut_b[i] +
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gma_crtc->lut_adj[i]));
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}
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gma_power_end(dev);
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} else {
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for (i = 0; i < 256; i++) {
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/* FIXME: Why pipe[0] and not pipe[..._crtc->pipe]? */
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dev_priv->regs.pipe[0].palette[i] =
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((gma_crtc->lut_r[i] +
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gma_crtc->lut_adj[i]) << 16) |
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((gma_crtc->lut_g[i] +
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gma_crtc->lut_adj[i]) << 8) |
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(gma_crtc->lut_b[i] +
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gma_crtc->lut_adj[i]);
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}
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}
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}
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void gma_crtc_gamma_set(struct drm_crtc *crtc, u16 *red, u16 *green, u16 *blue,
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u32 start, u32 size)
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{
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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int i;
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int end = (start + size > 256) ? 256 : start + size;
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for (i = start; i < end; i++) {
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gma_crtc->lut_r[i] = red[i] >> 8;
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gma_crtc->lut_g[i] = green[i] >> 8;
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gma_crtc->lut_b[i] = blue[i] >> 8;
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}
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gma_crtc_load_lut(crtc);
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}
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/**
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* Sets the power management mode of the pipe and plane.
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*
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* This code should probably grow support for turning the cursor off and back
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* on appropriately at the same time as we're turning the pipe off/on.
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*/
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void gma_crtc_dpms(struct drm_crtc *crtc, int mode)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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int pipe = gma_crtc->pipe;
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const struct psb_offset *map = &dev_priv->regmap[pipe];
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u32 temp;
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/* XXX: When our outputs are all unaware of DPMS modes other than off
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* and on, we should map those modes to DRM_MODE_DPMS_OFF in the CRTC.
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*/
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if (IS_CDV(dev))
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dev_priv->ops->disable_sr(dev);
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switch (mode) {
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case DRM_MODE_DPMS_ON:
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case DRM_MODE_DPMS_STANDBY:
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case DRM_MODE_DPMS_SUSPEND:
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if (gma_crtc->active)
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break;
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gma_crtc->active = true;
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/* Enable the DPLL */
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temp = REG_READ(map->dpll);
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if ((temp & DPLL_VCO_ENABLE) == 0) {
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REG_WRITE(map->dpll, temp);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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REG_WRITE(map->dpll, temp | DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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/* Wait for the clocks to stabilize. */
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udelay(150);
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}
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/* Enable the plane */
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temp = REG_READ(map->cntr);
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if ((temp & DISPLAY_PLANE_ENABLE) == 0) {
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REG_WRITE(map->cntr,
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temp | DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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REG_WRITE(map->base, REG_READ(map->base));
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}
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udelay(150);
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/* Enable the pipe */
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temp = REG_READ(map->conf);
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if ((temp & PIPEACONF_ENABLE) == 0)
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REG_WRITE(map->conf, temp | PIPEACONF_ENABLE);
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temp = REG_READ(map->status);
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temp &= ~(0xFFFF);
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temp |= PIPE_FIFO_UNDERRUN;
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REG_WRITE(map->status, temp);
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REG_READ(map->status);
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gma_crtc_load_lut(crtc);
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/* Give the overlay scaler a chance to enable
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* if it's on this pipe */
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/* psb_intel_crtc_dpms_video(crtc, true); TODO */
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break;
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case DRM_MODE_DPMS_OFF:
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if (!gma_crtc->active)
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break;
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gma_crtc->active = false;
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/* Give the overlay scaler a chance to disable
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* if it's on this pipe */
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/* psb_intel_crtc_dpms_video(crtc, FALSE); TODO */
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/* Disable the VGA plane that we never use */
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REG_WRITE(VGACNTRL, VGA_DISP_DISABLE);
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/* Turn off vblank interrupts */
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drm_vblank_off(dev, pipe);
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/* Wait for vblank for the disable to take effect */
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gma_wait_for_vblank(dev);
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/* Disable plane */
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temp = REG_READ(map->cntr);
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if ((temp & DISPLAY_PLANE_ENABLE) != 0) {
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REG_WRITE(map->cntr,
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temp & ~DISPLAY_PLANE_ENABLE);
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/* Flush the plane changes */
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REG_WRITE(map->base, REG_READ(map->base));
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REG_READ(map->base);
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}
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/* Disable pipe */
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temp = REG_READ(map->conf);
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if ((temp & PIPEACONF_ENABLE) != 0) {
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REG_WRITE(map->conf, temp & ~PIPEACONF_ENABLE);
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REG_READ(map->conf);
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}
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/* Wait for vblank for the disable to take effect. */
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gma_wait_for_vblank(dev);
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udelay(150);
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/* Disable DPLL */
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temp = REG_READ(map->dpll);
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if ((temp & DPLL_VCO_ENABLE) != 0) {
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REG_WRITE(map->dpll, temp & ~DPLL_VCO_ENABLE);
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REG_READ(map->dpll);
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}
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/* Wait for the clocks to turn off. */
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udelay(150);
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break;
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}
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if (IS_CDV(dev))
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dev_priv->ops->update_wm(dev, crtc);
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/* Set FIFO watermarks */
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REG_WRITE(DSPARB, 0x3F3E);
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}
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int gma_crtc_cursor_set(struct drm_crtc *crtc,
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struct drm_file *file_priv,
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uint32_t handle,
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uint32_t width, uint32_t height)
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{
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struct drm_device *dev = crtc->dev;
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struct drm_psb_private *dev_priv = dev->dev_private;
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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int pipe = gma_crtc->pipe;
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uint32_t control = (pipe == 0) ? CURACNTR : CURBCNTR;
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uint32_t base = (pipe == 0) ? CURABASE : CURBBASE;
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uint32_t temp;
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size_t addr = 0;
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struct gtt_range *gt;
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struct gtt_range *cursor_gt = gma_crtc->cursor_gt;
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struct drm_gem_object *obj;
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void *tmp_dst, *tmp_src;
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int ret = 0, i, cursor_pages;
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/* If we didn't get a handle then turn the cursor off */
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if (!handle) {
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temp = CURSOR_MODE_DISABLE;
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mutex_lock(&dev->struct_mutex);
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if (gma_power_begin(dev, false)) {
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REG_WRITE(control, temp);
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REG_WRITE(base, 0);
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gma_power_end(dev);
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}
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/* Unpin the old GEM object */
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if (gma_crtc->cursor_obj) {
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gt = container_of(gma_crtc->cursor_obj,
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struct gtt_range, gem);
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psb_gtt_unpin(gt);
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drm_gem_object_unreference(gma_crtc->cursor_obj);
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gma_crtc->cursor_obj = NULL;
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}
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mutex_unlock(&dev->struct_mutex);
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return 0;
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}
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/* Currently we only support 64x64 cursors */
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if (width != 64 || height != 64) {
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dev_dbg(dev->dev, "We currently only support 64x64 cursors\n");
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return -EINVAL;
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}
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mutex_lock(&dev->struct_mutex);
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obj = drm_gem_object_lookup(dev, file_priv, handle);
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if (!obj) {
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ret = -ENOENT;
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goto unlock;
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}
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if (obj->size < width * height * 4) {
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dev_dbg(dev->dev, "Buffer is too small\n");
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ret = -ENOMEM;
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goto unref_cursor;
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}
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gt = container_of(obj, struct gtt_range, gem);
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/* Pin the memory into the GTT */
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ret = psb_gtt_pin(gt);
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if (ret) {
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dev_err(dev->dev, "Can not pin down handle 0x%x\n", handle);
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goto unref_cursor;
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}
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if (dev_priv->ops->cursor_needs_phys) {
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if (cursor_gt == NULL) {
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dev_err(dev->dev, "No hardware cursor mem available");
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ret = -ENOMEM;
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goto unref_cursor;
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}
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/* Prevent overflow */
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if (gt->npage > 4)
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cursor_pages = 4;
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else
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cursor_pages = gt->npage;
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/* Copy the cursor to cursor mem */
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tmp_dst = dev_priv->vram_addr + cursor_gt->offset;
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for (i = 0; i < cursor_pages; i++) {
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tmp_src = kmap(gt->pages[i]);
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memcpy(tmp_dst, tmp_src, PAGE_SIZE);
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kunmap(gt->pages[i]);
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tmp_dst += PAGE_SIZE;
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}
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addr = gma_crtc->cursor_addr;
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} else {
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addr = gt->offset;
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gma_crtc->cursor_addr = addr;
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}
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temp = 0;
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/* set the pipe for the cursor */
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temp |= (pipe << 28);
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temp |= CURSOR_MODE_64_ARGB_AX | MCURSOR_GAMMA_ENABLE;
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if (gma_power_begin(dev, false)) {
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REG_WRITE(control, temp);
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REG_WRITE(base, addr);
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gma_power_end(dev);
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}
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/* unpin the old bo */
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if (gma_crtc->cursor_obj) {
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gt = container_of(gma_crtc->cursor_obj, struct gtt_range, gem);
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psb_gtt_unpin(gt);
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drm_gem_object_unreference(gma_crtc->cursor_obj);
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}
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gma_crtc->cursor_obj = obj;
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unlock:
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mutex_unlock(&dev->struct_mutex);
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return ret;
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unref_cursor:
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drm_gem_object_unreference(obj);
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mutex_unlock(&dev->struct_mutex);
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return ret;
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}
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int gma_crtc_cursor_move(struct drm_crtc *crtc, int x, int y)
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{
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struct drm_device *dev = crtc->dev;
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struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
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int pipe = gma_crtc->pipe;
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uint32_t temp = 0;
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uint32_t addr;
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if (x < 0) {
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temp |= (CURSOR_POS_SIGN << CURSOR_X_SHIFT);
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x = -x;
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}
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if (y < 0) {
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temp |= (CURSOR_POS_SIGN << CURSOR_Y_SHIFT);
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y = -y;
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}
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temp |= ((x & CURSOR_POS_MASK) << CURSOR_X_SHIFT);
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temp |= ((y & CURSOR_POS_MASK) << CURSOR_Y_SHIFT);
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|
|
addr = gma_crtc->cursor_addr;
|
|
|
|
if (gma_power_begin(dev, false)) {
|
|
REG_WRITE((pipe == 0) ? CURAPOS : CURBPOS, temp);
|
|
REG_WRITE((pipe == 0) ? CURABASE : CURBBASE, addr);
|
|
gma_power_end(dev);
|
|
}
|
|
return 0;
|
|
}
|
|
|
|
bool gma_encoder_mode_fixup(struct drm_encoder *encoder,
|
|
const struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
bool gma_crtc_mode_fixup(struct drm_crtc *crtc,
|
|
const struct drm_display_mode *mode,
|
|
struct drm_display_mode *adjusted_mode)
|
|
{
|
|
return true;
|
|
}
|
|
|
|
void gma_crtc_prepare(struct drm_crtc *crtc)
|
|
{
|
|
const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
|
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
|
|
}
|
|
|
|
void gma_crtc_commit(struct drm_crtc *crtc)
|
|
{
|
|
const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
|
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_ON);
|
|
}
|
|
|
|
void gma_crtc_disable(struct drm_crtc *crtc)
|
|
{
|
|
struct gtt_range *gt;
|
|
const struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
|
|
|
|
crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
|
|
|
|
if (crtc->primary->fb) {
|
|
gt = to_psb_fb(crtc->primary->fb)->gtt;
|
|
psb_gtt_unpin(gt);
|
|
}
|
|
}
|
|
|
|
void gma_crtc_destroy(struct drm_crtc *crtc)
|
|
{
|
|
struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
|
|
|
|
kfree(gma_crtc->crtc_state);
|
|
drm_crtc_cleanup(crtc);
|
|
kfree(gma_crtc);
|
|
}
|
|
|
|
int gma_crtc_set_config(struct drm_mode_set *set)
|
|
{
|
|
struct drm_device *dev = set->crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
int ret;
|
|
|
|
if (!dev_priv->rpm_enabled)
|
|
return drm_crtc_helper_set_config(set);
|
|
|
|
pm_runtime_forbid(&dev->pdev->dev);
|
|
ret = drm_crtc_helper_set_config(set);
|
|
pm_runtime_allow(&dev->pdev->dev);
|
|
|
|
return ret;
|
|
}
|
|
|
|
/**
|
|
* Save HW states of given crtc
|
|
*/
|
|
void gma_crtc_save(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
|
|
struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;
|
|
const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
|
|
uint32_t palette_reg;
|
|
int i;
|
|
|
|
if (!crtc_state) {
|
|
dev_err(dev->dev, "No CRTC state found\n");
|
|
return;
|
|
}
|
|
|
|
crtc_state->saveDSPCNTR = REG_READ(map->cntr);
|
|
crtc_state->savePIPECONF = REG_READ(map->conf);
|
|
crtc_state->savePIPESRC = REG_READ(map->src);
|
|
crtc_state->saveFP0 = REG_READ(map->fp0);
|
|
crtc_state->saveFP1 = REG_READ(map->fp1);
|
|
crtc_state->saveDPLL = REG_READ(map->dpll);
|
|
crtc_state->saveHTOTAL = REG_READ(map->htotal);
|
|
crtc_state->saveHBLANK = REG_READ(map->hblank);
|
|
crtc_state->saveHSYNC = REG_READ(map->hsync);
|
|
crtc_state->saveVTOTAL = REG_READ(map->vtotal);
|
|
crtc_state->saveVBLANK = REG_READ(map->vblank);
|
|
crtc_state->saveVSYNC = REG_READ(map->vsync);
|
|
crtc_state->saveDSPSTRIDE = REG_READ(map->stride);
|
|
|
|
/* NOTE: DSPSIZE DSPPOS only for psb */
|
|
crtc_state->saveDSPSIZE = REG_READ(map->size);
|
|
crtc_state->saveDSPPOS = REG_READ(map->pos);
|
|
|
|
crtc_state->saveDSPBASE = REG_READ(map->base);
|
|
|
|
palette_reg = map->palette;
|
|
for (i = 0; i < 256; ++i)
|
|
crtc_state->savePalette[i] = REG_READ(palette_reg + (i << 2));
|
|
}
|
|
|
|
/**
|
|
* Restore HW states of given crtc
|
|
*/
|
|
void gma_crtc_restore(struct drm_crtc *crtc)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
struct drm_psb_private *dev_priv = dev->dev_private;
|
|
struct gma_crtc *gma_crtc = to_gma_crtc(crtc);
|
|
struct psb_intel_crtc_state *crtc_state = gma_crtc->crtc_state;
|
|
const struct psb_offset *map = &dev_priv->regmap[gma_crtc->pipe];
|
|
uint32_t palette_reg;
|
|
int i;
|
|
|
|
if (!crtc_state) {
|
|
dev_err(dev->dev, "No crtc state\n");
|
|
return;
|
|
}
|
|
|
|
if (crtc_state->saveDPLL & DPLL_VCO_ENABLE) {
|
|
REG_WRITE(map->dpll,
|
|
crtc_state->saveDPLL & ~DPLL_VCO_ENABLE);
|
|
REG_READ(map->dpll);
|
|
udelay(150);
|
|
}
|
|
|
|
REG_WRITE(map->fp0, crtc_state->saveFP0);
|
|
REG_READ(map->fp0);
|
|
|
|
REG_WRITE(map->fp1, crtc_state->saveFP1);
|
|
REG_READ(map->fp1);
|
|
|
|
REG_WRITE(map->dpll, crtc_state->saveDPLL);
|
|
REG_READ(map->dpll);
|
|
udelay(150);
|
|
|
|
REG_WRITE(map->htotal, crtc_state->saveHTOTAL);
|
|
REG_WRITE(map->hblank, crtc_state->saveHBLANK);
|
|
REG_WRITE(map->hsync, crtc_state->saveHSYNC);
|
|
REG_WRITE(map->vtotal, crtc_state->saveVTOTAL);
|
|
REG_WRITE(map->vblank, crtc_state->saveVBLANK);
|
|
REG_WRITE(map->vsync, crtc_state->saveVSYNC);
|
|
REG_WRITE(map->stride, crtc_state->saveDSPSTRIDE);
|
|
|
|
REG_WRITE(map->size, crtc_state->saveDSPSIZE);
|
|
REG_WRITE(map->pos, crtc_state->saveDSPPOS);
|
|
|
|
REG_WRITE(map->src, crtc_state->savePIPESRC);
|
|
REG_WRITE(map->base, crtc_state->saveDSPBASE);
|
|
REG_WRITE(map->conf, crtc_state->savePIPECONF);
|
|
|
|
gma_wait_for_vblank(dev);
|
|
|
|
REG_WRITE(map->cntr, crtc_state->saveDSPCNTR);
|
|
REG_WRITE(map->base, crtc_state->saveDSPBASE);
|
|
|
|
gma_wait_for_vblank(dev);
|
|
|
|
palette_reg = map->palette;
|
|
for (i = 0; i < 256; ++i)
|
|
REG_WRITE(palette_reg + (i << 2), crtc_state->savePalette[i]);
|
|
}
|
|
|
|
void gma_encoder_prepare(struct drm_encoder *encoder)
|
|
{
|
|
const struct drm_encoder_helper_funcs *encoder_funcs =
|
|
encoder->helper_private;
|
|
/* lvds has its own version of prepare see psb_intel_lvds_prepare */
|
|
encoder_funcs->dpms(encoder, DRM_MODE_DPMS_OFF);
|
|
}
|
|
|
|
void gma_encoder_commit(struct drm_encoder *encoder)
|
|
{
|
|
const struct drm_encoder_helper_funcs *encoder_funcs =
|
|
encoder->helper_private;
|
|
/* lvds has its own version of commit see psb_intel_lvds_commit */
|
|
encoder_funcs->dpms(encoder, DRM_MODE_DPMS_ON);
|
|
}
|
|
|
|
void gma_encoder_destroy(struct drm_encoder *encoder)
|
|
{
|
|
struct gma_encoder *intel_encoder = to_gma_encoder(encoder);
|
|
|
|
drm_encoder_cleanup(encoder);
|
|
kfree(intel_encoder);
|
|
}
|
|
|
|
/* Currently there is only a 1:1 mapping of encoders and connectors */
|
|
struct drm_encoder *gma_best_encoder(struct drm_connector *connector)
|
|
{
|
|
struct gma_encoder *gma_encoder = gma_attached_encoder(connector);
|
|
|
|
return &gma_encoder->base;
|
|
}
|
|
|
|
void gma_connector_attach_encoder(struct gma_connector *connector,
|
|
struct gma_encoder *encoder)
|
|
{
|
|
connector->encoder = encoder;
|
|
drm_mode_connector_attach_encoder(&connector->base,
|
|
&encoder->base);
|
|
}
|
|
|
|
#define GMA_PLL_INVALID(s) { /* DRM_ERROR(s); */ return false; }
|
|
|
|
bool gma_pll_is_valid(struct drm_crtc *crtc,
|
|
const struct gma_limit_t *limit,
|
|
struct gma_clock_t *clock)
|
|
{
|
|
if (clock->p1 < limit->p1.min || limit->p1.max < clock->p1)
|
|
GMA_PLL_INVALID("p1 out of range");
|
|
if (clock->p < limit->p.min || limit->p.max < clock->p)
|
|
GMA_PLL_INVALID("p out of range");
|
|
if (clock->m2 < limit->m2.min || limit->m2.max < clock->m2)
|
|
GMA_PLL_INVALID("m2 out of range");
|
|
if (clock->m1 < limit->m1.min || limit->m1.max < clock->m1)
|
|
GMA_PLL_INVALID("m1 out of range");
|
|
/* On CDV m1 is always 0 */
|
|
if (clock->m1 <= clock->m2 && clock->m1 != 0)
|
|
GMA_PLL_INVALID("m1 <= m2 && m1 != 0");
|
|
if (clock->m < limit->m.min || limit->m.max < clock->m)
|
|
GMA_PLL_INVALID("m out of range");
|
|
if (clock->n < limit->n.min || limit->n.max < clock->n)
|
|
GMA_PLL_INVALID("n out of range");
|
|
if (clock->vco < limit->vco.min || limit->vco.max < clock->vco)
|
|
GMA_PLL_INVALID("vco out of range");
|
|
/* XXX: We may need to be checking "Dot clock"
|
|
* depending on the multiplier, connector, etc.,
|
|
* rather than just a single range.
|
|
*/
|
|
if (clock->dot < limit->dot.min || limit->dot.max < clock->dot)
|
|
GMA_PLL_INVALID("dot out of range");
|
|
|
|
return true;
|
|
}
|
|
|
|
bool gma_find_best_pll(const struct gma_limit_t *limit,
|
|
struct drm_crtc *crtc, int target, int refclk,
|
|
struct gma_clock_t *best_clock)
|
|
{
|
|
struct drm_device *dev = crtc->dev;
|
|
const struct gma_clock_funcs *clock_funcs =
|
|
to_gma_crtc(crtc)->clock_funcs;
|
|
struct gma_clock_t clock;
|
|
int err = target;
|
|
|
|
if (gma_pipe_has_type(crtc, INTEL_OUTPUT_LVDS) &&
|
|
(REG_READ(LVDS) & LVDS_PORT_EN) != 0) {
|
|
/*
|
|
* For LVDS, if the panel is on, just rely on its current
|
|
* settings for dual-channel. We haven't figured out how to
|
|
* reliably set up different single/dual channel state, if we
|
|
* even can.
|
|
*/
|
|
if ((REG_READ(LVDS) & LVDS_CLKB_POWER_MASK) ==
|
|
LVDS_CLKB_POWER_UP)
|
|
clock.p2 = limit->p2.p2_fast;
|
|
else
|
|
clock.p2 = limit->p2.p2_slow;
|
|
} else {
|
|
if (target < limit->p2.dot_limit)
|
|
clock.p2 = limit->p2.p2_slow;
|
|
else
|
|
clock.p2 = limit->p2.p2_fast;
|
|
}
|
|
|
|
memset(best_clock, 0, sizeof(*best_clock));
|
|
|
|
/* m1 is always 0 on CDV so the outmost loop will run just once */
|
|
for (clock.m1 = limit->m1.min; clock.m1 <= limit->m1.max; clock.m1++) {
|
|
for (clock.m2 = limit->m2.min;
|
|
(clock.m2 < clock.m1 || clock.m1 == 0) &&
|
|
clock.m2 <= limit->m2.max; clock.m2++) {
|
|
for (clock.n = limit->n.min;
|
|
clock.n <= limit->n.max; clock.n++) {
|
|
for (clock.p1 = limit->p1.min;
|
|
clock.p1 <= limit->p1.max;
|
|
clock.p1++) {
|
|
int this_err;
|
|
|
|
clock_funcs->clock(refclk, &clock);
|
|
|
|
if (!clock_funcs->pll_is_valid(crtc,
|
|
limit, &clock))
|
|
continue;
|
|
|
|
this_err = abs(clock.dot - target);
|
|
if (this_err < err) {
|
|
*best_clock = clock;
|
|
err = this_err;
|
|
}
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
return err != target;
|
|
}
|