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![Linus Torvalds](/assets/img/avatar_default.png)
Pull drm updates from Dave Airlie: "This is the main drm pull request for v4.2. I've one other new driver from freescale on my radar, it's been posted and reviewed, I'd just like to get someone to give it a last look, so maybe I'll send it or maybe I'll leave it. There is no major nouveau changes in here, Ben was working on something big, and we agreed it was a bit late, there wasn't anything else he considered urgent to merge. There might be another msm pull for some bits that are waiting on arm-soc, I'll see how we time it. This touches some "of" stuff, acks are in place except for the fixes to the build in various configs,t hat I just applied. Summary: New drivers: - virtio-gpu: KMS only pieces of driver for virtio-gpu in qemu. This is just the first part of this driver, enough to run unaccelerated userspace on. As qemu merges more we'll start adding the 3D features for the virgl 3d work. - amdgpu: a new driver from AMD to driver their newer GPUs. (VI+) It contains a new cleaner userspace API, and is a clean break from radeon moving forward, that AMD are going to concentrate on. It also contains a set of register headers auto generated from AMD internal database. core: - atomic modesetting API completed, enabled by default now. - Add support for mode_id blob to atomic ioctl to complete interface. - bunch of Displayport MST fixes - lots of misc fixes. panel: - new simple panels - fix some long-standing build issues with bridge drivers radeon: - VCE1 support - add a GPU reset counter for userspace - lots of fixes. amdkfd: - H/W debugger support module - static user-mode queues - support killing all the waves when a process terminates - use standard DECLARE_BITMAP i915: - Add Broxton support - S3, rotation support for Skylake - RPS booting tuning - CPT modeset sequence fixes - ns2501 dither support - enable cmd parser on haswell - cdclk handling fixes - gen8 dynamic pte allocation - lots of atomic conversion work exynos: - Add atomic modesetting support - Add iommu support - Consolidate drm driver initialization - and MIC, DECON and MIPI-DSI support for exynos5433 omapdrm: - atomic modesetting support (fixes lots of things in rewrite) tegra: - DP aux transaction fixes - iommu support fix msm: - adreno a306 support - various dsi bits - various 64-bit fixes - NV12MT support rcar-du: - atomic and misc fixes sti: - fix HDMI timing complaince tilcdc: - use drm component API to access tda998x driver - fix module unloading qxl: - stability fixes" * 'drm-next' of git://people.freedesktop.org/~airlied/linux: (872 commits) drm/nouveau: Pause between setting gpu to D3hot and cutting the power drm/dp/mst: close deadlock in connector destruction. drm: Always enable atomic API drm/vgem: Set unique to "vgem" of: fix a build error to of_graph_get_endpoint_by_regs function drm/dp/mst: take lock around looking up the branch device on hpd irq drm/dp/mst: make sure mst_primary mstb is valid in work function of: add EXPORT_SYMBOL for of_graph_get_endpoint_by_regs ARM: dts: rename the clock of MIPI DSI 'pll_clk' to 'sclk_mipi' drm/atomic: Don't set crtc_state->enable manually drm/exynos: dsi: do not set TE GPIO direction by input drm/exynos: dsi: add support for MIC driver as a bridge drm/exynos: dsi: add support for Exynos5433 drm/exynos: dsi: make use of array for clock access drm/exynos: dsi: make use of driver data for static values drm/exynos: dsi: add macros for register access drm/exynos: dsi: rename pll_clk to sclk_clk drm/exynos: mic: add MIC driver of: add helper for getting endpoint node of specific identifiers drm/exynos: add Exynos5433 decon driver ...
733 lines
18 KiB
C
733 lines
18 KiB
C
/*
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* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
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* Copyright © 2006-2008,2010 Intel Corporation
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* Jesse Barnes <jesse.barnes@intel.com>
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*
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* Authors:
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* Eric Anholt <eric@anholt.net>
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* Chris Wilson <chris@chris-wilson.co.uk>
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*/
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#include <linux/i2c.h>
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#include <linux/i2c-algo-bit.h>
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#include <linux/export.h>
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include <drm/i915_drm.h>
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#include "i915_drv.h"
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struct gmbus_pin {
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const char *name;
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int reg;
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};
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/* Map gmbus pin pairs to names and registers. */
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static const struct gmbus_pin gmbus_pins[] = {
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[GMBUS_PIN_SSC] = { "ssc", GPIOB },
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[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
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[GMBUS_PIN_PANEL] = { "panel", GPIOC },
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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};
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static const struct gmbus_pin gmbus_pins_bdw[] = {
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[GMBUS_PIN_VGADDC] = { "vga", GPIOA },
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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};
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static const struct gmbus_pin gmbus_pins_skl[] = {
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[GMBUS_PIN_DPC] = { "dpc", GPIOD },
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[GMBUS_PIN_DPB] = { "dpb", GPIOE },
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[GMBUS_PIN_DPD] = { "dpd", GPIOF },
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};
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static const struct gmbus_pin gmbus_pins_bxt[] = {
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[GMBUS_PIN_1_BXT] = { "dpb", PCH_GPIOB },
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[GMBUS_PIN_2_BXT] = { "dpc", PCH_GPIOC },
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[GMBUS_PIN_3_BXT] = { "misc", PCH_GPIOD },
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};
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/* pin is expected to be valid */
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static const struct gmbus_pin *get_gmbus_pin(struct drm_i915_private *dev_priv,
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unsigned int pin)
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{
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if (IS_BROXTON(dev_priv))
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return &gmbus_pins_bxt[pin];
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else if (IS_SKYLAKE(dev_priv))
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return &gmbus_pins_skl[pin];
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else if (IS_BROADWELL(dev_priv))
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return &gmbus_pins_bdw[pin];
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else
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return &gmbus_pins[pin];
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}
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bool intel_gmbus_is_valid_pin(struct drm_i915_private *dev_priv,
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unsigned int pin)
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{
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unsigned int size;
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if (IS_BROXTON(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_bxt);
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else if (IS_SKYLAKE(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_skl);
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else if (IS_BROADWELL(dev_priv))
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size = ARRAY_SIZE(gmbus_pins_bdw);
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else
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size = ARRAY_SIZE(gmbus_pins);
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return pin < size && get_gmbus_pin(dev_priv, pin)->reg;
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}
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/* Intel GPIO access functions */
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#define I2C_RISEFALL_TIME 10
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static inline struct intel_gmbus *
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to_intel_gmbus(struct i2c_adapter *i2c)
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{
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return container_of(i2c, struct intel_gmbus, adapter);
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}
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void
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intel_i2c_reset(struct drm_device *dev)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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I915_WRITE(dev_priv->gpio_mmio_base + GMBUS0, 0);
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I915_WRITE(dev_priv->gpio_mmio_base + GMBUS4, 0);
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}
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static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
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{
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u32 val;
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/* When using bit bashing for I2C, this bit needs to be set to 1 */
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if (!IS_PINEVIEW(dev_priv->dev))
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return;
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val = I915_READ(DSPCLK_GATE_D);
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if (enable)
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val |= DPCUNIT_CLOCK_GATE_DISABLE;
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else
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val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
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I915_WRITE(DSPCLK_GATE_D, val);
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}
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static u32 get_reserved(struct intel_gmbus *bus)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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struct drm_device *dev = dev_priv->dev;
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u32 reserved = 0;
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/* On most chips, these bits must be preserved in software. */
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if (!IS_I830(dev) && !IS_845G(dev))
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reserved = I915_READ_NOTRACE(bus->gpio_reg) &
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(GPIO_DATA_PULLUP_DISABLE |
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GPIO_CLOCK_PULLUP_DISABLE);
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return reserved;
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}
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static int get_clock(void *data)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
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return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
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}
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static int get_data(void *data)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
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return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
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}
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static void set_clock(void *data, int state_high)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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u32 clock_bits;
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if (state_high)
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clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
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else
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clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
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GPIO_CLOCK_VAL_MASK;
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
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POSTING_READ(bus->gpio_reg);
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}
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static void set_data(void *data, int state_high)
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{
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struct intel_gmbus *bus = data;
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struct drm_i915_private *dev_priv = bus->dev_priv;
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u32 reserved = get_reserved(bus);
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u32 data_bits;
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if (state_high)
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data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
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else
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data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
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GPIO_DATA_VAL_MASK;
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I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
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POSTING_READ(bus->gpio_reg);
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}
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static int
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intel_gpio_pre_xfer(struct i2c_adapter *adapter)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_i915_private *dev_priv = bus->dev_priv;
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intel_i2c_reset(dev_priv->dev);
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intel_i2c_quirk_set(dev_priv, true);
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set_data(bus, 1);
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set_clock(bus, 1);
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udelay(I2C_RISEFALL_TIME);
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return 0;
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}
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static void
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intel_gpio_post_xfer(struct i2c_adapter *adapter)
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{
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struct intel_gmbus *bus = container_of(adapter,
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struct intel_gmbus,
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adapter);
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struct drm_i915_private *dev_priv = bus->dev_priv;
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set_data(bus, 1);
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set_clock(bus, 1);
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intel_i2c_quirk_set(dev_priv, false);
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}
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static void
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intel_gpio_setup(struct intel_gmbus *bus, unsigned int pin)
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{
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struct drm_i915_private *dev_priv = bus->dev_priv;
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struct i2c_algo_bit_data *algo;
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algo = &bus->bit_algo;
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bus->gpio_reg = dev_priv->gpio_mmio_base +
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get_gmbus_pin(dev_priv, pin)->reg;
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bus->adapter.algo_data = algo;
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algo->setsda = set_data;
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algo->setscl = set_clock;
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algo->getsda = get_data;
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algo->getscl = get_clock;
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algo->pre_xfer = intel_gpio_pre_xfer;
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algo->post_xfer = intel_gpio_post_xfer;
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algo->udelay = I2C_RISEFALL_TIME;
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algo->timeout = usecs_to_jiffies(2200);
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algo->data = bus;
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}
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static int
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gmbus_wait_hw_status(struct drm_i915_private *dev_priv,
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u32 gmbus2_status,
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u32 gmbus4_irq_en)
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{
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int i;
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int reg_offset = dev_priv->gpio_mmio_base;
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u32 gmbus2 = 0;
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DEFINE_WAIT(wait);
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if (!HAS_GMBUS_IRQ(dev_priv->dev))
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gmbus4_irq_en = 0;
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/* Important: The hw handles only the first bit, so set only one! Since
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* we also need to check for NAKs besides the hw ready/idle signal, we
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* need to wake up periodically and check that ourselves. */
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I915_WRITE(GMBUS4 + reg_offset, gmbus4_irq_en);
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for (i = 0; i < msecs_to_jiffies_timeout(50); i++) {
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prepare_to_wait(&dev_priv->gmbus_wait_queue, &wait,
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TASK_UNINTERRUPTIBLE);
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gmbus2 = I915_READ_NOTRACE(GMBUS2 + reg_offset);
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if (gmbus2 & (GMBUS_SATOER | gmbus2_status))
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break;
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schedule_timeout(1);
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}
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finish_wait(&dev_priv->gmbus_wait_queue, &wait);
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I915_WRITE(GMBUS4 + reg_offset, 0);
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if (gmbus2 & GMBUS_SATOER)
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return -ENXIO;
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if (gmbus2 & gmbus2_status)
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return 0;
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return -ETIMEDOUT;
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}
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static int
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gmbus_wait_idle(struct drm_i915_private *dev_priv)
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{
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int ret;
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int reg_offset = dev_priv->gpio_mmio_base;
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#define C ((I915_READ_NOTRACE(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0)
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if (!HAS_GMBUS_IRQ(dev_priv->dev))
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return wait_for(C, 10);
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/* Important: The hw handles only the first bit, so set only one! */
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I915_WRITE(GMBUS4 + reg_offset, GMBUS_IDLE_EN);
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ret = wait_event_timeout(dev_priv->gmbus_wait_queue, C,
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msecs_to_jiffies_timeout(10));
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I915_WRITE(GMBUS4 + reg_offset, 0);
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if (ret)
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return 0;
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else
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return -ETIMEDOUT;
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#undef C
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}
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static int
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gmbus_xfer_read_chunk(struct drm_i915_private *dev_priv,
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unsigned short addr, u8 *buf, unsigned int len,
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u32 gmbus1_index)
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{
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int reg_offset = dev_priv->gpio_mmio_base;
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I915_WRITE(GMBUS1 + reg_offset,
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gmbus1_index |
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GMBUS_CYCLE_WAIT |
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(len << GMBUS_BYTE_COUNT_SHIFT) |
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(addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_READ | GMBUS_SW_RDY);
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while (len) {
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int ret;
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u32 val, loop = 0;
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ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
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GMBUS_HW_RDY_EN);
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if (ret)
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return ret;
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val = I915_READ(GMBUS3 + reg_offset);
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do {
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*buf++ = val & 0xff;
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val >>= 8;
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} while (--len && ++loop < 4);
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}
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return 0;
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}
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static int
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gmbus_xfer_read(struct drm_i915_private *dev_priv, struct i2c_msg *msg,
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u32 gmbus1_index)
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{
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u8 *buf = msg->buf;
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unsigned int rx_size = msg->len;
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unsigned int len;
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int ret;
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do {
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len = min(rx_size, GMBUS_BYTE_COUNT_MAX);
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ret = gmbus_xfer_read_chunk(dev_priv, msg->addr,
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buf, len, gmbus1_index);
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if (ret)
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return ret;
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rx_size -= len;
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buf += len;
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} while (rx_size != 0);
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return 0;
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}
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static int
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gmbus_xfer_write_chunk(struct drm_i915_private *dev_priv,
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unsigned short addr, u8 *buf, unsigned int len)
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{
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int reg_offset = dev_priv->gpio_mmio_base;
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unsigned int chunk_size = len;
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u32 val, loop;
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val = loop = 0;
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while (len && loop < 4) {
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val |= *buf++ << (8 * loop++);
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len -= 1;
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}
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I915_WRITE(GMBUS3 + reg_offset, val);
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I915_WRITE(GMBUS1 + reg_offset,
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GMBUS_CYCLE_WAIT |
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(chunk_size << GMBUS_BYTE_COUNT_SHIFT) |
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(addr << GMBUS_SLAVE_ADDR_SHIFT) |
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GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
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while (len) {
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int ret;
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val = loop = 0;
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do {
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val |= *buf++ << (8 * loop);
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} while (--len && ++loop < 4);
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I915_WRITE(GMBUS3 + reg_offset, val);
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ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_RDY,
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GMBUS_HW_RDY_EN);
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if (ret)
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return ret;
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}
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return 0;
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}
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|
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static int
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gmbus_xfer_write(struct drm_i915_private *dev_priv, struct i2c_msg *msg)
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{
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u8 *buf = msg->buf;
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unsigned int tx_size = msg->len;
|
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unsigned int len;
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int ret;
|
|
|
|
do {
|
|
len = min(tx_size, GMBUS_BYTE_COUNT_MAX);
|
|
|
|
ret = gmbus_xfer_write_chunk(dev_priv, msg->addr, buf, len);
|
|
if (ret)
|
|
return ret;
|
|
|
|
buf += len;
|
|
tx_size -= len;
|
|
} while (tx_size != 0);
|
|
|
|
return 0;
|
|
}
|
|
|
|
/*
|
|
* The gmbus controller can combine a 1 or 2 byte write with a read that
|
|
* immediately follows it by using an "INDEX" cycle.
|
|
*/
|
|
static bool
|
|
gmbus_is_index_read(struct i2c_msg *msgs, int i, int num)
|
|
{
|
|
return (i + 1 < num &&
|
|
!(msgs[i].flags & I2C_M_RD) && msgs[i].len <= 2 &&
|
|
(msgs[i + 1].flags & I2C_M_RD));
|
|
}
|
|
|
|
static int
|
|
gmbus_xfer_index_read(struct drm_i915_private *dev_priv, struct i2c_msg *msgs)
|
|
{
|
|
int reg_offset = dev_priv->gpio_mmio_base;
|
|
u32 gmbus1_index = 0;
|
|
u32 gmbus5 = 0;
|
|
int ret;
|
|
|
|
if (msgs[0].len == 2)
|
|
gmbus5 = GMBUS_2BYTE_INDEX_EN |
|
|
msgs[0].buf[1] | (msgs[0].buf[0] << 8);
|
|
if (msgs[0].len == 1)
|
|
gmbus1_index = GMBUS_CYCLE_INDEX |
|
|
(msgs[0].buf[0] << GMBUS_SLAVE_INDEX_SHIFT);
|
|
|
|
/* GMBUS5 holds 16-bit index */
|
|
if (gmbus5)
|
|
I915_WRITE(GMBUS5 + reg_offset, gmbus5);
|
|
|
|
ret = gmbus_xfer_read(dev_priv, &msgs[1], gmbus1_index);
|
|
|
|
/* Clear GMBUS5 after each index transfer */
|
|
if (gmbus5)
|
|
I915_WRITE(GMBUS5 + reg_offset, 0);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int
|
|
gmbus_xfer(struct i2c_adapter *adapter,
|
|
struct i2c_msg *msgs,
|
|
int num)
|
|
{
|
|
struct intel_gmbus *bus = container_of(adapter,
|
|
struct intel_gmbus,
|
|
adapter);
|
|
struct drm_i915_private *dev_priv = bus->dev_priv;
|
|
int i = 0, inc, try = 0, reg_offset;
|
|
int ret = 0;
|
|
|
|
intel_aux_display_runtime_get(dev_priv);
|
|
mutex_lock(&dev_priv->gmbus_mutex);
|
|
|
|
if (bus->force_bit) {
|
|
ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
|
|
goto out;
|
|
}
|
|
|
|
reg_offset = dev_priv->gpio_mmio_base;
|
|
|
|
retry:
|
|
I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
|
|
|
|
for (; i < num; i += inc) {
|
|
inc = 1;
|
|
if (gmbus_is_index_read(msgs, i, num)) {
|
|
ret = gmbus_xfer_index_read(dev_priv, &msgs[i]);
|
|
inc = 2; /* an index read is two msgs */
|
|
} else if (msgs[i].flags & I2C_M_RD) {
|
|
ret = gmbus_xfer_read(dev_priv, &msgs[i], 0);
|
|
} else {
|
|
ret = gmbus_xfer_write(dev_priv, &msgs[i]);
|
|
}
|
|
|
|
if (ret == -ETIMEDOUT)
|
|
goto timeout;
|
|
if (ret == -ENXIO)
|
|
goto clear_err;
|
|
|
|
ret = gmbus_wait_hw_status(dev_priv, GMBUS_HW_WAIT_PHASE,
|
|
GMBUS_HW_WAIT_EN);
|
|
if (ret == -ENXIO)
|
|
goto clear_err;
|
|
if (ret)
|
|
goto timeout;
|
|
}
|
|
|
|
/* Generate a STOP condition on the bus. Note that gmbus can't generata
|
|
* a STOP on the very first cycle. To simplify the code we
|
|
* unconditionally generate the STOP condition with an additional gmbus
|
|
* cycle. */
|
|
I915_WRITE(GMBUS1 + reg_offset, GMBUS_CYCLE_STOP | GMBUS_SW_RDY);
|
|
|
|
/* Mark the GMBUS interface as disabled after waiting for idle.
|
|
* We will re-enable it at the start of the next xfer,
|
|
* till then let it sleep.
|
|
*/
|
|
if (gmbus_wait_idle(dev_priv)) {
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out waiting for idle\n",
|
|
adapter->name);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
I915_WRITE(GMBUS0 + reg_offset, 0);
|
|
ret = ret ?: i;
|
|
goto out;
|
|
|
|
clear_err:
|
|
/*
|
|
* Wait for bus to IDLE before clearing NAK.
|
|
* If we clear the NAK while bus is still active, then it will stay
|
|
* active and the next transaction may fail.
|
|
*
|
|
* If no ACK is received during the address phase of a transaction, the
|
|
* adapter must report -ENXIO. It is not clear what to return if no ACK
|
|
* is received at other times. But we have to be careful to not return
|
|
* spurious -ENXIO because that will prevent i2c and drm edid functions
|
|
* from retrying. So return -ENXIO only when gmbus properly quiescents -
|
|
* timing out seems to happen when there _is_ a ddc chip present, but
|
|
* it's slow responding and only answers on the 2nd retry.
|
|
*/
|
|
ret = -ENXIO;
|
|
if (gmbus_wait_idle(dev_priv)) {
|
|
DRM_DEBUG_KMS("GMBUS [%s] timed out after NAK\n",
|
|
adapter->name);
|
|
ret = -ETIMEDOUT;
|
|
}
|
|
|
|
/* Toggle the Software Clear Interrupt bit. This has the effect
|
|
* of resetting the GMBUS controller and so clearing the
|
|
* BUS_ERROR raised by the slave's NAK.
|
|
*/
|
|
I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
|
|
I915_WRITE(GMBUS1 + reg_offset, 0);
|
|
I915_WRITE(GMBUS0 + reg_offset, 0);
|
|
|
|
DRM_DEBUG_KMS("GMBUS [%s] NAK for addr: %04x %c(%d)\n",
|
|
adapter->name, msgs[i].addr,
|
|
(msgs[i].flags & I2C_M_RD) ? 'r' : 'w', msgs[i].len);
|
|
|
|
/*
|
|
* Passive adapters sometimes NAK the first probe. Retry the first
|
|
* message once on -ENXIO for GMBUS transfers; the bit banging algorithm
|
|
* has retries internally. See also the retry loop in
|
|
* drm_do_probe_ddc_edid, which bails out on the first -ENXIO.
|
|
*/
|
|
if (ret == -ENXIO && i == 0 && try++ == 0) {
|
|
DRM_DEBUG_KMS("GMBUS [%s] NAK on first message, retry\n",
|
|
adapter->name);
|
|
goto retry;
|
|
}
|
|
|
|
goto out;
|
|
|
|
timeout:
|
|
DRM_INFO("GMBUS [%s] timed out, falling back to bit banging on pin %d\n",
|
|
bus->adapter.name, bus->reg0 & 0xff);
|
|
I915_WRITE(GMBUS0 + reg_offset, 0);
|
|
|
|
/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
|
|
bus->force_bit = 1;
|
|
ret = i2c_bit_algo.master_xfer(adapter, msgs, num);
|
|
|
|
out:
|
|
mutex_unlock(&dev_priv->gmbus_mutex);
|
|
intel_aux_display_runtime_put(dev_priv);
|
|
return ret;
|
|
}
|
|
|
|
static u32 gmbus_func(struct i2c_adapter *adapter)
|
|
{
|
|
return i2c_bit_algo.functionality(adapter) &
|
|
(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
|
|
/* I2C_FUNC_10BIT_ADDR | */
|
|
I2C_FUNC_SMBUS_READ_BLOCK_DATA |
|
|
I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
|
|
}
|
|
|
|
static const struct i2c_algorithm gmbus_algorithm = {
|
|
.master_xfer = gmbus_xfer,
|
|
.functionality = gmbus_func
|
|
};
|
|
|
|
/**
|
|
* intel_gmbus_setup - instantiate all Intel i2c GMBuses
|
|
* @dev: DRM device
|
|
*/
|
|
int intel_setup_gmbus(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_gmbus *bus;
|
|
unsigned int pin;
|
|
int ret;
|
|
|
|
if (HAS_PCH_NOP(dev))
|
|
return 0;
|
|
else if (HAS_PCH_SPLIT(dev))
|
|
dev_priv->gpio_mmio_base = PCH_GPIOA - GPIOA;
|
|
else if (IS_VALLEYVIEW(dev))
|
|
dev_priv->gpio_mmio_base = VLV_DISPLAY_BASE;
|
|
else
|
|
dev_priv->gpio_mmio_base = 0;
|
|
|
|
mutex_init(&dev_priv->gmbus_mutex);
|
|
init_waitqueue_head(&dev_priv->gmbus_wait_queue);
|
|
|
|
for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
|
|
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
|
|
continue;
|
|
|
|
bus = &dev_priv->gmbus[pin];
|
|
|
|
bus->adapter.owner = THIS_MODULE;
|
|
bus->adapter.class = I2C_CLASS_DDC;
|
|
snprintf(bus->adapter.name,
|
|
sizeof(bus->adapter.name),
|
|
"i915 gmbus %s",
|
|
get_gmbus_pin(dev_priv, pin)->name);
|
|
|
|
bus->adapter.dev.parent = &dev->pdev->dev;
|
|
bus->dev_priv = dev_priv;
|
|
|
|
bus->adapter.algo = &gmbus_algorithm;
|
|
|
|
/* By default use a conservative clock rate */
|
|
bus->reg0 = pin | GMBUS_RATE_100KHZ;
|
|
|
|
/* gmbus seems to be broken on i830 */
|
|
if (IS_I830(dev))
|
|
bus->force_bit = 1;
|
|
|
|
intel_gpio_setup(bus, pin);
|
|
|
|
ret = i2c_add_adapter(&bus->adapter);
|
|
if (ret)
|
|
goto err;
|
|
}
|
|
|
|
intel_i2c_reset(dev_priv->dev);
|
|
|
|
return 0;
|
|
|
|
err:
|
|
while (--pin) {
|
|
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
|
|
continue;
|
|
|
|
bus = &dev_priv->gmbus[pin];
|
|
i2c_del_adapter(&bus->adapter);
|
|
}
|
|
return ret;
|
|
}
|
|
|
|
struct i2c_adapter *intel_gmbus_get_adapter(struct drm_i915_private *dev_priv,
|
|
unsigned int pin)
|
|
{
|
|
if (WARN_ON(!intel_gmbus_is_valid_pin(dev_priv, pin)))
|
|
return NULL;
|
|
|
|
return &dev_priv->gmbus[pin].adapter;
|
|
}
|
|
|
|
void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
|
|
{
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
|
|
bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
|
|
}
|
|
|
|
void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
|
|
{
|
|
struct intel_gmbus *bus = to_intel_gmbus(adapter);
|
|
|
|
bus->force_bit += force_bit ? 1 : -1;
|
|
DRM_DEBUG_KMS("%sabling bit-banging on %s. force bit now %d\n",
|
|
force_bit ? "en" : "dis", adapter->name,
|
|
bus->force_bit);
|
|
}
|
|
|
|
void intel_teardown_gmbus(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_gmbus *bus;
|
|
unsigned int pin;
|
|
|
|
for (pin = 0; pin < ARRAY_SIZE(dev_priv->gmbus); pin++) {
|
|
if (!intel_gmbus_is_valid_pin(dev_priv, pin))
|
|
continue;
|
|
|
|
bus = &dev_priv->gmbus[pin];
|
|
i2c_del_adapter(&bus->adapter);
|
|
}
|
|
}
|