mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-27 03:10:12 +00:00
3bbaba0cea
This change adds the programming of the MOCS registers to the gen 9+ platforms. The set of MOCS configuration entries introduced by this patch is intended to be minimal but sufficient to cover the needs of current userspace - i.e. a good set of defaults. It is expected to be extended in the future to provide further default values or to allow userspace to redefine its private MOCS tables based on its demand for additional caching configurations. In this setup, userspace should only utilize the first N entries, higher entries are reserved for future use. It creates a fixed register set that is programmed across the different engines so that all engines have the same table. This is done as the main RCS context only holds the registers for itself and the shared L3 values. By trying to keep the registers consistent across the different engines it should make the programming for the registers consistent. v2: -'static const' for private data structures and style changes.(Matt Turner) v3: - Make the tables "slightly" more readable. (Damien Lespiau) - Updated tables fix performance regression. v4: - Code formatting. (Chris Wilson) - re-privatised mocs code. (Daniel Vetter) v5: - Changed the name of a function. (Chris Wilson) v6: - re-based - Added Mesa table entry (skylake & broxton) (Francisco Jerez) - Tidied up the readability defines (Francisco Jerez) - NUMBER of entries defines wrong. (Jim Bish) - Added comments to clear up the meaning of the tables (Jim Bish) Signed-off-by: Peter Antoine <peter.antoine@intel.com> v7 (Francisco Jerez): - Don't write L3-specific MOCS_ESC/SCC values into the e/LLC control tables. Prefix L3-specific defines consistently with L3_ and e/LLC-specific defines with LE_ to avoid this kind of confusion in the future. - Change L3CC WT define back to RESERVED (matches my hardware documentation and the original patch, probably a misunderstanding of my own previous comment). - Drop Android tables, define new minimal tables more suitable for the open source stack. - Add comment that the MOCS tables are part of the kernel ABI. - Move intel_logical_ring_begin() and _advance() calls one level down (Chris Wilson). - Minor formatting and style fixes. v8 (Francisco Jerez): - Add table size sanity check to emit_mocs_control/l3cc_table() (Chris Wilson). - Add comment about undefined entries being implicitly set to uncached for forwards compatibility. v9 (Francisco Jerez): - Minor style fixes. Signed-off-by: Francisco Jerez <currojerez@riseup.net> Acked-by: Damien Lespiau <damien.lespiau@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
89 lines
3.6 KiB
C
89 lines
3.6 KiB
C
/*
|
|
* Copyright © 2014 Intel Corporation
|
|
*
|
|
* Permission is hereby granted, free of charge, to any person obtaining a
|
|
* copy of this software and associated documentation files (the "Software"),
|
|
* to deal in the Software without restriction, including without limitation
|
|
* the rights to use, copy, modify, merge, publish, distribute, sublicense,
|
|
* and/or sell copies of the Software, and to permit persons to whom the
|
|
* Software is furnished to do so, subject to the following conditions:
|
|
*
|
|
* The above copyright notice and this permission notice (including the next
|
|
* paragraph) shall be included in all copies or substantial portions of the
|
|
* Software.
|
|
*
|
|
* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
|
|
* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
|
|
* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
|
|
* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
|
|
* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
|
|
* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
|
|
* DEALINGS IN THE SOFTWARE.
|
|
*/
|
|
|
|
#ifndef _INTEL_LRC_H_
|
|
#define _INTEL_LRC_H_
|
|
|
|
#define GEN8_LR_CONTEXT_ALIGN 4096
|
|
|
|
/* Execlists regs */
|
|
#define RING_ELSP(ring) ((ring)->mmio_base+0x230)
|
|
#define RING_EXECLIST_STATUS(ring) ((ring)->mmio_base+0x234)
|
|
#define RING_CONTEXT_CONTROL(ring) ((ring)->mmio_base+0x244)
|
|
#define CTX_CTRL_INHIBIT_SYN_CTX_SWITCH (1 << 3)
|
|
#define CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT (1 << 0)
|
|
#define CTX_CTRL_RS_CTX_ENABLE (1 << 1)
|
|
#define RING_CONTEXT_STATUS_BUF(ring) ((ring)->mmio_base+0x370)
|
|
#define RING_CONTEXT_STATUS_PTR(ring) ((ring)->mmio_base+0x3a0)
|
|
|
|
/* Logical Rings */
|
|
int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request);
|
|
int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request);
|
|
void intel_logical_ring_stop(struct intel_engine_cs *ring);
|
|
void intel_logical_ring_cleanup(struct intel_engine_cs *ring);
|
|
int intel_logical_rings_init(struct drm_device *dev);
|
|
int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords);
|
|
|
|
int logical_ring_flush_all_caches(struct drm_i915_gem_request *req);
|
|
/**
|
|
* intel_logical_ring_advance() - advance the ringbuffer tail
|
|
* @ringbuf: Ringbuffer to advance.
|
|
*
|
|
* The tail is only updated in our logical ringbuffer struct.
|
|
*/
|
|
static inline void intel_logical_ring_advance(struct intel_ringbuffer *ringbuf)
|
|
{
|
|
ringbuf->tail &= ringbuf->size - 1;
|
|
}
|
|
/**
|
|
* intel_logical_ring_emit() - write a DWORD to the ringbuffer.
|
|
* @ringbuf: Ringbuffer to write to.
|
|
* @data: DWORD to write.
|
|
*/
|
|
static inline void intel_logical_ring_emit(struct intel_ringbuffer *ringbuf,
|
|
u32 data)
|
|
{
|
|
iowrite32(data, ringbuf->virtual_start + ringbuf->tail);
|
|
ringbuf->tail += 4;
|
|
}
|
|
|
|
/* Logical Ring Contexts */
|
|
void intel_lr_context_free(struct intel_context *ctx);
|
|
int intel_lr_context_deferred_create(struct intel_context *ctx,
|
|
struct intel_engine_cs *ring);
|
|
void intel_lr_context_unpin(struct drm_i915_gem_request *req);
|
|
void intel_lr_context_reset(struct drm_device *dev,
|
|
struct intel_context *ctx);
|
|
|
|
/* Execlists */
|
|
int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists);
|
|
struct i915_execbuffer_params;
|
|
int intel_execlists_submission(struct i915_execbuffer_params *params,
|
|
struct drm_i915_gem_execbuffer2 *args,
|
|
struct list_head *vmas);
|
|
u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj);
|
|
|
|
void intel_lrc_irq_handler(struct intel_engine_cs *ring);
|
|
void intel_execlists_retire_requests(struct intel_engine_cs *ring);
|
|
|
|
#endif /* _INTEL_LRC_H_ */
|