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![Rodrigo Vivi](/assets/img/avatar_default.png)
Since active function on VLV immediately activate PSR let's give more time for idleness. Different from core platforms where we have idle_frames count. Also kms_psr_sink_crc now is automated and always get this: [drm:intel_enable_pipe] enabling pipe A [drm:intel_edp_backlight_on] [drm:intel_panel_enable_backlight] pipe [drm:intel_panel_enable_backlight] pipe A [drm:intel_panel_actually_set_backlight] set backlight PWM = 7812 PSR gets enabled somewhere here after backlight. [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x0 [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp PSR gets flushed around here by intel_atomic_commit [drm:vlv_pipe_set_fifo_size] Pipe A FIFO split 511 / 511 / 511 [drm:vlv_update_wm] Setting FIFO watermarks - A: plane=391, cursor=63, sp [drm:intel_set_memory_cxsr] memory self-refresh is enabled [drm:intel_connector_check_state] [CONNECTOR:39:eDP-1] [drm:check_encoder_state] [ENCODER:30:DAC-30] [drm:check_encoder_state] [ENCODER:31:TMDS-31] [drm:check_encoder_state] [ENCODER:36:TMDS-36] [drm:check_encoder_state] [ENCODER:38:TMDS-38] [drm:check_crtc_state] [CRTC:21] [drm:check_crtc_state] [CRTC:26] [drm:intel_psr_activate [i915]] *ERROR* PSR Active [drm:intel_get_hpd_pins] hotplug event received, stat 0x00000000, dig 0x [drm:intel_set_cpu_fifo_underrun_reporting [i915]] *ERROR* pipe A underrun [drm:intel_cpu_fifo_underrun_irq_handler [i915]] *ERROR* CPU pipe A FIFO Underrun. It is true that in a product we won't keep disabling and enabling planes so frequently, but for safeness let's stay conservative. It is also true that 500ms is an etternity. But PSR is anyway a power saving feature for idle scenario. So if it is idle feature stays on and 500ms to get it reanabled is not that insane. v2: Rebase over intel_psr.c and fix typo. v3: Revival: Manual tests indicated that this is needed. With a short delay there is a huge risk of getting blank screens when planes are being enabled. v4: Revival 2 with reasonable delay. 1/2 sec instead of 5. VBT is 10 sec but actually time for link training what we aren't doing, but with only 100 sec in some cases kms_psr_sink_crc manual was showing blank screen, so let's use this for now. Also changed comment by a FIXME. v5: Rebase after a long time, remove FIXME and update comment above. v6: msecs_to_jiffies is already on delay. remove duplication. v7: use msecs_to_jiffies on schedule_delayed_work call. Reviewed-by: Durgadoss R <durgadoss.r@intel.com> (v4) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Tested-By: Intel Graphics QA PRTS (Patch Regression Test System Contact: shuang.he@intel.com) Signed-off-by: Rodrigo Vivi <rodrigo.vivi@intel.com> Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
754 lines
24 KiB
C
754 lines
24 KiB
C
/*
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* Copyright © 2014 Intel Corporation
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice (including the next
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* paragraph) shall be included in all copies or substantial portions of the
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* Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
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* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
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* DEALINGS IN THE SOFTWARE.
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*/
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/**
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* DOC: Panel Self Refresh (PSR/SRD)
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*
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* Since Haswell Display controller supports Panel Self-Refresh on display
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* panels witch have a remote frame buffer (RFB) implemented according to PSR
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* spec in eDP1.3. PSR feature allows the display to go to lower standby states
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* when system is idle but display is on as it eliminates display refresh
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* request to DDR memory completely as long as the frame buffer for that
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* display is unchanged.
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*
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* Panel Self Refresh must be supported by both Hardware (source) and
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* Panel (sink).
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*
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* PSR saves power by caching the framebuffer in the panel RFB, which allows us
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* to power down the link and memory controller. For DSI panels the same idea
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* is called "manual mode".
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*
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* The implementation uses the hardware-based PSR support which automatically
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* enters/exits self-refresh mode. The hardware takes care of sending the
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* required DP aux message and could even retrain the link (that part isn't
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* enabled yet though). The hardware also keeps track of any frontbuffer
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* changes to know when to exit self-refresh mode again. Unfortunately that
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* part doesn't work too well, hence why the i915 PSR support uses the
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* software frontbuffer tracking to make sure it doesn't miss a screen
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* update. For this integration intel_psr_invalidate() and intel_psr_flush()
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* get called by the frontbuffer tracking code. Note that because of locking
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* issues the self-refresh re-enable code is done from a work queue, which
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* must be correctly synchronized/cancelled when shutting down the pipe."
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*/
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#include <drm/drmP.h>
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#include "intel_drv.h"
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#include "i915_drv.h"
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static bool is_edp_psr(struct intel_dp *intel_dp)
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{
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return intel_dp->psr_dpcd[0] & DP_PSR_IS_SUPPORTED;
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}
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static bool vlv_is_psr_active_on_pipe(struct drm_device *dev, int pipe)
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{
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t val;
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val = I915_READ(VLV_PSRSTAT(pipe)) &
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VLV_EDP_PSR_CURR_STATE_MASK;
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return (val == VLV_EDP_PSR_ACTIVE_NORFB_UP) ||
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(val == VLV_EDP_PSR_ACTIVE_SF_UPDATE);
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}
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static void intel_psr_write_vsc(struct intel_dp *intel_dp,
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struct edp_vsc_psr *vsc_psr)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct intel_crtc *crtc = to_intel_crtc(dig_port->base.base.crtc);
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u32 ctl_reg = HSW_TVIDEO_DIP_CTL(crtc->config->cpu_transcoder);
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u32 data_reg = HSW_TVIDEO_DIP_VSC_DATA(crtc->config->cpu_transcoder);
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uint32_t *data = (uint32_t *) vsc_psr;
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unsigned int i;
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/* As per BSPec (Pipe Video Data Island Packet), we need to disable
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the video DIP being updated before program video DIP data buffer
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registers for DIP being updated. */
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I915_WRITE(ctl_reg, 0);
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POSTING_READ(ctl_reg);
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for (i = 0; i < VIDEO_DIP_VSC_DATA_SIZE; i += 4) {
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if (i < sizeof(struct edp_vsc_psr))
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I915_WRITE(data_reg + i, *data++);
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else
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I915_WRITE(data_reg + i, 0);
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}
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I915_WRITE(ctl_reg, VIDEO_DIP_ENABLE_VSC_HSW);
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POSTING_READ(ctl_reg);
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}
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static void vlv_psr_setup_vsc(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = intel_dig_port->base.base.crtc;
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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uint32_t val;
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/* VLV auto-generate VSC package as per EDP 1.3 spec, Table 3.10 */
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val = I915_READ(VLV_VSCSDP(pipe));
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val &= ~VLV_EDP_PSR_SDP_FREQ_MASK;
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val |= VLV_EDP_PSR_SDP_FREQ_EVFRAME;
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I915_WRITE(VLV_VSCSDP(pipe), val);
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}
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static void skl_psr_setup_su_vsc(struct intel_dp *intel_dp)
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{
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struct edp_vsc_psr psr_vsc;
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/* Prepare VSC Header for SU as per EDP 1.4 spec, Table 6.11 */
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memset(&psr_vsc, 0, sizeof(psr_vsc));
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psr_vsc.sdp_header.HB0 = 0;
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psr_vsc.sdp_header.HB1 = 0x7;
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psr_vsc.sdp_header.HB2 = 0x3;
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psr_vsc.sdp_header.HB3 = 0xb;
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intel_psr_write_vsc(intel_dp, &psr_vsc);
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}
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static void hsw_psr_setup_vsc(struct intel_dp *intel_dp)
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{
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struct edp_vsc_psr psr_vsc;
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/* Prepare VSC packet as per EDP 1.3 spec, Table 3.10 */
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memset(&psr_vsc, 0, sizeof(psr_vsc));
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psr_vsc.sdp_header.HB0 = 0;
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psr_vsc.sdp_header.HB1 = 0x7;
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psr_vsc.sdp_header.HB2 = 0x2;
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psr_vsc.sdp_header.HB3 = 0x8;
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intel_psr_write_vsc(intel_dp, &psr_vsc);
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}
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static void vlv_psr_enable_sink(struct intel_dp *intel_dp)
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{
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
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DP_PSR_ENABLE | DP_PSR_MAIN_LINK_ACTIVE);
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}
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static void hsw_psr_enable_sink(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t aux_clock_divider;
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uint32_t aux_data_reg, aux_ctl_reg;
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int precharge = 0x3;
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static const uint8_t aux_msg[] = {
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[0] = DP_AUX_NATIVE_WRITE << 4,
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[1] = DP_SET_POWER >> 8,
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[2] = DP_SET_POWER & 0xff,
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[3] = 1 - 1,
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[4] = DP_SET_POWER_D0,
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};
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int i;
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BUILD_BUG_ON(sizeof(aux_msg) > 20);
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aux_clock_divider = intel_dp->get_aux_clock_divider(intel_dp, 0);
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG,
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DP_PSR_ENABLE & ~DP_PSR_MAIN_LINK_ACTIVE);
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/* Enable AUX frame sync at sink */
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if (dev_priv->psr.aux_frame_sync)
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drm_dp_dpcd_writeb(&intel_dp->aux,
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DP_SINK_DEVICE_AUX_FRAME_SYNC_CONF,
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DP_AUX_FRAME_SYNC_ENABLE);
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aux_data_reg = (INTEL_INFO(dev)->gen >= 9) ?
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DPA_AUX_CH_DATA1 : EDP_PSR_AUX_DATA1(dev);
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aux_ctl_reg = (INTEL_INFO(dev)->gen >= 9) ?
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DPA_AUX_CH_CTL : EDP_PSR_AUX_CTL(dev);
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/* Setup AUX registers */
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for (i = 0; i < sizeof(aux_msg); i += 4)
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I915_WRITE(aux_data_reg + i,
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intel_dp_pack_aux(&aux_msg[i], sizeof(aux_msg) - i));
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if (INTEL_INFO(dev)->gen >= 9) {
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uint32_t val;
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val = I915_READ(aux_ctl_reg);
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val &= ~DP_AUX_CH_CTL_TIME_OUT_MASK;
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val |= DP_AUX_CH_CTL_TIME_OUT_1600us;
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val &= ~DP_AUX_CH_CTL_MESSAGE_SIZE_MASK;
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val |= (sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT);
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/* Use hardcoded data values for PSR, frame sync and GTC */
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val &= ~DP_AUX_CH_CTL_PSR_DATA_AUX_REG_SKL;
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val &= ~DP_AUX_CH_CTL_FS_DATA_AUX_REG_SKL;
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val &= ~DP_AUX_CH_CTL_GTC_DATA_AUX_REG_SKL;
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I915_WRITE(aux_ctl_reg, val);
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} else {
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I915_WRITE(aux_ctl_reg,
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DP_AUX_CH_CTL_TIME_OUT_400us |
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(sizeof(aux_msg) << DP_AUX_CH_CTL_MESSAGE_SIZE_SHIFT) |
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(precharge << DP_AUX_CH_CTL_PRECHARGE_2US_SHIFT) |
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(aux_clock_divider << DP_AUX_CH_CTL_BIT_CLOCK_2X_SHIFT));
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}
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drm_dp_dpcd_writeb(&intel_dp->aux, DP_PSR_EN_CFG, DP_PSR_ENABLE);
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}
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static void vlv_psr_enable_source(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dig_port->base.base.crtc;
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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/* Transition from PSR_state 0 to PSR_state 1, i.e. PSR Inactive */
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I915_WRITE(VLV_PSRCTL(pipe),
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VLV_EDP_PSR_MODE_SW_TIMER |
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VLV_EDP_PSR_SRC_TRANSMITTER_STATE |
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VLV_EDP_PSR_ENABLE);
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}
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static void vlv_psr_activate(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dig_port->base.base.crtc;
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enum pipe pipe = to_intel_crtc(crtc)->pipe;
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/* Let's do the transition from PSR_state 1 to PSR_state 2
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* that is PSR transition to active - static frame transmission.
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* Then Hardware is responsible for the transition to PSR_state 3
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* that is PSR active - no Remote Frame Buffer (RFB) update.
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*/
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I915_WRITE(VLV_PSRCTL(pipe), I915_READ(VLV_PSRCTL(pipe)) |
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VLV_EDP_PSR_ACTIVE_ENTRY);
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}
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static void hsw_psr_enable_source(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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uint32_t max_sleep_time = 0x1f;
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/* Lately it was identified that depending on panel idle frame count
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* calculated at HW can be off by 1. So let's use what came
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* from VBT + 1.
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* There are also other cases where panel demands at least 4
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* but VBT is not being set. To cover these 2 cases lets use
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* at least 5 when VBT isn't set to be on the safest side.
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*/
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uint32_t idle_frames = dev_priv->vbt.psr.idle_frames ?
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dev_priv->vbt.psr.idle_frames + 1 : 5;
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uint32_t val = 0x0;
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const uint32_t link_entry_time = EDP_PSR_MIN_LINK_ENTRY_TIME_8_LINES;
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if (intel_dp->psr_dpcd[1] & DP_PSR_NO_TRAIN_ON_EXIT) {
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/* It doesn't mean we shouldn't send TPS patters, so let's
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send the minimal TP1 possible and skip TP2. */
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val |= EDP_PSR_TP1_TIME_100us;
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val |= EDP_PSR_TP2_TP3_TIME_0us;
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val |= EDP_PSR_SKIP_AUX_EXIT;
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/* Sink should be able to train with the 5 or 6 idle patterns */
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idle_frames += 4;
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}
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I915_WRITE(EDP_PSR_CTL(dev), val |
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(IS_BROADWELL(dev) ? 0 : link_entry_time) |
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max_sleep_time << EDP_PSR_MAX_SLEEP_TIME_SHIFT |
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idle_frames << EDP_PSR_IDLE_FRAME_SHIFT |
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EDP_PSR_ENABLE);
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if (dev_priv->psr.psr2_support)
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I915_WRITE(EDP_PSR2_CTL, EDP_PSR2_ENABLE |
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EDP_SU_TRACK_ENABLE | EDP_PSR2_TP2_TIME_100);
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}
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static bool intel_psr_match_conditions(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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struct drm_crtc *crtc = dig_port->base.base.crtc;
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struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
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lockdep_assert_held(&dev_priv->psr.lock);
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WARN_ON(!drm_modeset_is_locked(&dev->mode_config.connection_mutex));
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WARN_ON(!drm_modeset_is_locked(&crtc->mutex));
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dev_priv->psr.source_ok = false;
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if (IS_HASWELL(dev) && dig_port->port != PORT_A) {
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DRM_DEBUG_KMS("HSW ties PSR to DDI A (eDP)\n");
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return false;
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}
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if (!i915.enable_psr) {
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DRM_DEBUG_KMS("PSR disable by flag\n");
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return false;
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}
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if (IS_HASWELL(dev) &&
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I915_READ(HSW_STEREO_3D_CTL(intel_crtc->config->cpu_transcoder)) &
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S3D_ENABLE) {
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DRM_DEBUG_KMS("PSR condition failed: Stereo 3D is Enabled\n");
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return false;
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}
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if (IS_HASWELL(dev) &&
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intel_crtc->config->base.adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) {
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DRM_DEBUG_KMS("PSR condition failed: Interlaced is Enabled\n");
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return false;
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}
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if (!IS_VALLEYVIEW(dev) && ((dev_priv->vbt.psr.full_link) ||
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(dig_port->port != PORT_A))) {
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DRM_DEBUG_KMS("PSR condition failed: Link Standby requested/needed but not supported on this platform\n");
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return false;
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}
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dev_priv->psr.source_ok = true;
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return true;
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}
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static void intel_psr_activate(struct intel_dp *intel_dp)
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{
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struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
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struct drm_device *dev = intel_dig_port->base.base.dev;
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struct drm_i915_private *dev_priv = dev->dev_private;
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WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
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WARN_ON(dev_priv->psr.active);
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lockdep_assert_held(&dev_priv->psr.lock);
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/* Enable/Re-enable PSR on the host */
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if (HAS_DDI(dev))
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/* On HSW+ after we enable PSR on source it will activate it
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* as soon as it match configure idle_frame count. So
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* we just actually enable it here on activation time.
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*/
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hsw_psr_enable_source(intel_dp);
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else
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vlv_psr_activate(intel_dp);
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dev_priv->psr.active = true;
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}
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/**
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* intel_psr_enable - Enable PSR
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* @intel_dp: Intel DP
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*
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* This function can only be called after the pipe is fully trained and enabled.
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*/
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void intel_psr_enable(struct intel_dp *intel_dp)
|
|
{
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_crtc *crtc = to_intel_crtc(intel_dig_port->base.base.crtc);
|
|
|
|
if (!HAS_PSR(dev)) {
|
|
DRM_DEBUG_KMS("PSR not supported on this platform\n");
|
|
return;
|
|
}
|
|
|
|
if (!is_edp_psr(intel_dp)) {
|
|
DRM_DEBUG_KMS("PSR not supported by this panel\n");
|
|
return;
|
|
}
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
if (dev_priv->psr.enabled) {
|
|
DRM_DEBUG_KMS("PSR already in use\n");
|
|
goto unlock;
|
|
}
|
|
|
|
if (!intel_psr_match_conditions(intel_dp))
|
|
goto unlock;
|
|
|
|
dev_priv->psr.busy_frontbuffer_bits = 0;
|
|
|
|
if (HAS_DDI(dev)) {
|
|
hsw_psr_setup_vsc(intel_dp);
|
|
|
|
if (dev_priv->psr.psr2_support) {
|
|
/* PSR2 is restricted to work with panel resolutions upto 3200x2000 */
|
|
if (crtc->config->pipe_src_w > 3200 ||
|
|
crtc->config->pipe_src_h > 2000)
|
|
dev_priv->psr.psr2_support = false;
|
|
else
|
|
skl_psr_setup_su_vsc(intel_dp);
|
|
}
|
|
|
|
/* Avoid continuous PSR exit by masking memup and hpd */
|
|
I915_WRITE(EDP_PSR_DEBUG_CTL(dev), EDP_PSR_DEBUG_MASK_MEMUP |
|
|
EDP_PSR_DEBUG_MASK_HPD);
|
|
|
|
/* Enable PSR on the panel */
|
|
hsw_psr_enable_sink(intel_dp);
|
|
|
|
if (INTEL_INFO(dev)->gen >= 9)
|
|
intel_psr_activate(intel_dp);
|
|
} else {
|
|
vlv_psr_setup_vsc(intel_dp);
|
|
|
|
/* Enable PSR on the panel */
|
|
vlv_psr_enable_sink(intel_dp);
|
|
|
|
/* On HSW+ enable_source also means go to PSR entry/active
|
|
* state as soon as idle_frame achieved and here would be
|
|
* to soon. However on VLV enable_source just enable PSR
|
|
* but let it on inactive state. So we might do this prior
|
|
* to active transition, i.e. here.
|
|
*/
|
|
vlv_psr_enable_source(intel_dp);
|
|
}
|
|
|
|
dev_priv->psr.enabled = intel_dp;
|
|
unlock:
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
static void vlv_psr_disable(struct intel_dp *intel_dp)
|
|
{
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_crtc *intel_crtc =
|
|
to_intel_crtc(intel_dig_port->base.base.crtc);
|
|
uint32_t val;
|
|
|
|
if (dev_priv->psr.active) {
|
|
/* Put VLV PSR back to PSR_state 0 that is PSR Disabled. */
|
|
if (wait_for((I915_READ(VLV_PSRSTAT(intel_crtc->pipe)) &
|
|
VLV_EDP_PSR_IN_TRANS) == 0, 1))
|
|
WARN(1, "PSR transition took longer than expected\n");
|
|
|
|
val = I915_READ(VLV_PSRCTL(intel_crtc->pipe));
|
|
val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
|
|
val &= ~VLV_EDP_PSR_ENABLE;
|
|
val &= ~VLV_EDP_PSR_MODE_MASK;
|
|
I915_WRITE(VLV_PSRCTL(intel_crtc->pipe), val);
|
|
|
|
dev_priv->psr.active = false;
|
|
} else {
|
|
WARN_ON(vlv_is_psr_active_on_pipe(dev, intel_crtc->pipe));
|
|
}
|
|
}
|
|
|
|
static void hsw_psr_disable(struct intel_dp *intel_dp)
|
|
{
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
if (dev_priv->psr.active) {
|
|
I915_WRITE(EDP_PSR_CTL(dev),
|
|
I915_READ(EDP_PSR_CTL(dev)) & ~EDP_PSR_ENABLE);
|
|
|
|
/* Wait till PSR is idle */
|
|
if (_wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev)) &
|
|
EDP_PSR_STATUS_STATE_MASK) == 0, 2000, 10))
|
|
DRM_ERROR("Timed out waiting for PSR Idle State\n");
|
|
|
|
dev_priv->psr.active = false;
|
|
} else {
|
|
WARN_ON(I915_READ(EDP_PSR_CTL(dev)) & EDP_PSR_ENABLE);
|
|
}
|
|
}
|
|
|
|
/**
|
|
* intel_psr_disable - Disable PSR
|
|
* @intel_dp: Intel DP
|
|
*
|
|
* This function needs to be called before disabling pipe.
|
|
*/
|
|
void intel_psr_disable(struct intel_dp *intel_dp)
|
|
{
|
|
struct intel_digital_port *intel_dig_port = dp_to_dig_port(intel_dp);
|
|
struct drm_device *dev = intel_dig_port->base.base.dev;
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
if (!dev_priv->psr.enabled) {
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
return;
|
|
}
|
|
|
|
if (HAS_DDI(dev))
|
|
hsw_psr_disable(intel_dp);
|
|
else
|
|
vlv_psr_disable(intel_dp);
|
|
|
|
dev_priv->psr.enabled = NULL;
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
|
|
cancel_delayed_work_sync(&dev_priv->psr.work);
|
|
}
|
|
|
|
static void intel_psr_work(struct work_struct *work)
|
|
{
|
|
struct drm_i915_private *dev_priv =
|
|
container_of(work, typeof(*dev_priv), psr.work.work);
|
|
struct intel_dp *intel_dp = dev_priv->psr.enabled;
|
|
struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
|
|
enum pipe pipe = to_intel_crtc(crtc)->pipe;
|
|
|
|
/* We have to make sure PSR is ready for re-enable
|
|
* otherwise it keeps disabled until next full enable/disable cycle.
|
|
* PSR might take some time to get fully disabled
|
|
* and be ready for re-enable.
|
|
*/
|
|
if (HAS_DDI(dev_priv->dev)) {
|
|
if (wait_for((I915_READ(EDP_PSR_STATUS_CTL(dev_priv->dev)) &
|
|
EDP_PSR_STATUS_STATE_MASK) == 0, 50)) {
|
|
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
|
|
return;
|
|
}
|
|
} else {
|
|
if (wait_for((I915_READ(VLV_PSRSTAT(pipe)) &
|
|
VLV_EDP_PSR_IN_TRANS) == 0, 1)) {
|
|
DRM_ERROR("Timed out waiting for PSR Idle for re-enable\n");
|
|
return;
|
|
}
|
|
}
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
intel_dp = dev_priv->psr.enabled;
|
|
|
|
if (!intel_dp)
|
|
goto unlock;
|
|
|
|
/*
|
|
* The delayed work can race with an invalidate hence we need to
|
|
* recheck. Since psr_flush first clears this and then reschedules we
|
|
* won't ever miss a flush when bailing out here.
|
|
*/
|
|
if (dev_priv->psr.busy_frontbuffer_bits)
|
|
goto unlock;
|
|
|
|
intel_psr_activate(intel_dp);
|
|
unlock:
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
static void intel_psr_exit(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct intel_dp *intel_dp = dev_priv->psr.enabled;
|
|
struct drm_crtc *crtc = dp_to_dig_port(intel_dp)->base.base.crtc;
|
|
enum pipe pipe = to_intel_crtc(crtc)->pipe;
|
|
u32 val;
|
|
|
|
if (!dev_priv->psr.active)
|
|
return;
|
|
|
|
if (HAS_DDI(dev)) {
|
|
val = I915_READ(EDP_PSR_CTL(dev));
|
|
|
|
WARN_ON(!(val & EDP_PSR_ENABLE));
|
|
|
|
I915_WRITE(EDP_PSR_CTL(dev), val & ~EDP_PSR_ENABLE);
|
|
} else {
|
|
val = I915_READ(VLV_PSRCTL(pipe));
|
|
|
|
/* Here we do the transition from PSR_state 3 to PSR_state 5
|
|
* directly once PSR State 4 that is active with single frame
|
|
* update can be skipped. PSR_state 5 that is PSR exit then
|
|
* Hardware is responsible to transition back to PSR_state 1
|
|
* that is PSR inactive. Same state after
|
|
* vlv_edp_psr_enable_source.
|
|
*/
|
|
val &= ~VLV_EDP_PSR_ACTIVE_ENTRY;
|
|
I915_WRITE(VLV_PSRCTL(pipe), val);
|
|
|
|
/* Send AUX wake up - Spec says after transitioning to PSR
|
|
* active we have to send AUX wake up by writing 01h in DPCD
|
|
* 600h of sink device.
|
|
* XXX: This might slow down the transition, but without this
|
|
* HW doesn't complete the transition to PSR_state 1 and we
|
|
* never get the screen updated.
|
|
*/
|
|
drm_dp_dpcd_writeb(&intel_dp->aux, DP_SET_POWER,
|
|
DP_SET_POWER_D0);
|
|
}
|
|
|
|
dev_priv->psr.active = false;
|
|
}
|
|
|
|
/**
|
|
* intel_psr_single_frame_update - Single Frame Update
|
|
* @dev: DRM device
|
|
* @frontbuffer_bits: frontbuffer plane tracking bits
|
|
*
|
|
* Some platforms support a single frame update feature that is used to
|
|
* send and update only one frame on Remote Frame Buffer.
|
|
* So far it is only implemented for Valleyview and Cherryview because
|
|
* hardware requires this to be done before a page flip.
|
|
*/
|
|
void intel_psr_single_frame_update(struct drm_device *dev,
|
|
unsigned frontbuffer_bits)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_crtc *crtc;
|
|
enum pipe pipe;
|
|
u32 val;
|
|
|
|
/*
|
|
* Single frame update is already supported on BDW+ but it requires
|
|
* many W/A and it isn't really needed.
|
|
*/
|
|
if (!IS_VALLEYVIEW(dev))
|
|
return;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
if (!dev_priv->psr.enabled) {
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
return;
|
|
}
|
|
|
|
crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
|
|
pipe = to_intel_crtc(crtc)->pipe;
|
|
|
|
if (frontbuffer_bits & INTEL_FRONTBUFFER_ALL_MASK(pipe)) {
|
|
val = I915_READ(VLV_PSRCTL(pipe));
|
|
|
|
/*
|
|
* We need to set this bit before writing registers for a flip.
|
|
* This bit will be self-clear when it gets to the PSR active state.
|
|
*/
|
|
I915_WRITE(VLV_PSRCTL(pipe), val | VLV_EDP_PSR_SINGLE_FRAME_UPDATE);
|
|
}
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_invalidate - Invalidade PSR
|
|
* @dev: DRM device
|
|
* @frontbuffer_bits: frontbuffer plane tracking bits
|
|
*
|
|
* Since the hardware frontbuffer tracking has gaps we need to integrate
|
|
* with the software frontbuffer tracking. This function gets called every
|
|
* time frontbuffer rendering starts and a buffer gets dirtied. PSR must be
|
|
* disabled if the frontbuffer mask contains a buffer relevant to PSR.
|
|
*
|
|
* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits."
|
|
*/
|
|
void intel_psr_invalidate(struct drm_device *dev,
|
|
unsigned frontbuffer_bits)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_crtc *crtc;
|
|
enum pipe pipe;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
if (!dev_priv->psr.enabled) {
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
return;
|
|
}
|
|
|
|
crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
|
|
pipe = to_intel_crtc(crtc)->pipe;
|
|
|
|
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
|
|
dev_priv->psr.busy_frontbuffer_bits |= frontbuffer_bits;
|
|
|
|
if (frontbuffer_bits)
|
|
intel_psr_exit(dev);
|
|
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_flush - Flush PSR
|
|
* @dev: DRM device
|
|
* @frontbuffer_bits: frontbuffer plane tracking bits
|
|
* @origin: which operation caused the flush
|
|
*
|
|
* Since the hardware frontbuffer tracking has gaps we need to integrate
|
|
* with the software frontbuffer tracking. This function gets called every
|
|
* time frontbuffer rendering has completed and flushed out to memory. PSR
|
|
* can be enabled again if no other frontbuffer relevant to PSR is dirty.
|
|
*
|
|
* Dirty frontbuffers relevant to PSR are tracked in busy_frontbuffer_bits.
|
|
*/
|
|
void intel_psr_flush(struct drm_device *dev,
|
|
unsigned frontbuffer_bits, enum fb_op_origin origin)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
struct drm_crtc *crtc;
|
|
enum pipe pipe;
|
|
int delay_ms = HAS_DDI(dev) ? 100 : 500;
|
|
|
|
mutex_lock(&dev_priv->psr.lock);
|
|
if (!dev_priv->psr.enabled) {
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
return;
|
|
}
|
|
|
|
crtc = dp_to_dig_port(dev_priv->psr.enabled)->base.base.crtc;
|
|
pipe = to_intel_crtc(crtc)->pipe;
|
|
|
|
frontbuffer_bits &= INTEL_FRONTBUFFER_ALL_MASK(pipe);
|
|
dev_priv->psr.busy_frontbuffer_bits &= ~frontbuffer_bits;
|
|
|
|
if (HAS_DDI(dev)) {
|
|
/*
|
|
* By definition every flush should mean invalidate + flush,
|
|
* however on core platforms let's minimize the
|
|
* disable/re-enable so we can avoid the invalidate when flip
|
|
* originated the flush.
|
|
*/
|
|
if (frontbuffer_bits && origin != ORIGIN_FLIP)
|
|
intel_psr_exit(dev);
|
|
} else {
|
|
/*
|
|
* On Valleyview and Cherryview we don't use hardware tracking
|
|
* so any plane updates or cursor moves don't result in a PSR
|
|
* invalidating. Which means we need to manually fake this in
|
|
* software for all flushes.
|
|
*/
|
|
if (frontbuffer_bits)
|
|
intel_psr_exit(dev);
|
|
}
|
|
|
|
if (!dev_priv->psr.active && !dev_priv->psr.busy_frontbuffer_bits)
|
|
schedule_delayed_work(&dev_priv->psr.work,
|
|
msecs_to_jiffies(delay_ms));
|
|
mutex_unlock(&dev_priv->psr.lock);
|
|
}
|
|
|
|
/**
|
|
* intel_psr_init - Init basic PSR work and mutex.
|
|
* @dev: DRM device
|
|
*
|
|
* This function is called only once at driver load to initialize basic
|
|
* PSR stuff.
|
|
*/
|
|
void intel_psr_init(struct drm_device *dev)
|
|
{
|
|
struct drm_i915_private *dev_priv = dev->dev_private;
|
|
|
|
INIT_DELAYED_WORK(&dev_priv->psr.work, intel_psr_work);
|
|
mutex_init(&dev_priv->psr.lock);
|
|
}
|