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19b4385922
- Ingenic fixes/improvments - other fixes and cleanups -----BEGIN PGP SIGNATURE----- iQJOBAABCAA4FiEEbt46xwy6kEcDOXoUeZbBVTGwZHAFAmDdyJQaHHRzYm9nZW5k QGFscGhhLmZyYW5rZW4uZGUACgkQeZbBVTGwZHBlyRAAhj5dC1EyGsc0cWyzC8ZU Nh45vzMCSxa4mxAelNjuVKdE0h7gLeRa8/sKPV+EcS3ZFcSfZQeIHEbH9Na3EDS7 KtUZmkjrHCDdRTh7kou7E7mb716HvoQEyq6d1VyZOahyqf2ZcjIsFinK+As+4wBV JcXJMcpUWemI4Ojm8cbmNWQW3V2Ty9qLNUa6BpmntbdOdYowTih9QWHv2u1YsOR7 R6LJXdyo6V1RieeqfZaWXTQtN8yyXYhBewLIy0DxBAm329f5sRHUVd9/ZD2RMByD 1weEhbs0jhmYZFSfkwZ8SjAb4GkusjNTnDiK4Rsuz6pQK0BIGNAV0Mrnedq+i5eD wrrTI1/envStDpj9XGlSNajcaQGpTza1V1uaCIm4EanOMMTBc8DTXaj7MCOlTD8j fkNE3ykfloVSSzZAWCmcpV9fBsFwQp3m+cWrtIAAnOJDK+NV5FfABUwFHKnBUpxG YOUNCed0WJFx++xrHKylt8hWILLEATLHh1h5vDsEYJi4gwt2KxCSYQBGgSYKa1At tOUa5UINTMvpe4U9GEjHh6f1VedtUNYUzXjD5g2cn62d81RCSx3hB1KkfQSKtaDw H9sR8d+rDFt4fK9T/HPZ3EyM2i9FkZNv+CulfGNd3M0vnF8+qX2xRehWrqhwBBi0 2p7V9/t5TPhziAfJySKX+Jg= =j2kH -----END PGP SIGNATURE----- Merge tag 'mips_5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux Pull MIPS updates from Thomas Bogendoerfer: - add support for OpeneEmbed SOM9331 board - Ingenic fixes/improvments - other fixes and cleanups * tag 'mips_5.14' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (39 commits) MIPS: Fix PKMAP with 32-bit MIPS huge page support MIPS: CI20: Add second percpu timer for SMP. MIPS: CI20: Reduce clocksource to 750 kHz. MIPS: Ingenic: Add MAC syscon nodes for Ingenic SoCs. dt-bindings: clock: Add documentation for MAC PHY control bindings. MIPS: X1830: Respect cell count of common properties. MIPS: set mips32r5 for virt extensions MIPS: loongsoon64: Reserve memory below starting pfn to prevent Oops MIPS: MT extensions are not available on MIPS32r1 mips/kvm: Use BUG_ON instead of if condition followed by BUG MIPS: OCTEON: octeon-usb: Use devm_platform_get_and_ioremap_resource() MIPS: add PMD table accounting into MIPS'pmd_alloc_one MIPS: Loongson64: fix spelling of SPDX tag MIPS: ingenic: rs90: Add dedicated VRAM memory region MIPS: ingenic: gcw0: Set codec to cap-less mode for FM radio MIPS: ingenic: jz4780: Fix I2C nodes to match DT doc MIPS: ingenic: Select CPU_SUPPORTS_CPUFREQ && MIPS_EXTERNAL_TIMER MIPS: Kconfig: ingenic: Ensure MACH_INGENIC_GENERIC selects all SoCs MIPS: cpu-probe: Fix FPU detection on Ingenic JZ4760(B) MIPS: boot: Support specifying UART port on Ingenic SoCs ...
289 lines
6.9 KiB
Text
289 lines
6.9 KiB
Text
// SPDX-License-Identifier: GPL-2.0
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/dts-v1/;
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#include <dt-bindings/interrupt-controller/irq.h>
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/ {
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compatible = "loongson,loongson2k1000";
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#address-cells = <2>;
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#size-cells = <2>;
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cpus {
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#address-cells = <1>;
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#size-cells = <0>;
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cpu0: cpu@0 {
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device_type = "cpu";
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compatible = "loongson,gs264";
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reg = <0x0>;
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#clock-cells = <1>;
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clocks = <&cpu_clk>;
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};
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};
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memory@200000 {
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compatible = "memory";
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device_type = "memory";
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reg = <0x00000000 0x00200000 0x00000000 0x0ee00000>, /* 238 MB at 2 MB */
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<0x00000000 0x20000000 0x00000000 0x1f000000>, /* 496 MB at 512 MB */
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<0x00000001 0x10000000 0x00000001 0xb0000000>; /* 6912 MB at 4352MB */
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};
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cpu_clk: cpu_clk {
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#clock-cells = <0>;
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compatible = "fixed-clock";
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clock-frequency = <800000000>;
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};
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cpuintc: interrupt-controller {
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#address-cells = <0>;
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#interrupt-cells = <1>;
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interrupt-controller;
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compatible = "mti,cpu-interrupt-controller";
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};
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package0: bus@10000000 {
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compatible = "simple-bus";
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#address-cells = <2>;
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#size-cells = <2>;
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ranges = <0 0x10000000 0 0x10000000 0 0x10000000 /* ioports */
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0 0x40000000 0 0x40000000 0 0x40000000
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0xfe 0x00000000 0xfe 0x00000000 0 0x40000000>;
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liointc0: interrupt-controller@1fe11400 {
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compatible = "loongson,liointc-2.0";
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reg = <0 0x1fe11400 0 0x40>,
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<0 0x1fe11040 0 0x8>,
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<0 0x1fe11140 0 0x8>;
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reg-names = "main", "isr0", "isr1";
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&cpuintc>;
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interrupts = <2>;
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interrupt-names = "int0";
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loongson,parent_int_map = <0xffffffff>, /* int0 */
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<0x00000000>, /* int1 */
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<0x00000000>, /* int2 */
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<0x00000000>; /* int3 */
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};
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liointc1: interrupt-controller@1fe11440 {
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compatible = "loongson,liointc-2.0";
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reg = <0 0x1fe11440 0 0x40>,
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<0 0x1fe11048 0 0x8>,
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<0 0x1fe11148 0 0x8>;
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reg-names = "main", "isr0", "isr1";
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interrupt-controller;
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#interrupt-cells = <2>;
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interrupt-parent = <&cpuintc>;
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interrupts = <3>;
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interrupt-names = "int1";
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loongson,parent_int_map = <0x00000000>, /* int0 */
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<0xffffffff>, /* int1 */
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<0x00000000>, /* int2 */
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<0x00000000>; /* int3 */
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};
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uart0: serial@1fe00000 {
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compatible = "ns16550a";
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reg = <0 0x1fe00000 0 0x8>;
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clock-frequency = <125000000>;
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interrupt-parent = <&liointc0>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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no-loopback-test;
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};
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pci@1a000000 {
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compatible = "loongson,ls2k-pci";
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device_type = "pci";
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#address-cells = <3>;
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#size-cells = <2>;
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#interrupt-cells = <2>;
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reg = <0 0x1a000000 0 0x02000000>,
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<0xfe 0x00000000 0 0x20000000>;
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ranges = <0x01000000 0x0 0x00000000 0x0 0x18000000 0x0 0x00010000>,
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<0x02000000 0x0 0x40000000 0x0 0x40000000 0x0 0x40000000>;
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gmac@3,0 {
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compatible = "pci0014,7a03.0",
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"pci0014,7a03",
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"pciclass0c0320",
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"pciclass0c03",
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"loongson, pci-gmac";
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reg = <0x1800 0x0 0x0 0x0 0x0>;
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interrupts = <12 IRQ_TYPE_LEVEL_LOW>,
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<13 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "macirq", "eth_lpi";
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interrupt-parent = <&liointc0>;
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phy-mode = "rgmii";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy0: ethernet-phy@0 {
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reg = <0>;
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};
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};
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};
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gmac@3,1 {
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compatible = "pci0014,7a03.0",
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"pci0014,7a03",
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"pciclass0c0320",
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"pciclass0c03",
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"loongson, pci-gmac";
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reg = <0x1900 0x0 0x0 0x0 0x0>;
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interrupts = <14 IRQ_TYPE_LEVEL_LOW>,
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<15 IRQ_TYPE_LEVEL_LOW>;
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interrupt-names = "macirq", "eth_lpi";
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interrupt-parent = <&liointc0>;
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phy-mode = "rgmii";
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mdio {
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#address-cells = <1>;
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#size-cells = <0>;
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compatible = "snps,dwmac-mdio";
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phy1: ethernet-phy@1 {
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reg = <0>;
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};
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};
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};
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ehci@4,1 {
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compatible = "pci0014,7a14.0",
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"pci0014,7a14",
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"pciclass0c0320",
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"pciclass0c03";
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reg = <0x2100 0x0 0x0 0x0 0x0>;
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interrupts = <18 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc1>;
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};
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ohci@4,2 {
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compatible = "pci0014,7a24.0",
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"pci0014,7a24",
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"pciclass0c0310",
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"pciclass0c03";
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reg = <0x2200 0x0 0x0 0x0 0x0>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc1>;
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};
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sata@8,0 {
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compatible = "pci0014,7a08.0",
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"pci0014,7a08",
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"pciclass010601",
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"pciclass0106";
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reg = <0x4000 0x0 0x0 0x0 0x0>;
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interrupts = <19 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc0>;
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};
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pci_bridge@9,0 {
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compatible = "pci0014,7a19.0",
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"pci0014,7a19",
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"pciclass060400",
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"pciclass0604";
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reg = <0x4800 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &liointc1 0 IRQ_TYPE_LEVEL_LOW>;
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external-facing;
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};
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pci_bridge@a,0 {
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compatible = "pci0014,7a09.0",
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"pci0014,7a09",
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"pciclass060400",
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"pciclass0604";
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reg = <0x5000 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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interrupts = <1 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &liointc1 1 IRQ_TYPE_LEVEL_LOW>;
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external-facing;
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};
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pci_bridge@b,0 {
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compatible = "pci0014,7a09.0",
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"pci0014,7a09",
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"pciclass060400",
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"pciclass0604";
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reg = <0x5800 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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interrupts = <2 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &liointc1 2 IRQ_TYPE_LEVEL_LOW>;
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external-facing;
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};
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pci_bridge@c,0 {
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compatible = "pci0014,7a09.0",
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"pci0014,7a09",
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"pciclass060400",
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"pciclass0604";
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reg = <0x6000 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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interrupts = <3 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &liointc1 3 IRQ_TYPE_LEVEL_LOW>;
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external-facing;
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};
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pci_bridge@d,0 {
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compatible = "pci0014,7a19.0",
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"pci0014,7a19",
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"pciclass060400",
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"pciclass0604";
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reg = <0x6800 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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interrupts = <4 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &liointc1 4 IRQ_TYPE_LEVEL_LOW>;
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external-facing;
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};
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pci_bridge@e,0 {
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compatible = "pci0014,7a09.0",
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"pci0014,7a09",
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"pciclass060400",
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"pciclass0604";
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reg = <0x7000 0x0 0x0 0x0 0x0>;
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#interrupt-cells = <1>;
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interrupts = <5 IRQ_TYPE_LEVEL_LOW>;
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interrupt-parent = <&liointc1>;
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interrupt-map-mask = <0 0 0 0>;
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interrupt-map = <0 0 0 0 &liointc1 5 IRQ_TYPE_LEVEL_LOW>;
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external-facing;
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};
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};
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};
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};
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