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![Antonio Ospite](/assets/img/avatar_default.png)
Signed-off-by: Antonio Ospite <ao2@ao2.it> Cc: Mika Westerberg <mika.westerberg@linux.intel.com> Cc: Samuel Ortiz <sameo@linux.intel.com> Signed-off-by: Jiri Kosina <jkosina@suse.cz>
458 lines
11 KiB
C
458 lines
11 KiB
C
/*
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* Driver for Intel MSIC
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*
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* Copyright (C) 2011, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/err.h>
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#include <linux/gpio.h>
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#include <linux/io.h>
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#include <linux/module.h>
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#include <linux/mfd/core.h>
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#include <linux/mfd/intel_msic.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <asm/intel_scu_ipc.h>
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#define MSIC_VENDOR(id) ((id >> 6) & 3)
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#define MSIC_VERSION(id) (id & 0x3f)
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#define MSIC_MAJOR(id) ('A' + ((id >> 3) & 7))
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#define MSIC_MINOR(id) (id & 7)
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/*
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* MSIC interrupt tree is readable from SRAM at INTEL_MSIC_IRQ_PHYS_BASE.
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* Since IRQ block starts from address 0x002 we need to subtract that from
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* the actual IRQ status register address.
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*/
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#define MSIC_IRQ_STATUS(x) (INTEL_MSIC_IRQ_PHYS_BASE + ((x) - 2))
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#define MSIC_IRQ_STATUS_ACCDET MSIC_IRQ_STATUS(INTEL_MSIC_ACCDET)
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/*
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* The SCU hardware has limitation of 16 bytes per read/write buffer on
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* Medfield.
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*/
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#define SCU_IPC_RWBUF_LIMIT 16
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/**
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* struct intel_msic - an MSIC MFD instance
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* @pdev: pointer to the platform device
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* @vendor: vendor ID
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* @version: chip version
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* @irq_base: base address of the mapped MSIC SRAM interrupt tree
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*/
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struct intel_msic {
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struct platform_device *pdev;
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unsigned vendor;
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unsigned version;
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void __iomem *irq_base;
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};
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static struct resource msic_touch_resources[] = {
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource msic_adc_resources[] = {
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource msic_battery_resources[] = {
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource msic_gpio_resources[] = {
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource msic_audio_resources[] = {
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{
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.name = "IRQ",
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.flags = IORESOURCE_IRQ,
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},
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/*
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* We will pass IRQ_BASE to the driver now but this can be removed
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* when/if the driver starts to use intel_msic_irq_read().
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*/
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{
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.name = "IRQ_BASE",
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.flags = IORESOURCE_MEM,
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.start = MSIC_IRQ_STATUS_ACCDET,
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.end = MSIC_IRQ_STATUS_ACCDET,
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},
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};
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static struct resource msic_hdmi_resources[] = {
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource msic_thermal_resources[] = {
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource msic_power_btn_resources[] = {
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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static struct resource msic_ocd_resources[] = {
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{
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.flags = IORESOURCE_IRQ,
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},
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};
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/*
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* Devices that are part of the MSIC and are available via firmware
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* populated SFI DEVS table.
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*/
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static struct mfd_cell msic_devs[] = {
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[INTEL_MSIC_BLOCK_TOUCH] = {
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.name = "msic_touch",
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.num_resources = ARRAY_SIZE(msic_touch_resources),
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.resources = msic_touch_resources,
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},
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[INTEL_MSIC_BLOCK_ADC] = {
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.name = "msic_adc",
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.num_resources = ARRAY_SIZE(msic_adc_resources),
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.resources = msic_adc_resources,
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},
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[INTEL_MSIC_BLOCK_BATTERY] = {
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.name = "msic_battery",
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.num_resources = ARRAY_SIZE(msic_battery_resources),
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.resources = msic_battery_resources,
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},
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[INTEL_MSIC_BLOCK_GPIO] = {
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.name = "msic_gpio",
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.num_resources = ARRAY_SIZE(msic_gpio_resources),
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.resources = msic_gpio_resources,
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},
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[INTEL_MSIC_BLOCK_AUDIO] = {
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.name = "msic_audio",
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.num_resources = ARRAY_SIZE(msic_audio_resources),
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.resources = msic_audio_resources,
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},
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[INTEL_MSIC_BLOCK_HDMI] = {
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.name = "msic_hdmi",
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.num_resources = ARRAY_SIZE(msic_hdmi_resources),
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.resources = msic_hdmi_resources,
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},
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[INTEL_MSIC_BLOCK_THERMAL] = {
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.name = "msic_thermal",
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.num_resources = ARRAY_SIZE(msic_thermal_resources),
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.resources = msic_thermal_resources,
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},
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[INTEL_MSIC_BLOCK_POWER_BTN] = {
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.name = "msic_power_btn",
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.num_resources = ARRAY_SIZE(msic_power_btn_resources),
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.resources = msic_power_btn_resources,
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},
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[INTEL_MSIC_BLOCK_OCD] = {
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.name = "msic_ocd",
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.num_resources = ARRAY_SIZE(msic_ocd_resources),
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.resources = msic_ocd_resources,
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},
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};
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/*
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* Other MSIC related devices which are not directly available via SFI DEVS
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* table. These can be pseudo devices, regulators etc. which are needed for
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* different purposes.
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*
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* These devices appear only after the MSIC driver itself is initialized so
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* we can guarantee that the SCU IPC interface is ready.
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*/
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static const struct mfd_cell msic_other_devs[] = {
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/* Audio codec in the MSIC */
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{
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.id = -1,
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.name = "sn95031",
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},
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};
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/**
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* intel_msic_reg_read - read a single MSIC register
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* @reg: register to read
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* @val: register value is placed here
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*
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* Read a single register from MSIC. Returns %0 on success and negative
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* errno in case of failure.
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*
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* Function may sleep.
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*/
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int intel_msic_reg_read(unsigned short reg, u8 *val)
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{
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return intel_scu_ipc_ioread8(reg, val);
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}
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EXPORT_SYMBOL_GPL(intel_msic_reg_read);
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/**
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* intel_msic_reg_write - write a single MSIC register
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* @reg: register to write
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* @val: value to write to that register
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*
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* Write a single MSIC register. Returns 0 on success and negative
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* errno in case of failure.
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*
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* Function may sleep.
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*/
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int intel_msic_reg_write(unsigned short reg, u8 val)
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{
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return intel_scu_ipc_iowrite8(reg, val);
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}
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EXPORT_SYMBOL_GPL(intel_msic_reg_write);
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/**
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* intel_msic_reg_update - update a single MSIC register
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* @reg: register to update
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* @val: value to write to the register
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* @mask: specifies which of the bits are updated (%0 = don't update,
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* %1 = update)
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*
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* Perform an update to a register @reg. @mask is used to specify which
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* bits are updated. Returns %0 in case of success and negative errno in
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* case of failure.
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*
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* Function may sleep.
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*/
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int intel_msic_reg_update(unsigned short reg, u8 val, u8 mask)
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{
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return intel_scu_ipc_update_register(reg, val, mask);
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}
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EXPORT_SYMBOL_GPL(intel_msic_reg_update);
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/**
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* intel_msic_bulk_read - read an array of registers
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* @reg: array of register addresses to read
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* @buf: array where the read values are placed
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* @count: number of registers to read
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*
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* Function reads @count registers from the MSIC using addresses passed in
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* @reg. Read values are placed in @buf. Reads are performed atomically
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* wrt. MSIC.
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*
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* Returns %0 in case of success and negative errno in case of failure.
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*
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* Function may sleep.
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*/
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int intel_msic_bulk_read(unsigned short *reg, u8 *buf, size_t count)
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{
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if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
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return -EINVAL;
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return intel_scu_ipc_readv(reg, buf, count);
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}
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EXPORT_SYMBOL_GPL(intel_msic_bulk_read);
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/**
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* intel_msic_bulk_write - write an array of values to the MSIC registers
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* @reg: array of registers to write
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* @buf: values to write to each register
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* @count: number of registers to write
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*
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* Function writes @count registers in @buf to MSIC. Writes are performed
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* atomically wrt MSIC. Returns %0 in case of success and negative errno in
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* case of failure.
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*
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* Function may sleep.
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*/
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int intel_msic_bulk_write(unsigned short *reg, u8 *buf, size_t count)
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{
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if (WARN_ON(count > SCU_IPC_RWBUF_LIMIT))
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return -EINVAL;
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return intel_scu_ipc_writev(reg, buf, count);
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}
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EXPORT_SYMBOL_GPL(intel_msic_bulk_write);
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/**
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* intel_msic_irq_read - read a register from an MSIC interrupt tree
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* @msic: MSIC instance
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* @reg: interrupt register (between %INTEL_MSIC_IRQLVL1 and
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* %INTEL_MSIC_RESETIRQ2)
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* @val: value of the register is placed here
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*
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* This function can be used by an MSIC subdevice interrupt handler to read
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* a register value from the MSIC interrupt tree. In this way subdevice
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* drivers don't have to map in the interrupt tree themselves but can just
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* call this function instead.
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*
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* Function doesn't sleep and is callable from interrupt context.
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*
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* Returns %-EINVAL if @reg is outside of the allowed register region.
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*/
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int intel_msic_irq_read(struct intel_msic *msic, unsigned short reg, u8 *val)
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{
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if (WARN_ON(reg < INTEL_MSIC_IRQLVL1 || reg > INTEL_MSIC_RESETIRQ2))
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return -EINVAL;
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*val = readb(msic->irq_base + (reg - INTEL_MSIC_IRQLVL1));
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return 0;
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}
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EXPORT_SYMBOL_GPL(intel_msic_irq_read);
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static int intel_msic_init_devices(struct intel_msic *msic)
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{
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struct platform_device *pdev = msic->pdev;
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struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
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int ret, i;
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if (pdata->gpio) {
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struct mfd_cell *cell = &msic_devs[INTEL_MSIC_BLOCK_GPIO];
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cell->platform_data = pdata->gpio;
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cell->pdata_size = sizeof(*pdata->gpio);
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}
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if (pdata->ocd) {
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unsigned gpio = pdata->ocd->gpio;
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ret = devm_gpio_request_one(&pdev->dev, gpio,
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GPIOF_IN, "ocd_gpio");
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if (ret) {
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dev_err(&pdev->dev, "failed to register OCD GPIO\n");
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return ret;
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}
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ret = gpio_to_irq(gpio);
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if (ret < 0) {
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dev_err(&pdev->dev, "no IRQ number for OCD GPIO\n");
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return ret;
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}
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/* Update the IRQ number for the OCD */
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pdata->irq[INTEL_MSIC_BLOCK_OCD] = ret;
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}
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for (i = 0; i < ARRAY_SIZE(msic_devs); i++) {
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if (!pdata->irq[i])
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continue;
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ret = mfd_add_devices(&pdev->dev, -1, &msic_devs[i], 1, NULL,
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pdata->irq[i], NULL);
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if (ret)
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goto fail;
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}
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ret = mfd_add_devices(&pdev->dev, 0, msic_other_devs,
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ARRAY_SIZE(msic_other_devs), NULL, 0, NULL);
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if (ret)
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goto fail;
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return 0;
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fail:
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mfd_remove_devices(&pdev->dev);
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return ret;
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}
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static void intel_msic_remove_devices(struct intel_msic *msic)
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{
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struct platform_device *pdev = msic->pdev;
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mfd_remove_devices(&pdev->dev);
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}
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static int intel_msic_probe(struct platform_device *pdev)
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{
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struct intel_msic_platform_data *pdata = dev_get_platdata(&pdev->dev);
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struct intel_msic *msic;
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struct resource *res;
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u8 id0, id1;
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int ret;
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if (!pdata) {
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dev_err(&pdev->dev, "no platform data passed\n");
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return -EINVAL;
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}
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/* First validate that we have an MSIC in place */
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ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID0, &id0);
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if (ret) {
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dev_err(&pdev->dev, "failed to identify the MSIC chip (ID0)\n");
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return -ENXIO;
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}
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ret = intel_scu_ipc_ioread8(INTEL_MSIC_ID1, &id1);
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if (ret) {
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dev_err(&pdev->dev, "failed to identify the MSIC chip (ID1)\n");
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return -ENXIO;
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}
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if (MSIC_VENDOR(id0) != MSIC_VENDOR(id1)) {
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dev_err(&pdev->dev, "invalid vendor ID: %x, %x\n", id0, id1);
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return -ENXIO;
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}
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msic = devm_kzalloc(&pdev->dev, sizeof(*msic), GFP_KERNEL);
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if (!msic)
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return -ENOMEM;
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msic->vendor = MSIC_VENDOR(id0);
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msic->version = MSIC_VERSION(id0);
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msic->pdev = pdev;
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/*
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* Map in the MSIC interrupt tree area in SRAM. This is exposed to
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* the clients via intel_msic_irq_read().
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*/
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res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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msic->irq_base = devm_ioremap_resource(&pdev->dev, res);
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if (IS_ERR(msic->irq_base))
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return PTR_ERR(msic->irq_base);
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platform_set_drvdata(pdev, msic);
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ret = intel_msic_init_devices(msic);
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if (ret) {
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dev_err(&pdev->dev, "failed to initialize MSIC devices\n");
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return ret;
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}
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dev_info(&pdev->dev, "Intel MSIC version %c%d (vendor %#x)\n",
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MSIC_MAJOR(msic->version), MSIC_MINOR(msic->version),
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msic->vendor);
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return 0;
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}
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static int intel_msic_remove(struct platform_device *pdev)
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{
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struct intel_msic *msic = platform_get_drvdata(pdev);
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intel_msic_remove_devices(msic);
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return 0;
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}
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static struct platform_driver intel_msic_driver = {
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.probe = intel_msic_probe,
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.remove = intel_msic_remove,
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.driver = {
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.name = "intel_msic",
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.owner = THIS_MODULE,
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},
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};
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module_platform_driver(intel_msic_driver);
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MODULE_DESCRIPTION("Driver for Intel MSIC");
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MODULE_AUTHOR("Mika Westerberg <mika.westerberg@linux.intel.com>");
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MODULE_LICENSE("GPL");
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