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![Chew, Chiau Ee](/assets/img/avatar_default.png)
This is to fix the SPI DMA transfer failure for speed less than 1M. If using current DMA burst size setting (16), the Rx data bytes are invalid due to each data byte is multiplied according to the burst size setting. Let's said supposedly we shall receive the following 18 bytes of data: 01 02 03 04 05 06 07 08 09 10 11 12 13 14 15 16 17 18 Instead, the data bytes received consist of "16 bytes of '01' + 2 bytes of '02'" : 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 01 02 02 Signed-off-by: Chew, Chiau Ee <chiau.ee.chew@intel.com> Acked-by: Mika Westerberg <mika.westerberg@linux.intel.com> Signed-off-by: Mark Brown <broonie@linaro.org>
376 lines
9 KiB
C
376 lines
9 KiB
C
/*
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* PXA2xx SPI DMA engine support.
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*
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* Copyright (C) 2013, Intel Corporation
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* Author: Mika Westerberg <mika.westerberg@linux.intel.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#include <linux/device.h>
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#include <linux/dma-mapping.h>
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#include <linux/dmaengine.h>
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#include <linux/pxa2xx_ssp.h>
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#include <linux/scatterlist.h>
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#include <linux/sizes.h>
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#include <linux/spi/spi.h>
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#include <linux/spi/pxa2xx_spi.h>
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#include "spi-pxa2xx.h"
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static int pxa2xx_spi_map_dma_buffer(struct driver_data *drv_data,
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enum dma_data_direction dir)
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{
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int i, nents, len = drv_data->len;
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struct scatterlist *sg;
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struct device *dmadev;
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struct sg_table *sgt;
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void *buf, *pbuf;
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if (dir == DMA_TO_DEVICE) {
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dmadev = drv_data->tx_chan->device->dev;
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sgt = &drv_data->tx_sgt;
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buf = drv_data->tx;
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drv_data->tx_map_len = len;
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} else {
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dmadev = drv_data->rx_chan->device->dev;
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sgt = &drv_data->rx_sgt;
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buf = drv_data->rx;
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drv_data->rx_map_len = len;
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}
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nents = DIV_ROUND_UP(len, SZ_2K);
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if (nents != sgt->nents) {
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int ret;
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sg_free_table(sgt);
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ret = sg_alloc_table(sgt, nents, GFP_ATOMIC);
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if (ret)
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return ret;
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}
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pbuf = buf;
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for_each_sg(sgt->sgl, sg, sgt->nents, i) {
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size_t bytes = min_t(size_t, len, SZ_2K);
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if (buf)
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sg_set_buf(sg, pbuf, bytes);
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else
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sg_set_buf(sg, drv_data->dummy, bytes);
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pbuf += bytes;
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len -= bytes;
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}
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nents = dma_map_sg(dmadev, sgt->sgl, sgt->nents, dir);
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if (!nents)
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return -ENOMEM;
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return nents;
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}
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static void pxa2xx_spi_unmap_dma_buffer(struct driver_data *drv_data,
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enum dma_data_direction dir)
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{
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struct device *dmadev;
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struct sg_table *sgt;
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if (dir == DMA_TO_DEVICE) {
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dmadev = drv_data->tx_chan->device->dev;
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sgt = &drv_data->tx_sgt;
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} else {
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dmadev = drv_data->rx_chan->device->dev;
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sgt = &drv_data->rx_sgt;
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}
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dma_unmap_sg(dmadev, sgt->sgl, sgt->nents, dir);
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}
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static void pxa2xx_spi_unmap_dma_buffers(struct driver_data *drv_data)
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{
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if (!drv_data->dma_mapped)
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return;
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pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_FROM_DEVICE);
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pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);
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drv_data->dma_mapped = 0;
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}
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static void pxa2xx_spi_dma_transfer_complete(struct driver_data *drv_data,
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bool error)
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{
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struct spi_message *msg = drv_data->cur_msg;
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/*
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* It is possible that one CPU is handling ROR interrupt and other
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* just gets DMA completion. Calling pump_transfers() twice for the
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* same transfer leads to problems thus we prevent concurrent calls
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* by using ->dma_running.
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*/
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if (atomic_dec_and_test(&drv_data->dma_running)) {
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void __iomem *reg = drv_data->ioaddr;
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/*
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* If the other CPU is still handling the ROR interrupt we
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* might not know about the error yet. So we re-check the
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* ROR bit here before we clear the status register.
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*/
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if (!error) {
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u32 status = read_SSSR(reg) & drv_data->mask_sr;
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error = status & SSSR_ROR;
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}
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/* Clear status & disable interrupts */
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write_SSCR1(read_SSCR1(reg) & ~drv_data->dma_cr1, reg);
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write_SSSR_CS(drv_data, drv_data->clear_sr);
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if (!pxa25x_ssp_comp(drv_data))
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write_SSTO(0, reg);
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if (!error) {
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pxa2xx_spi_unmap_dma_buffers(drv_data);
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drv_data->tx += drv_data->tx_map_len;
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drv_data->rx += drv_data->rx_map_len;
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msg->actual_length += drv_data->len;
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msg->state = pxa2xx_spi_next_transfer(drv_data);
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} else {
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/* In case we got an error we disable the SSP now */
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write_SSCR0(read_SSCR0(reg) & ~SSCR0_SSE, reg);
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msg->state = ERROR_STATE;
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}
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tasklet_schedule(&drv_data->pump_transfers);
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}
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}
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static void pxa2xx_spi_dma_callback(void *data)
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{
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pxa2xx_spi_dma_transfer_complete(data, false);
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}
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static struct dma_async_tx_descriptor *
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pxa2xx_spi_dma_prepare_one(struct driver_data *drv_data,
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enum dma_transfer_direction dir)
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{
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struct pxa2xx_spi_master *pdata = drv_data->master_info;
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struct chip_data *chip = drv_data->cur_chip;
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enum dma_slave_buswidth width;
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struct dma_slave_config cfg;
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struct dma_chan *chan;
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struct sg_table *sgt;
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int nents, ret;
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switch (drv_data->n_bytes) {
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case 1:
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width = DMA_SLAVE_BUSWIDTH_1_BYTE;
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break;
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case 2:
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width = DMA_SLAVE_BUSWIDTH_2_BYTES;
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break;
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default:
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width = DMA_SLAVE_BUSWIDTH_4_BYTES;
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break;
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}
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memset(&cfg, 0, sizeof(cfg));
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cfg.direction = dir;
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if (dir == DMA_MEM_TO_DEV) {
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cfg.dst_addr = drv_data->ssdr_physical;
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cfg.dst_addr_width = width;
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cfg.dst_maxburst = chip->dma_burst_size;
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cfg.slave_id = pdata->tx_slave_id;
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sgt = &drv_data->tx_sgt;
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nents = drv_data->tx_nents;
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chan = drv_data->tx_chan;
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} else {
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cfg.src_addr = drv_data->ssdr_physical;
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cfg.src_addr_width = width;
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cfg.src_maxburst = chip->dma_burst_size;
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cfg.slave_id = pdata->rx_slave_id;
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sgt = &drv_data->rx_sgt;
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nents = drv_data->rx_nents;
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chan = drv_data->rx_chan;
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}
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ret = dmaengine_slave_config(chan, &cfg);
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if (ret) {
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dev_warn(&drv_data->pdev->dev, "DMA slave config failed\n");
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return NULL;
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}
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return dmaengine_prep_slave_sg(chan, sgt->sgl, nents, dir,
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DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
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}
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static bool pxa2xx_spi_dma_filter(struct dma_chan *chan, void *param)
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{
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const struct pxa2xx_spi_master *pdata = param;
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return chan->chan_id == pdata->tx_chan_id ||
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chan->chan_id == pdata->rx_chan_id;
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}
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bool pxa2xx_spi_dma_is_possible(size_t len)
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{
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return len <= MAX_DMA_LEN;
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}
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int pxa2xx_spi_map_dma_buffers(struct driver_data *drv_data)
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{
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const struct chip_data *chip = drv_data->cur_chip;
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int ret;
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if (!chip->enable_dma)
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return 0;
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/* Don't bother with DMA if we can't do even a single burst */
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if (drv_data->len < chip->dma_burst_size)
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return 0;
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ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_TO_DEVICE);
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if (ret <= 0) {
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dev_warn(&drv_data->pdev->dev, "failed to DMA map TX\n");
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return 0;
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}
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drv_data->tx_nents = ret;
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ret = pxa2xx_spi_map_dma_buffer(drv_data, DMA_FROM_DEVICE);
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if (ret <= 0) {
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pxa2xx_spi_unmap_dma_buffer(drv_data, DMA_TO_DEVICE);
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dev_warn(&drv_data->pdev->dev, "failed to DMA map RX\n");
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return 0;
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}
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drv_data->rx_nents = ret;
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return 1;
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}
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irqreturn_t pxa2xx_spi_dma_transfer(struct driver_data *drv_data)
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{
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u32 status;
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status = read_SSSR(drv_data->ioaddr) & drv_data->mask_sr;
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if (status & SSSR_ROR) {
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dev_err(&drv_data->pdev->dev, "FIFO overrun\n");
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dmaengine_terminate_all(drv_data->rx_chan);
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dmaengine_terminate_all(drv_data->tx_chan);
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pxa2xx_spi_dma_transfer_complete(drv_data, true);
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return IRQ_HANDLED;
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}
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return IRQ_NONE;
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}
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int pxa2xx_spi_dma_prepare(struct driver_data *drv_data, u32 dma_burst)
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{
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struct dma_async_tx_descriptor *tx_desc, *rx_desc;
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tx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_MEM_TO_DEV);
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if (!tx_desc) {
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dev_err(&drv_data->pdev->dev,
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"failed to get DMA TX descriptor\n");
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return -EBUSY;
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}
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rx_desc = pxa2xx_spi_dma_prepare_one(drv_data, DMA_DEV_TO_MEM);
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if (!rx_desc) {
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dev_err(&drv_data->pdev->dev,
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"failed to get DMA RX descriptor\n");
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return -EBUSY;
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}
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/* We are ready when RX completes */
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rx_desc->callback = pxa2xx_spi_dma_callback;
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rx_desc->callback_param = drv_data;
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dmaengine_submit(rx_desc);
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dmaengine_submit(tx_desc);
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return 0;
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}
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void pxa2xx_spi_dma_start(struct driver_data *drv_data)
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{
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dma_async_issue_pending(drv_data->rx_chan);
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dma_async_issue_pending(drv_data->tx_chan);
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atomic_set(&drv_data->dma_running, 1);
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}
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int pxa2xx_spi_dma_setup(struct driver_data *drv_data)
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{
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struct pxa2xx_spi_master *pdata = drv_data->master_info;
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struct device *dev = &drv_data->pdev->dev;
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dma_cap_mask_t mask;
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dma_cap_zero(mask);
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dma_cap_set(DMA_SLAVE, mask);
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drv_data->dummy = devm_kzalloc(dev, SZ_2K, GFP_KERNEL);
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if (!drv_data->dummy)
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return -ENOMEM;
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drv_data->tx_chan = dma_request_slave_channel_compat(mask,
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pxa2xx_spi_dma_filter, pdata, dev, "tx");
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if (!drv_data->tx_chan)
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return -ENODEV;
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drv_data->rx_chan = dma_request_slave_channel_compat(mask,
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pxa2xx_spi_dma_filter, pdata, dev, "rx");
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if (!drv_data->rx_chan) {
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dma_release_channel(drv_data->tx_chan);
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drv_data->tx_chan = NULL;
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return -ENODEV;
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}
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return 0;
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}
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void pxa2xx_spi_dma_release(struct driver_data *drv_data)
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{
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if (drv_data->rx_chan) {
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dmaengine_terminate_all(drv_data->rx_chan);
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dma_release_channel(drv_data->rx_chan);
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sg_free_table(&drv_data->rx_sgt);
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drv_data->rx_chan = NULL;
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}
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if (drv_data->tx_chan) {
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dmaengine_terminate_all(drv_data->tx_chan);
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dma_release_channel(drv_data->tx_chan);
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sg_free_table(&drv_data->tx_sgt);
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drv_data->tx_chan = NULL;
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}
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}
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void pxa2xx_spi_dma_resume(struct driver_data *drv_data)
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{
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}
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int pxa2xx_spi_set_dma_burst_and_threshold(struct chip_data *chip,
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struct spi_device *spi,
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u8 bits_per_word, u32 *burst_code,
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u32 *threshold)
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{
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struct pxa2xx_spi_chip *chip_info = spi->controller_data;
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/*
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* If the DMA burst size is given in chip_info we use that,
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* otherwise we use the default. Also we use the default FIFO
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* thresholds for now.
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*/
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*burst_code = chip_info ? chip_info->dma_burst_size : 1;
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*threshold = SSCR1_RxTresh(RX_THRESH_DFLT)
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| SSCR1_TxTresh(TX_THRESH_DFLT);
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return 0;
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}
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