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![Wei Yongjun](/assets/img/avatar_default.png)
Fix to return -EINVAL from the error handling case instead of 0 when failed to get fifo length. Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn> Signed-off-by: Mark Brown <broonie@linaro.org>
837 lines
19 KiB
C
837 lines
19 KiB
C
/*
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* Copyright (c) 2014, Fuzhou Rockchip Electronics Co., Ltd
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* Author: Addy Ke <addy.ke@rock-chips.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms and conditions of the GNU General Public License,
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* version 2, as published by the Free Software Foundation.
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*
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* This program is distributed in the hope it will be useful, but WITHOUT
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* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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* more details.
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*
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*/
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#include <linux/init.h>
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#include <linux/module.h>
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#include <linux/clk.h>
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#include <linux/err.h>
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#include <linux/delay.h>
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#include <linux/interrupt.h>
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#include <linux/platform_device.h>
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#include <linux/slab.h>
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#include <linux/spi/spi.h>
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#include <linux/scatterlist.h>
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#include <linux/of.h>
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#include <linux/pm_runtime.h>
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#include <linux/io.h>
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#include <linux/dmaengine.h>
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#define DRIVER_NAME "rockchip-spi"
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/* SPI register offsets */
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#define ROCKCHIP_SPI_CTRLR0 0x0000
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#define ROCKCHIP_SPI_CTRLR1 0x0004
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#define ROCKCHIP_SPI_SSIENR 0x0008
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#define ROCKCHIP_SPI_SER 0x000c
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#define ROCKCHIP_SPI_BAUDR 0x0010
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#define ROCKCHIP_SPI_TXFTLR 0x0014
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#define ROCKCHIP_SPI_RXFTLR 0x0018
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#define ROCKCHIP_SPI_TXFLR 0x001c
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#define ROCKCHIP_SPI_RXFLR 0x0020
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#define ROCKCHIP_SPI_SR 0x0024
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#define ROCKCHIP_SPI_IPR 0x0028
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#define ROCKCHIP_SPI_IMR 0x002c
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#define ROCKCHIP_SPI_ISR 0x0030
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#define ROCKCHIP_SPI_RISR 0x0034
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#define ROCKCHIP_SPI_ICR 0x0038
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#define ROCKCHIP_SPI_DMACR 0x003c
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#define ROCKCHIP_SPI_DMATDLR 0x0040
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#define ROCKCHIP_SPI_DMARDLR 0x0044
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#define ROCKCHIP_SPI_TXDR 0x0400
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#define ROCKCHIP_SPI_RXDR 0x0800
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/* Bit fields in CTRLR0 */
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#define CR0_DFS_OFFSET 0
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#define CR0_CFS_OFFSET 2
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#define CR0_SCPH_OFFSET 6
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#define CR0_SCPOL_OFFSET 7
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#define CR0_CSM_OFFSET 8
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#define CR0_CSM_KEEP 0x0
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/* ss_n be high for half sclk_out cycles */
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#define CR0_CSM_HALF 0X1
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/* ss_n be high for one sclk_out cycle */
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#define CR0_CSM_ONE 0x2
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/* ss_n to sclk_out delay */
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#define CR0_SSD_OFFSET 10
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/*
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* The period between ss_n active and
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* sclk_out active is half sclk_out cycles
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*/
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#define CR0_SSD_HALF 0x0
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/*
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* The period between ss_n active and
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* sclk_out active is one sclk_out cycle
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*/
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#define CR0_SSD_ONE 0x1
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#define CR0_EM_OFFSET 11
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#define CR0_EM_LITTLE 0x0
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#define CR0_EM_BIG 0x1
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#define CR0_FBM_OFFSET 12
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#define CR0_FBM_MSB 0x0
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#define CR0_FBM_LSB 0x1
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#define CR0_BHT_OFFSET 13
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#define CR0_BHT_16BIT 0x0
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#define CR0_BHT_8BIT 0x1
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#define CR0_RSD_OFFSET 14
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#define CR0_FRF_OFFSET 16
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#define CR0_FRF_SPI 0x0
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#define CR0_FRF_SSP 0x1
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#define CR0_FRF_MICROWIRE 0x2
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#define CR0_XFM_OFFSET 18
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#define CR0_XFM_MASK (0x03 << SPI_XFM_OFFSET)
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#define CR0_XFM_TR 0x0
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#define CR0_XFM_TO 0x1
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#define CR0_XFM_RO 0x2
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#define CR0_OPM_OFFSET 20
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#define CR0_OPM_MASTER 0x0
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#define CR0_OPM_SLAVE 0x1
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#define CR0_MTM_OFFSET 0x21
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/* Bit fields in SER, 2bit */
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#define SER_MASK 0x3
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/* Bit fields in SR, 5bit */
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#define SR_MASK 0x1f
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#define SR_BUSY (1 << 0)
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#define SR_TF_FULL (1 << 1)
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#define SR_TF_EMPTY (1 << 2)
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#define SR_RF_EMPTY (1 << 3)
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#define SR_RF_FULL (1 << 4)
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/* Bit fields in ISR, IMR, ISR, RISR, 5bit */
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#define INT_MASK 0x1f
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#define INT_TF_EMPTY (1 << 0)
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#define INT_TF_OVERFLOW (1 << 1)
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#define INT_RF_UNDERFLOW (1 << 2)
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#define INT_RF_OVERFLOW (1 << 3)
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#define INT_RF_FULL (1 << 4)
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/* Bit fields in ICR, 4bit */
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#define ICR_MASK 0x0f
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#define ICR_ALL (1 << 0)
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#define ICR_RF_UNDERFLOW (1 << 1)
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#define ICR_RF_OVERFLOW (1 << 2)
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#define ICR_TF_OVERFLOW (1 << 3)
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/* Bit fields in DMACR */
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#define RF_DMA_EN (1 << 0)
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#define TF_DMA_EN (1 << 1)
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#define RXBUSY (1 << 0)
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#define TXBUSY (1 << 1)
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enum rockchip_ssi_type {
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SSI_MOTO_SPI = 0,
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SSI_TI_SSP,
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SSI_NS_MICROWIRE,
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};
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struct rockchip_spi_dma_data {
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struct dma_chan *ch;
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enum dma_transfer_direction direction;
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dma_addr_t addr;
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};
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struct rockchip_spi {
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struct device *dev;
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struct spi_master *master;
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struct clk *spiclk;
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struct clk *apb_pclk;
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void __iomem *regs;
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/*depth of the FIFO buffer */
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u32 fifo_len;
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/* max bus freq supported */
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u32 max_freq;
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/* supported slave numbers */
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enum rockchip_ssi_type type;
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u16 mode;
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u8 tmode;
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u8 bpw;
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u8 n_bytes;
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unsigned len;
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u32 speed;
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const void *tx;
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const void *tx_end;
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void *rx;
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void *rx_end;
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u32 state;
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/* protect state */
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spinlock_t lock;
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struct completion xfer_completion;
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u32 use_dma;
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struct sg_table tx_sg;
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struct sg_table rx_sg;
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struct rockchip_spi_dma_data dma_rx;
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struct rockchip_spi_dma_data dma_tx;
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};
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static inline void spi_enable_chip(struct rockchip_spi *rs, int enable)
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{
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writel_relaxed((enable ? 1 : 0), rs->regs + ROCKCHIP_SPI_SSIENR);
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}
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static inline void spi_set_clk(struct rockchip_spi *rs, u16 div)
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{
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writel_relaxed(div, rs->regs + ROCKCHIP_SPI_BAUDR);
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}
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static inline void flush_fifo(struct rockchip_spi *rs)
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{
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while (readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR))
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readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
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}
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static inline void wait_for_idle(struct rockchip_spi *rs)
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{
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unsigned long timeout = jiffies + msecs_to_jiffies(5);
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do {
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if (!(readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY))
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return;
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} while (time_before(jiffies, timeout));
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dev_warn(rs->dev, "spi controller is in busy state!\n");
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}
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static u32 get_fifo_len(struct rockchip_spi *rs)
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{
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u32 fifo;
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for (fifo = 2; fifo < 32; fifo++) {
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writel_relaxed(fifo, rs->regs + ROCKCHIP_SPI_TXFTLR);
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if (fifo != readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFTLR))
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break;
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}
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writel_relaxed(0, rs->regs + ROCKCHIP_SPI_TXFTLR);
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return (fifo == 31) ? 0 : fifo;
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}
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static inline u32 tx_max(struct rockchip_spi *rs)
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{
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u32 tx_left, tx_room;
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tx_left = (rs->tx_end - rs->tx) / rs->n_bytes;
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tx_room = rs->fifo_len - readl_relaxed(rs->regs + ROCKCHIP_SPI_TXFLR);
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return min(tx_left, tx_room);
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}
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static inline u32 rx_max(struct rockchip_spi *rs)
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{
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u32 rx_left = (rs->rx_end - rs->rx) / rs->n_bytes;
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u32 rx_room = (u32)readl_relaxed(rs->regs + ROCKCHIP_SPI_RXFLR);
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return min(rx_left, rx_room);
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}
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static void rockchip_spi_set_cs(struct spi_device *spi, bool enable)
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{
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u32 ser;
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struct rockchip_spi *rs = spi_master_get_devdata(spi->master);
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ser = readl_relaxed(rs->regs + ROCKCHIP_SPI_SER) & SER_MASK;
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/*
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* drivers/spi/spi.c:
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* static void spi_set_cs(struct spi_device *spi, bool enable)
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* {
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* if (spi->mode & SPI_CS_HIGH)
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* enable = !enable;
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*
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* if (spi->cs_gpio >= 0)
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* gpio_set_value(spi->cs_gpio, !enable);
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* else if (spi->master->set_cs)
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* spi->master->set_cs(spi, !enable);
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* }
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*
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* Note: enable(rockchip_spi_set_cs) = !enable(spi_set_cs)
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*/
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if (!enable)
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ser |= 1 << spi->chip_select;
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else
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ser &= ~(1 << spi->chip_select);
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writel_relaxed(ser, rs->regs + ROCKCHIP_SPI_SER);
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}
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static int rockchip_spi_prepare_message(struct spi_master *master,
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struct spi_message *msg)
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{
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struct rockchip_spi *rs = spi_master_get_devdata(master);
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struct spi_device *spi = msg->spi;
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rs->mode = spi->mode;
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return 0;
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}
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static int rockchip_spi_unprepare_message(struct spi_master *master,
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struct spi_message *msg)
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{
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unsigned long flags;
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struct rockchip_spi *rs = spi_master_get_devdata(master);
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spin_lock_irqsave(&rs->lock, flags);
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/*
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* For DMA mode, we need terminate DMA channel and flush
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* fifo for the next transfer if DMA thansfer timeout.
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* unprepare_message() was called by core if transfer complete
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* or timeout. Maybe it is reasonable for error handling here.
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*/
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if (rs->use_dma) {
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if (rs->state & RXBUSY) {
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dmaengine_terminate_all(rs->dma_rx.ch);
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flush_fifo(rs);
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}
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if (rs->state & TXBUSY)
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dmaengine_terminate_all(rs->dma_tx.ch);
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}
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spin_unlock_irqrestore(&rs->lock, flags);
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return 0;
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}
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static void rockchip_spi_pio_writer(struct rockchip_spi *rs)
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{
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u32 max = tx_max(rs);
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u32 txw = 0;
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while (max--) {
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if (rs->n_bytes == 1)
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txw = *(u8 *)(rs->tx);
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else
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txw = *(u16 *)(rs->tx);
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writel_relaxed(txw, rs->regs + ROCKCHIP_SPI_TXDR);
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rs->tx += rs->n_bytes;
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}
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}
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static void rockchip_spi_pio_reader(struct rockchip_spi *rs)
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{
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u32 max = rx_max(rs);
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u32 rxw;
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while (max--) {
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rxw = readl_relaxed(rs->regs + ROCKCHIP_SPI_RXDR);
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if (rs->n_bytes == 1)
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*(u8 *)(rs->rx) = (u8)rxw;
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else
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*(u16 *)(rs->rx) = (u16)rxw;
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rs->rx += rs->n_bytes;
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}
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}
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static int rockchip_spi_pio_transfer(struct rockchip_spi *rs)
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{
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int remain = 0;
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do {
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if (rs->tx) {
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remain = rs->tx_end - rs->tx;
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rockchip_spi_pio_writer(rs);
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}
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if (rs->rx) {
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remain = rs->rx_end - rs->rx;
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rockchip_spi_pio_reader(rs);
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}
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cpu_relax();
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} while (remain);
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/* If tx, wait until the FIFO data completely. */
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if (rs->tx)
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wait_for_idle(rs);
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return 0;
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}
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static void rockchip_spi_dma_rxcb(void *data)
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{
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unsigned long flags;
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struct rockchip_spi *rs = data;
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spin_lock_irqsave(&rs->lock, flags);
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rs->state &= ~RXBUSY;
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if (!(rs->state & TXBUSY))
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spi_finalize_current_transfer(rs->master);
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spin_unlock_irqrestore(&rs->lock, flags);
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}
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static void rockchip_spi_dma_txcb(void *data)
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{
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unsigned long flags;
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struct rockchip_spi *rs = data;
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/* Wait until the FIFO data completely. */
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wait_for_idle(rs);
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spin_lock_irqsave(&rs->lock, flags);
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rs->state &= ~TXBUSY;
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if (!(rs->state & RXBUSY))
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spi_finalize_current_transfer(rs->master);
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spin_unlock_irqrestore(&rs->lock, flags);
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}
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static int rockchip_spi_dma_transfer(struct rockchip_spi *rs)
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{
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unsigned long flags;
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struct dma_slave_config rxconf, txconf;
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struct dma_async_tx_descriptor *rxdesc, *txdesc;
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spin_lock_irqsave(&rs->lock, flags);
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rs->state &= ~RXBUSY;
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rs->state &= ~TXBUSY;
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spin_unlock_irqrestore(&rs->lock, flags);
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if (rs->rx) {
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rxconf.direction = rs->dma_rx.direction;
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rxconf.src_addr = rs->dma_rx.addr;
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rxconf.src_addr_width = rs->n_bytes;
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rxconf.src_maxburst = rs->n_bytes;
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dmaengine_slave_config(rs->dma_rx.ch, &rxconf);
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rxdesc = dmaengine_prep_slave_sg(
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rs->dma_rx.ch,
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rs->rx_sg.sgl, rs->rx_sg.nents,
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rs->dma_rx.direction, DMA_PREP_INTERRUPT);
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rxdesc->callback = rockchip_spi_dma_rxcb;
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rxdesc->callback_param = rs;
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}
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if (rs->tx) {
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txconf.direction = rs->dma_tx.direction;
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txconf.dst_addr = rs->dma_tx.addr;
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txconf.dst_addr_width = rs->n_bytes;
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txconf.dst_maxburst = rs->n_bytes;
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dmaengine_slave_config(rs->dma_tx.ch, &txconf);
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txdesc = dmaengine_prep_slave_sg(
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rs->dma_tx.ch,
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rs->tx_sg.sgl, rs->tx_sg.nents,
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rs->dma_tx.direction, DMA_PREP_INTERRUPT);
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txdesc->callback = rockchip_spi_dma_txcb;
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txdesc->callback_param = rs;
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}
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/* rx must be started before tx due to spi instinct */
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if (rs->rx) {
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spin_lock_irqsave(&rs->lock, flags);
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rs->state |= RXBUSY;
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spin_unlock_irqrestore(&rs->lock, flags);
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dmaengine_submit(rxdesc);
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dma_async_issue_pending(rs->dma_rx.ch);
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}
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if (rs->tx) {
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spin_lock_irqsave(&rs->lock, flags);
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rs->state |= TXBUSY;
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spin_unlock_irqrestore(&rs->lock, flags);
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dmaengine_submit(txdesc);
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dma_async_issue_pending(rs->dma_tx.ch);
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}
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return 1;
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}
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static void rockchip_spi_config(struct rockchip_spi *rs)
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{
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u32 div = 0;
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u32 dmacr = 0;
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u32 cr0 = (CR0_BHT_8BIT << CR0_BHT_OFFSET)
|
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| (CR0_SSD_ONE << CR0_SSD_OFFSET);
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cr0 |= (rs->n_bytes << CR0_DFS_OFFSET);
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cr0 |= ((rs->mode & 0x3) << CR0_SCPH_OFFSET);
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cr0 |= (rs->tmode << CR0_XFM_OFFSET);
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cr0 |= (rs->type << CR0_FRF_OFFSET);
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if (rs->use_dma) {
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if (rs->tx)
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dmacr |= TF_DMA_EN;
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if (rs->rx)
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dmacr |= RF_DMA_EN;
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}
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/* div doesn't support odd number */
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div = rs->max_freq / rs->speed;
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div = (div + 1) & 0xfffe;
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spi_enable_chip(rs, 0);
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|
|
writel_relaxed(cr0, rs->regs + ROCKCHIP_SPI_CTRLR0);
|
|
|
|
writel_relaxed(rs->len - 1, rs->regs + ROCKCHIP_SPI_CTRLR1);
|
|
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_TXFTLR);
|
|
writel_relaxed(rs->fifo_len / 2 - 1, rs->regs + ROCKCHIP_SPI_RXFTLR);
|
|
|
|
writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMATDLR);
|
|
writel_relaxed(0, rs->regs + ROCKCHIP_SPI_DMARDLR);
|
|
writel_relaxed(dmacr, rs->regs + ROCKCHIP_SPI_DMACR);
|
|
|
|
spi_set_clk(rs, div);
|
|
|
|
dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
|
|
|
|
spi_enable_chip(rs, 1);
|
|
}
|
|
|
|
static int rockchip_spi_transfer_one(
|
|
struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
int ret = 0;
|
|
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
|
|
|
WARN_ON((readl_relaxed(rs->regs + ROCKCHIP_SPI_SR) & SR_BUSY));
|
|
|
|
if (!xfer->tx_buf && !xfer->rx_buf) {
|
|
dev_err(rs->dev, "No buffer for transfer\n");
|
|
return -EINVAL;
|
|
}
|
|
|
|
rs->speed = xfer->speed_hz;
|
|
rs->bpw = xfer->bits_per_word;
|
|
rs->n_bytes = rs->bpw >> 3;
|
|
|
|
rs->tx = xfer->tx_buf;
|
|
rs->tx_end = rs->tx + xfer->len;
|
|
rs->rx = xfer->rx_buf;
|
|
rs->rx_end = rs->rx + xfer->len;
|
|
rs->len = xfer->len;
|
|
|
|
rs->tx_sg = xfer->tx_sg;
|
|
rs->rx_sg = xfer->rx_sg;
|
|
|
|
if (rs->tx && rs->rx)
|
|
rs->tmode = CR0_XFM_TR;
|
|
else if (rs->tx)
|
|
rs->tmode = CR0_XFM_TO;
|
|
else if (rs->rx)
|
|
rs->tmode = CR0_XFM_RO;
|
|
|
|
if (master->can_dma && master->can_dma(master, spi, xfer))
|
|
rs->use_dma = 1;
|
|
else
|
|
rs->use_dma = 0;
|
|
|
|
rockchip_spi_config(rs);
|
|
|
|
if (rs->use_dma)
|
|
ret = rockchip_spi_dma_transfer(rs);
|
|
else
|
|
ret = rockchip_spi_pio_transfer(rs);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static bool rockchip_spi_can_dma(struct spi_master *master,
|
|
struct spi_device *spi,
|
|
struct spi_transfer *xfer)
|
|
{
|
|
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
|
|
|
return (xfer->len > rs->fifo_len);
|
|
}
|
|
|
|
static int rockchip_spi_probe(struct platform_device *pdev)
|
|
{
|
|
int ret = 0;
|
|
struct rockchip_spi *rs;
|
|
struct spi_master *master;
|
|
struct resource *mem;
|
|
|
|
master = spi_alloc_master(&pdev->dev, sizeof(struct rockchip_spi));
|
|
if (!master)
|
|
return -ENOMEM;
|
|
|
|
platform_set_drvdata(pdev, master);
|
|
|
|
rs = spi_master_get_devdata(master);
|
|
memset(rs, 0, sizeof(struct rockchip_spi));
|
|
|
|
/* Get basic io resource and map it */
|
|
mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
rs->regs = devm_ioremap_resource(&pdev->dev, mem);
|
|
if (IS_ERR(rs->regs)) {
|
|
ret = PTR_ERR(rs->regs);
|
|
goto err_ioremap_resource;
|
|
}
|
|
|
|
rs->apb_pclk = devm_clk_get(&pdev->dev, "apb_pclk");
|
|
if (IS_ERR(rs->apb_pclk)) {
|
|
dev_err(&pdev->dev, "Failed to get apb_pclk\n");
|
|
ret = PTR_ERR(rs->apb_pclk);
|
|
goto err_ioremap_resource;
|
|
}
|
|
|
|
rs->spiclk = devm_clk_get(&pdev->dev, "spiclk");
|
|
if (IS_ERR(rs->spiclk)) {
|
|
dev_err(&pdev->dev, "Failed to get spi_pclk\n");
|
|
ret = PTR_ERR(rs->spiclk);
|
|
goto err_ioremap_resource;
|
|
}
|
|
|
|
ret = clk_prepare_enable(rs->apb_pclk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to enable apb_pclk\n");
|
|
goto err_ioremap_resource;
|
|
}
|
|
|
|
ret = clk_prepare_enable(rs->spiclk);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to enable spi_clk\n");
|
|
goto err_spiclk_enable;
|
|
}
|
|
|
|
spi_enable_chip(rs, 0);
|
|
|
|
rs->type = SSI_MOTO_SPI;
|
|
rs->master = master;
|
|
rs->dev = &pdev->dev;
|
|
rs->max_freq = clk_get_rate(rs->spiclk);
|
|
|
|
rs->fifo_len = get_fifo_len(rs);
|
|
if (!rs->fifo_len) {
|
|
dev_err(&pdev->dev, "Failed to get fifo length\n");
|
|
ret = -EINVAL;
|
|
goto err_get_fifo_len;
|
|
}
|
|
|
|
spin_lock_init(&rs->lock);
|
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
master->auto_runtime_pm = true;
|
|
master->bus_num = pdev->id;
|
|
master->mode_bits = SPI_CPOL | SPI_CPHA | SPI_LOOP;
|
|
master->num_chipselect = 2;
|
|
master->dev.of_node = pdev->dev.of_node;
|
|
master->bits_per_word_mask = SPI_BPW_MASK(16) | SPI_BPW_MASK(8);
|
|
|
|
master->set_cs = rockchip_spi_set_cs;
|
|
master->prepare_message = rockchip_spi_prepare_message;
|
|
master->unprepare_message = rockchip_spi_unprepare_message;
|
|
master->transfer_one = rockchip_spi_transfer_one;
|
|
|
|
rs->dma_tx.ch = dma_request_slave_channel(rs->dev, "tx");
|
|
if (!rs->dma_tx.ch)
|
|
dev_warn(rs->dev, "Failed to request TX DMA channel\n");
|
|
|
|
rs->dma_rx.ch = dma_request_slave_channel(rs->dev, "rx");
|
|
if (!rs->dma_rx.ch) {
|
|
if (rs->dma_tx.ch) {
|
|
dma_release_channel(rs->dma_tx.ch);
|
|
rs->dma_tx.ch = NULL;
|
|
}
|
|
dev_warn(rs->dev, "Failed to request RX DMA channel\n");
|
|
}
|
|
|
|
if (rs->dma_tx.ch && rs->dma_rx.ch) {
|
|
rs->dma_tx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_TXDR);
|
|
rs->dma_rx.addr = (dma_addr_t)(mem->start + ROCKCHIP_SPI_RXDR);
|
|
rs->dma_tx.direction = DMA_MEM_TO_DEV;
|
|
rs->dma_tx.direction = DMA_DEV_TO_MEM;
|
|
|
|
master->can_dma = rockchip_spi_can_dma;
|
|
master->dma_tx = rs->dma_tx.ch;
|
|
master->dma_rx = rs->dma_rx.ch;
|
|
}
|
|
|
|
ret = devm_spi_register_master(&pdev->dev, master);
|
|
if (ret) {
|
|
dev_err(&pdev->dev, "Failed to register master\n");
|
|
goto err_register_master;
|
|
}
|
|
|
|
return 0;
|
|
|
|
err_register_master:
|
|
if (rs->dma_tx.ch)
|
|
dma_release_channel(rs->dma_tx.ch);
|
|
if (rs->dma_rx.ch)
|
|
dma_release_channel(rs->dma_rx.ch);
|
|
err_get_fifo_len:
|
|
clk_disable_unprepare(rs->spiclk);
|
|
err_spiclk_enable:
|
|
clk_disable_unprepare(rs->apb_pclk);
|
|
err_ioremap_resource:
|
|
spi_master_put(master);
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rockchip_spi_remove(struct platform_device *pdev)
|
|
{
|
|
struct spi_master *master = spi_master_get(platform_get_drvdata(pdev));
|
|
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
|
|
|
clk_disable_unprepare(rs->spiclk);
|
|
clk_disable_unprepare(rs->apb_pclk);
|
|
|
|
if (rs->dma_tx.ch)
|
|
dma_release_channel(rs->dma_tx.ch);
|
|
if (rs->dma_rx.ch)
|
|
dma_release_channel(rs->dma_rx.ch);
|
|
|
|
spi_master_put(master);
|
|
|
|
return 0;
|
|
}
|
|
|
|
#ifdef CONFIG_PM_SLEEP
|
|
static int rockchip_spi_suspend(struct device *dev)
|
|
{
|
|
int ret = 0;
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
|
|
|
ret = spi_master_suspend(rs->master);
|
|
if (ret)
|
|
return ret;
|
|
|
|
if (!pm_runtime_suspended(dev)) {
|
|
clk_disable_unprepare(rs->spiclk);
|
|
clk_disable_unprepare(rs->apb_pclk);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
static int rockchip_spi_resume(struct device *dev)
|
|
{
|
|
int ret = 0;
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
|
|
|
if (!pm_runtime_suspended(dev)) {
|
|
ret = clk_prepare_enable(rs->apb_pclk);
|
|
if (ret < 0)
|
|
return ret;
|
|
|
|
ret = clk_prepare_enable(rs->spiclk);
|
|
if (ret < 0) {
|
|
clk_disable_unprepare(rs->apb_pclk);
|
|
return ret;
|
|
}
|
|
}
|
|
|
|
ret = spi_master_resume(rs->master);
|
|
if (ret < 0) {
|
|
clk_disable_unprepare(rs->spiclk);
|
|
clk_disable_unprepare(rs->apb_pclk);
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_PM_SLEEP */
|
|
|
|
#ifdef CONFIG_PM_RUNTIME
|
|
static int rockchip_spi_runtime_suspend(struct device *dev)
|
|
{
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
|
|
|
clk_disable_unprepare(rs->spiclk);
|
|
clk_disable_unprepare(rs->apb_pclk);
|
|
|
|
return 0;
|
|
}
|
|
|
|
static int rockchip_spi_runtime_resume(struct device *dev)
|
|
{
|
|
int ret;
|
|
struct spi_master *master = dev_get_drvdata(dev);
|
|
struct rockchip_spi *rs = spi_master_get_devdata(master);
|
|
|
|
ret = clk_prepare_enable(rs->apb_pclk);
|
|
if (ret)
|
|
return ret;
|
|
|
|
ret = clk_prepare_enable(rs->spiclk);
|
|
if (ret)
|
|
clk_disable_unprepare(rs->apb_pclk);
|
|
|
|
return ret;
|
|
}
|
|
#endif /* CONFIG_PM_RUNTIME */
|
|
|
|
static const struct dev_pm_ops rockchip_spi_pm = {
|
|
SET_SYSTEM_SLEEP_PM_OPS(rockchip_spi_suspend, rockchip_spi_resume)
|
|
SET_RUNTIME_PM_OPS(rockchip_spi_runtime_suspend,
|
|
rockchip_spi_runtime_resume, NULL)
|
|
};
|
|
|
|
static const struct of_device_id rockchip_spi_dt_match[] = {
|
|
{ .compatible = "rockchip,rk3066-spi", },
|
|
{ .compatible = "rockchip,rk3188-spi", },
|
|
{ .compatible = "rockchip,rk3288-spi", },
|
|
{ },
|
|
};
|
|
MODULE_DEVICE_TABLE(of, rockchip_spi_dt_match);
|
|
|
|
static struct platform_driver rockchip_spi_driver = {
|
|
.driver = {
|
|
.name = DRIVER_NAME,
|
|
.owner = THIS_MODULE,
|
|
.pm = &rockchip_spi_pm,
|
|
.of_match_table = of_match_ptr(rockchip_spi_dt_match),
|
|
},
|
|
.probe = rockchip_spi_probe,
|
|
.remove = rockchip_spi_remove,
|
|
};
|
|
|
|
module_platform_driver(rockchip_spi_driver);
|
|
|
|
MODULE_AUTHOR("Addy Ke <addy.ke@rock-chips.com>");
|
|
MODULE_DESCRIPTION("ROCKCHIP SPI Controller Driver");
|
|
MODULE_LICENSE("GPL v2");
|