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316d0d92fb
Most ROHM PMIC sub-devices only use the regmap pointer from parent device. They can obtain this by dev_get_regamap so in most cases the MFD device does not need to allocate and populate the driver data. Simplify drivers by removing this. The BD70528 still needs the access to watchdog mutex so keep rohm_regmap_dev in use on BD70528 RTC and WDG drivers for now. Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com> Signed-off-by: Lee Jones <lee.jones@linaro.org>
313 lines
8.8 KiB
C
313 lines
8.8 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/* Copyright (C) 2018 ROHM Semiconductors */
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#ifndef __LINUX_MFD_BD718XX_H__
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#define __LINUX_MFD_BD718XX_H__
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#include <linux/mfd/rohm-generic.h>
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#include <linux/regmap.h>
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enum {
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BD718XX_BUCK1 = 0,
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BD718XX_BUCK2,
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BD718XX_BUCK3,
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BD718XX_BUCK4,
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BD718XX_BUCK5,
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BD718XX_BUCK6,
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BD718XX_BUCK7,
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BD718XX_BUCK8,
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BD718XX_LDO1,
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BD718XX_LDO2,
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BD718XX_LDO3,
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BD718XX_LDO4,
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BD718XX_LDO5,
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BD718XX_LDO6,
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BD718XX_LDO7,
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BD718XX_REGULATOR_AMOUNT,
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};
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/* Common voltage configurations */
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#define BD718XX_DVS_BUCK_VOLTAGE_NUM 0x3D
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#define BD718XX_4TH_NODVS_BUCK_VOLTAGE_NUM 0x3D
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#define BD718XX_LDO1_VOLTAGE_NUM 0x08
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#define BD718XX_LDO2_VOLTAGE_NUM 0x02
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#define BD718XX_LDO3_VOLTAGE_NUM 0x10
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#define BD718XX_LDO4_VOLTAGE_NUM 0x0A
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#define BD718XX_LDO6_VOLTAGE_NUM 0x0A
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/* BD71837 specific voltage configurations */
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#define BD71837_BUCK5_VOLTAGE_NUM 0x10
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#define BD71837_BUCK6_VOLTAGE_NUM 0x04
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#define BD71837_BUCK7_VOLTAGE_NUM 0x08
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#define BD71837_LDO5_VOLTAGE_NUM 0x10
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#define BD71837_LDO7_VOLTAGE_NUM 0x10
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/* BD71847 specific voltage configurations */
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#define BD71847_BUCK3_VOLTAGE_NUM 0x18
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#define BD71847_BUCK4_VOLTAGE_NUM 0x08
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#define BD71847_LDO5_VOLTAGE_NUM 0x20
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/* Registers specific to BD71837 */
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enum {
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BD71837_REG_BUCK3_CTRL = 0x07,
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BD71837_REG_BUCK4_CTRL = 0x08,
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BD71837_REG_BUCK3_VOLT_RUN = 0x12,
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BD71837_REG_BUCK4_VOLT_RUN = 0x13,
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BD71837_REG_LDO7_VOLT = 0x1E,
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};
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/* Registers common for BD71837 and BD71847 */
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enum {
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BD718XX_REG_REV = 0x00,
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BD718XX_REG_SWRESET = 0x01,
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BD718XX_REG_I2C_DEV = 0x02,
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BD718XX_REG_PWRCTRL0 = 0x03,
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BD718XX_REG_PWRCTRL1 = 0x04,
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BD718XX_REG_BUCK1_CTRL = 0x05,
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BD718XX_REG_BUCK2_CTRL = 0x06,
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BD718XX_REG_1ST_NODVS_BUCK_CTRL = 0x09,
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BD718XX_REG_2ND_NODVS_BUCK_CTRL = 0x0A,
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BD718XX_REG_3RD_NODVS_BUCK_CTRL = 0x0B,
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BD718XX_REG_4TH_NODVS_BUCK_CTRL = 0x0C,
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BD718XX_REG_BUCK1_VOLT_RUN = 0x0D,
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BD718XX_REG_BUCK1_VOLT_IDLE = 0x0E,
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BD718XX_REG_BUCK1_VOLT_SUSP = 0x0F,
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BD718XX_REG_BUCK2_VOLT_RUN = 0x10,
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BD718XX_REG_BUCK2_VOLT_IDLE = 0x11,
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BD718XX_REG_1ST_NODVS_BUCK_VOLT = 0x14,
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BD718XX_REG_2ND_NODVS_BUCK_VOLT = 0x15,
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BD718XX_REG_3RD_NODVS_BUCK_VOLT = 0x16,
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BD718XX_REG_4TH_NODVS_BUCK_VOLT = 0x17,
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BD718XX_REG_LDO1_VOLT = 0x18,
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BD718XX_REG_LDO2_VOLT = 0x19,
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BD718XX_REG_LDO3_VOLT = 0x1A,
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BD718XX_REG_LDO4_VOLT = 0x1B,
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BD718XX_REG_LDO5_VOLT = 0x1C,
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BD718XX_REG_LDO6_VOLT = 0x1D,
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BD718XX_REG_TRANS_COND0 = 0x1F,
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BD718XX_REG_TRANS_COND1 = 0x20,
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BD718XX_REG_VRFAULTEN = 0x21,
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BD718XX_REG_MVRFLTMASK0 = 0x22,
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BD718XX_REG_MVRFLTMASK1 = 0x23,
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BD718XX_REG_MVRFLTMASK2 = 0x24,
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BD718XX_REG_RCVCFG = 0x25,
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BD718XX_REG_RCVNUM = 0x26,
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BD718XX_REG_PWRONCONFIG0 = 0x27,
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BD718XX_REG_PWRONCONFIG1 = 0x28,
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BD718XX_REG_RESETSRC = 0x29,
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BD718XX_REG_MIRQ = 0x2A,
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BD718XX_REG_IRQ = 0x2B,
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BD718XX_REG_IN_MON = 0x2C,
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BD718XX_REG_POW_STATE = 0x2D,
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BD718XX_REG_OUT32K = 0x2E,
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BD718XX_REG_REGLOCK = 0x2F,
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BD718XX_REG_OTPVER = 0xFF,
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BD718XX_MAX_REGISTER = 0x100,
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};
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#define REGLOCK_PWRSEQ 0x1
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#define REGLOCK_VREG 0x10
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/* Generic BUCK control masks */
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#define BD718XX_BUCK_SEL 0x02
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#define BD718XX_BUCK_EN 0x01
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#define BD718XX_BUCK_RUN_ON 0x04
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/* Generic LDO masks */
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#define BD718XX_LDO_SEL 0x80
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#define BD718XX_LDO_EN 0x40
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/* BD71837 BUCK ramp rate CTRL reg bits */
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#define BUCK_RAMPRATE_MASK 0xC0
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#define BUCK_RAMPRATE_10P00MV 0x0
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#define BUCK_RAMPRATE_5P00MV 0x1
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#define BUCK_RAMPRATE_2P50MV 0x2
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#define BUCK_RAMPRATE_1P25MV 0x3
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#define DVS_BUCK_RUN_MASK 0x3F
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#define DVS_BUCK_SUSP_MASK 0x3F
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#define DVS_BUCK_IDLE_MASK 0x3F
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#define BD718XX_1ST_NODVS_BUCK_MASK 0x07
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#define BD718XX_3RD_NODVS_BUCK_MASK 0x07
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#define BD718XX_4TH_NODVS_BUCK_MASK 0x3F
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#define BD71847_BUCK3_MASK 0x07
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#define BD71847_BUCK3_RANGE_MASK 0xC0
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#define BD71847_BUCK4_MASK 0x03
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#define BD71847_BUCK4_RANGE_MASK 0x40
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#define BD71837_BUCK5_MASK 0x07
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#define BD71837_BUCK5_RANGE_MASK 0x80
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#define BD71837_BUCK6_MASK 0x03
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#define BD718XX_LDO1_MASK 0x03
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#define BD718XX_LDO1_RANGE_MASK 0x20
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#define BD718XX_LDO2_MASK 0x20
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#define BD718XX_LDO3_MASK 0x0F
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#define BD718XX_LDO4_MASK 0x0F
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#define BD718XX_LDO6_MASK 0x0F
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#define BD71837_LDO5_MASK 0x0F
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#define BD71847_LDO5_MASK 0x0F
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#define BD71847_LDO5_RANGE_MASK 0x20
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#define BD71837_LDO7_MASK 0x0F
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/* BD718XX Voltage monitoring masks */
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#define BD718XX_BUCK1_VRMON80 0x1
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#define BD718XX_BUCK1_VRMON130 0x2
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#define BD718XX_BUCK2_VRMON80 0x4
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#define BD718XX_BUCK2_VRMON130 0x8
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#define BD718XX_1ST_NODVS_BUCK_VRMON80 0x1
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#define BD718XX_1ST_NODVS_BUCK_VRMON130 0x2
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#define BD718XX_2ND_NODVS_BUCK_VRMON80 0x4
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#define BD718XX_2ND_NODVS_BUCK_VRMON130 0x8
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#define BD718XX_3RD_NODVS_BUCK_VRMON80 0x10
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#define BD718XX_3RD_NODVS_BUCK_VRMON130 0x20
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#define BD718XX_4TH_NODVS_BUCK_VRMON80 0x40
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#define BD718XX_4TH_NODVS_BUCK_VRMON130 0x80
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#define BD718XX_LDO1_VRMON80 0x1
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#define BD718XX_LDO2_VRMON80 0x2
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#define BD718XX_LDO3_VRMON80 0x4
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#define BD718XX_LDO4_VRMON80 0x8
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#define BD718XX_LDO5_VRMON80 0x10
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#define BD718XX_LDO6_VRMON80 0x20
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/* BD71837 specific voltage monitoring masks */
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#define BD71837_BUCK3_VRMON80 0x10
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#define BD71837_BUCK3_VRMON130 0x20
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#define BD71837_BUCK4_VRMON80 0x40
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#define BD71837_BUCK4_VRMON130 0x80
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#define BD71837_LDO7_VRMON80 0x40
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/* BD718XX_REG_IRQ bits */
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#define IRQ_SWRST 0x40
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#define IRQ_PWRON_S 0x20
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#define IRQ_PWRON_L 0x10
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#define IRQ_PWRON 0x08
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#define IRQ_WDOG 0x04
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#define IRQ_ON_REQ 0x02
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#define IRQ_STBY_REQ 0x01
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/* ROHM BD718XX irqs */
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enum {
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BD718XX_INT_STBY_REQ,
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BD718XX_INT_ON_REQ,
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BD718XX_INT_WDOG,
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BD718XX_INT_PWRBTN,
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BD718XX_INT_PWRBTN_L,
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BD718XX_INT_PWRBTN_S,
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BD718XX_INT_SWRST
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};
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/* ROHM BD718XX interrupt masks */
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#define BD718XX_INT_SWRST_MASK 0x40
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#define BD718XX_INT_PWRBTN_S_MASK 0x20
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#define BD718XX_INT_PWRBTN_L_MASK 0x10
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#define BD718XX_INT_PWRBTN_MASK 0x8
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#define BD718XX_INT_WDOG_MASK 0x4
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#define BD718XX_INT_ON_REQ_MASK 0x2
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#define BD718XX_INT_STBY_REQ_MASK 0x1
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/* Register write induced reset settings */
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/*
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* Even though the bit zero is not SWRESET type we still want to write zero
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* to it when changing type. Bit zero is 'SWRESET' trigger bit and if we
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* write 1 to it we will trigger the action. So always write 0 to it when
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* changning SWRESET action - no matter what we read from it.
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*/
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#define BD718XX_SWRESET_TYPE_MASK 7
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#define BD718XX_SWRESET_TYPE_DISABLED 0
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#define BD718XX_SWRESET_TYPE_COLD 4
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#define BD718XX_SWRESET_TYPE_WARM 6
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#define BD718XX_SWRESET_RESET_MASK 1
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#define BD718XX_SWRESET_RESET 1
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/* Poweroff state transition conditions */
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#define BD718XX_ON_REQ_POWEROFF_MASK 1
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#define BD718XX_SWRESET_POWEROFF_MASK 2
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#define BD718XX_WDOG_POWEROFF_MASK 4
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#define BD718XX_KEY_L_POWEROFF_MASK 8
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#define BD718XX_POWOFF_TO_SNVS 0
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#define BD718XX_POWOFF_TO_RDY 0xF
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#define BD718XX_POWOFF_TIME_MASK 0xF0
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enum {
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BD718XX_POWOFF_TIME_5MS = 0,
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BD718XX_POWOFF_TIME_10MS,
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BD718XX_POWOFF_TIME_15MS,
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BD718XX_POWOFF_TIME_20MS,
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BD718XX_POWOFF_TIME_25MS,
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BD718XX_POWOFF_TIME_30MS,
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BD718XX_POWOFF_TIME_35MS,
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BD718XX_POWOFF_TIME_40MS,
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BD718XX_POWOFF_TIME_45MS,
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BD718XX_POWOFF_TIME_50MS,
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BD718XX_POWOFF_TIME_75MS,
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BD718XX_POWOFF_TIME_100MS,
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BD718XX_POWOFF_TIME_250MS,
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BD718XX_POWOFF_TIME_500MS,
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BD718XX_POWOFF_TIME_750MS,
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BD718XX_POWOFF_TIME_1500MS
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};
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/* Poweron sequence state transition conditions */
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#define BD718XX_RDY_TO_SNVS_MASK 0xF
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#define BD718XX_SNVS_TO_RUN_MASK 0xF0
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#define BD718XX_PWR_TRIG_KEY_L 1
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#define BD718XX_PWR_TRIG_KEY_S 2
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#define BD718XX_PWR_TRIG_PMIC_ON 4
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#define BD718XX_PWR_TRIG_VSYS_UVLO 8
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#define BD718XX_RDY_TO_SNVS_SIFT 0
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#define BD718XX_SNVS_TO_RUN_SIFT 4
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#define BD718XX_PWRBTN_PRESS_DURATION_MASK 0xF
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/* Timeout value for detecting short press */
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enum {
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BD718XX_PWRBTN_SHORT_PRESS_10MS = 0,
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BD718XX_PWRBTN_SHORT_PRESS_500MS,
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BD718XX_PWRBTN_SHORT_PRESS_1000MS,
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BD718XX_PWRBTN_SHORT_PRESS_1500MS,
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BD718XX_PWRBTN_SHORT_PRESS_2000MS,
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BD718XX_PWRBTN_SHORT_PRESS_2500MS,
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BD718XX_PWRBTN_SHORT_PRESS_3000MS,
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BD718XX_PWRBTN_SHORT_PRESS_3500MS,
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BD718XX_PWRBTN_SHORT_PRESS_4000MS,
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BD718XX_PWRBTN_SHORT_PRESS_4500MS,
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BD718XX_PWRBTN_SHORT_PRESS_5000MS,
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BD718XX_PWRBTN_SHORT_PRESS_5500MS,
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BD718XX_PWRBTN_SHORT_PRESS_6000MS,
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BD718XX_PWRBTN_SHORT_PRESS_6500MS,
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BD718XX_PWRBTN_SHORT_PRESS_7000MS,
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BD718XX_PWRBTN_SHORT_PRESS_7500MS
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};
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/* Timeout value for detecting LONG press */
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enum {
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BD718XX_PWRBTN_LONG_PRESS_10MS = 0,
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BD718XX_PWRBTN_LONG_PRESS_1S,
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BD718XX_PWRBTN_LONG_PRESS_2S,
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BD718XX_PWRBTN_LONG_PRESS_3S,
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BD718XX_PWRBTN_LONG_PRESS_4S,
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BD718XX_PWRBTN_LONG_PRESS_5S,
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BD718XX_PWRBTN_LONG_PRESS_6S,
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BD718XX_PWRBTN_LONG_PRESS_7S,
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BD718XX_PWRBTN_LONG_PRESS_8S,
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BD718XX_PWRBTN_LONG_PRESS_9S,
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BD718XX_PWRBTN_LONG_PRESS_10S,
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BD718XX_PWRBTN_LONG_PRESS_11S,
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BD718XX_PWRBTN_LONG_PRESS_12S,
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BD718XX_PWRBTN_LONG_PRESS_13S,
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BD718XX_PWRBTN_LONG_PRESS_14S,
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BD718XX_PWRBTN_LONG_PRESS_15S
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};
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#endif /* __LINUX_MFD_BD718XX_H__ */
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