359 lines
11 KiB
C
359 lines
11 KiB
C
/* SPDX-License-Identifier: GPL-2.0 WITH Linux-syscall-note */
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/*
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* Copyright (C) 2019 Western Digital Corporation or its affiliates.
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*
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* Authors:
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* Anup Patel <anup.patel@wdc.com>
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*/
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#ifndef __LINUX_KVM_RISCV_H
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#define __LINUX_KVM_RISCV_H
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#ifndef __ASSEMBLY__
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#include <linux/types.h>
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#include <asm/bitsperlong.h>
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#include <asm/ptrace.h>
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#define __KVM_HAVE_IRQ_LINE
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#define KVM_COALESCED_MMIO_PAGE_OFFSET 1
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#define KVM_INTERRUPT_SET -1U
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#define KVM_INTERRUPT_UNSET -2U
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/* for KVM_GET_REGS and KVM_SET_REGS */
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struct kvm_regs {
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};
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/* for KVM_GET_FPU and KVM_SET_FPU */
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struct kvm_fpu {
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};
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/* KVM Debug exit structure */
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struct kvm_debug_exit_arch {
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};
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/* for KVM_SET_GUEST_DEBUG */
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struct kvm_guest_debug_arch {
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};
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/* definition of registers in kvm_run */
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struct kvm_sync_regs {
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};
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/* for KVM_GET_SREGS and KVM_SET_SREGS */
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struct kvm_sregs {
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};
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/* CONFIG registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_config {
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unsigned long isa;
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unsigned long zicbom_block_size;
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unsigned long mvendorid;
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unsigned long marchid;
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unsigned long mimpid;
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unsigned long zicboz_block_size;
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unsigned long satp_mode;
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};
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/* CORE registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_core {
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struct user_regs_struct regs;
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unsigned long mode;
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};
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/* Possible privilege modes for kvm_riscv_core */
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#define KVM_RISCV_MODE_S 1
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#define KVM_RISCV_MODE_U 0
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/* General CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_csr {
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unsigned long sstatus;
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unsigned long sie;
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unsigned long stvec;
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unsigned long sscratch;
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unsigned long sepc;
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unsigned long scause;
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unsigned long stval;
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unsigned long sip;
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unsigned long satp;
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unsigned long scounteren;
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unsigned long senvcfg;
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};
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/* AIA CSR registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_aia_csr {
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unsigned long siselect;
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unsigned long iprio1;
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unsigned long iprio2;
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unsigned long sieh;
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unsigned long siph;
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unsigned long iprio1h;
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unsigned long iprio2h;
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};
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/* Smstateen CSR for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_smstateen_csr {
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unsigned long sstateen0;
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};
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/* TIMER registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_timer {
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__u64 frequency;
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__u64 time;
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__u64 compare;
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__u64 state;
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};
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/*
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* ISA extension IDs specific to KVM. This is not the same as the host ISA
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* extension IDs as that is internal to the host and should not be exposed
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* to the guest. This should always be contiguous to keep the mapping simple
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* in KVM implementation.
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*/
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enum KVM_RISCV_ISA_EXT_ID {
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KVM_RISCV_ISA_EXT_A = 0,
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KVM_RISCV_ISA_EXT_C,
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KVM_RISCV_ISA_EXT_D,
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KVM_RISCV_ISA_EXT_F,
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KVM_RISCV_ISA_EXT_H,
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KVM_RISCV_ISA_EXT_I,
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KVM_RISCV_ISA_EXT_M,
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KVM_RISCV_ISA_EXT_SVPBMT,
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KVM_RISCV_ISA_EXT_SSTC,
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KVM_RISCV_ISA_EXT_SVINVAL,
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KVM_RISCV_ISA_EXT_ZIHINTPAUSE,
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KVM_RISCV_ISA_EXT_ZICBOM,
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KVM_RISCV_ISA_EXT_ZICBOZ,
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KVM_RISCV_ISA_EXT_ZBB,
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KVM_RISCV_ISA_EXT_SSAIA,
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KVM_RISCV_ISA_EXT_V,
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KVM_RISCV_ISA_EXT_SVNAPOT,
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KVM_RISCV_ISA_EXT_ZBA,
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KVM_RISCV_ISA_EXT_ZBS,
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KVM_RISCV_ISA_EXT_ZICNTR,
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KVM_RISCV_ISA_EXT_ZICSR,
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KVM_RISCV_ISA_EXT_ZIFENCEI,
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KVM_RISCV_ISA_EXT_ZIHPM,
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KVM_RISCV_ISA_EXT_SMSTATEEN,
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KVM_RISCV_ISA_EXT_ZICOND,
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KVM_RISCV_ISA_EXT_ZBC,
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KVM_RISCV_ISA_EXT_ZBKB,
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KVM_RISCV_ISA_EXT_ZBKC,
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KVM_RISCV_ISA_EXT_ZBKX,
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KVM_RISCV_ISA_EXT_ZKND,
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KVM_RISCV_ISA_EXT_ZKNE,
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KVM_RISCV_ISA_EXT_ZKNH,
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KVM_RISCV_ISA_EXT_ZKR,
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KVM_RISCV_ISA_EXT_ZKSED,
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KVM_RISCV_ISA_EXT_ZKSH,
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KVM_RISCV_ISA_EXT_ZKT,
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KVM_RISCV_ISA_EXT_ZVBB,
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KVM_RISCV_ISA_EXT_ZVBC,
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KVM_RISCV_ISA_EXT_ZVKB,
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KVM_RISCV_ISA_EXT_ZVKG,
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KVM_RISCV_ISA_EXT_ZVKNED,
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KVM_RISCV_ISA_EXT_ZVKNHA,
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KVM_RISCV_ISA_EXT_ZVKNHB,
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KVM_RISCV_ISA_EXT_ZVKSED,
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KVM_RISCV_ISA_EXT_ZVKSH,
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KVM_RISCV_ISA_EXT_ZVKT,
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KVM_RISCV_ISA_EXT_ZFH,
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KVM_RISCV_ISA_EXT_ZFHMIN,
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KVM_RISCV_ISA_EXT_ZIHINTNTL,
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KVM_RISCV_ISA_EXT_ZVFH,
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KVM_RISCV_ISA_EXT_ZVFHMIN,
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KVM_RISCV_ISA_EXT_ZFA,
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KVM_RISCV_ISA_EXT_ZTSO,
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KVM_RISCV_ISA_EXT_ZACAS,
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KVM_RISCV_ISA_EXT_MAX,
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};
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/*
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* SBI extension IDs specific to KVM. This is not the same as the SBI
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* extension IDs defined by the RISC-V SBI specification.
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*/
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enum KVM_RISCV_SBI_EXT_ID {
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KVM_RISCV_SBI_EXT_V01 = 0,
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KVM_RISCV_SBI_EXT_TIME,
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KVM_RISCV_SBI_EXT_IPI,
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KVM_RISCV_SBI_EXT_RFENCE,
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KVM_RISCV_SBI_EXT_SRST,
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KVM_RISCV_SBI_EXT_HSM,
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KVM_RISCV_SBI_EXT_PMU,
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KVM_RISCV_SBI_EXT_EXPERIMENTAL,
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KVM_RISCV_SBI_EXT_VENDOR,
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KVM_RISCV_SBI_EXT_DBCN,
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KVM_RISCV_SBI_EXT_STA,
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KVM_RISCV_SBI_EXT_MAX,
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};
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/* SBI STA extension registers for KVM_GET_ONE_REG and KVM_SET_ONE_REG */
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struct kvm_riscv_sbi_sta {
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unsigned long shmem_lo;
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unsigned long shmem_hi;
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};
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/* Possible states for kvm_riscv_timer */
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#define KVM_RISCV_TIMER_STATE_OFF 0
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#define KVM_RISCV_TIMER_STATE_ON 1
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#define KVM_REG_SIZE(id) \
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(1U << (((id) & KVM_REG_SIZE_MASK) >> KVM_REG_SIZE_SHIFT))
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/* If you need to interpret the index values, here is the key: */
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#define KVM_REG_RISCV_TYPE_MASK 0x00000000FF000000
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#define KVM_REG_RISCV_TYPE_SHIFT 24
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#define KVM_REG_RISCV_SUBTYPE_MASK 0x0000000000FF0000
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#define KVM_REG_RISCV_SUBTYPE_SHIFT 16
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/* Config registers are mapped as type 1 */
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#define KVM_REG_RISCV_CONFIG (0x01 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CONFIG_REG(name) \
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(offsetof(struct kvm_riscv_config, name) / sizeof(unsigned long))
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/* Core registers are mapped as type 2 */
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#define KVM_REG_RISCV_CORE (0x02 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CORE_REG(name) \
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(offsetof(struct kvm_riscv_core, name) / sizeof(unsigned long))
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/* Control and status registers are mapped as type 3 */
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#define KVM_REG_RISCV_CSR (0x03 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_CSR_GENERAL (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_CSR_AIA (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_CSR_SMSTATEEN (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_CSR_REG(name) \
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(offsetof(struct kvm_riscv_csr, name) / sizeof(unsigned long))
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#define KVM_REG_RISCV_CSR_AIA_REG(name) \
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(offsetof(struct kvm_riscv_aia_csr, name) / sizeof(unsigned long))
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#define KVM_REG_RISCV_CSR_SMSTATEEN_REG(name) \
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(offsetof(struct kvm_riscv_smstateen_csr, name) / sizeof(unsigned long))
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/* Timer registers are mapped as type 4 */
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#define KVM_REG_RISCV_TIMER (0x04 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_TIMER_REG(name) \
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(offsetof(struct kvm_riscv_timer, name) / sizeof(__u64))
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/* F extension registers are mapped as type 5 */
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#define KVM_REG_RISCV_FP_F (0x05 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_FP_F_REG(name) \
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(offsetof(struct __riscv_f_ext_state, name) / sizeof(__u32))
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/* D extension registers are mapped as type 6 */
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#define KVM_REG_RISCV_FP_D (0x06 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_FP_D_REG(name) \
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(offsetof(struct __riscv_d_ext_state, name) / sizeof(__u64))
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/* ISA Extension registers are mapped as type 7 */
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#define KVM_REG_RISCV_ISA_EXT (0x07 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_ISA_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_ISA_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_ISA_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_ISA_MULTI_REG(__ext_id) \
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((__ext_id) / __BITS_PER_LONG)
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#define KVM_REG_RISCV_ISA_MULTI_MASK(__ext_id) \
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(1UL << ((__ext_id) % __BITS_PER_LONG))
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#define KVM_REG_RISCV_ISA_MULTI_REG_LAST \
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KVM_REG_RISCV_ISA_MULTI_REG(KVM_RISCV_ISA_EXT_MAX - 1)
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/* SBI extension registers are mapped as type 8 */
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#define KVM_REG_RISCV_SBI_EXT (0x08 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_SBI_SINGLE (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_SBI_MULTI_EN (0x1 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_SBI_MULTI_DIS (0x2 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_SBI_MULTI_REG(__ext_id) \
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((__ext_id) / __BITS_PER_LONG)
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#define KVM_REG_RISCV_SBI_MULTI_MASK(__ext_id) \
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(1UL << ((__ext_id) % __BITS_PER_LONG))
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#define KVM_REG_RISCV_SBI_MULTI_REG_LAST \
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KVM_REG_RISCV_SBI_MULTI_REG(KVM_RISCV_SBI_EXT_MAX - 1)
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/* V extension registers are mapped as type 9 */
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#define KVM_REG_RISCV_VECTOR (0x09 << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_VECTOR_CSR_REG(name) \
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(offsetof(struct __riscv_v_ext_state, name) / sizeof(unsigned long))
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#define KVM_REG_RISCV_VECTOR_REG(n) \
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((n) + sizeof(struct __riscv_v_ext_state) / sizeof(unsigned long))
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/* Registers for specific SBI extensions are mapped as type 10 */
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#define KVM_REG_RISCV_SBI_STATE (0x0a << KVM_REG_RISCV_TYPE_SHIFT)
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#define KVM_REG_RISCV_SBI_STA (0x0 << KVM_REG_RISCV_SUBTYPE_SHIFT)
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#define KVM_REG_RISCV_SBI_STA_REG(name) \
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(offsetof(struct kvm_riscv_sbi_sta, name) / sizeof(unsigned long))
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/* Device Control API: RISC-V AIA */
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#define KVM_DEV_RISCV_APLIC_ALIGN 0x1000
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#define KVM_DEV_RISCV_APLIC_SIZE 0x4000
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#define KVM_DEV_RISCV_APLIC_MAX_HARTS 0x4000
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#define KVM_DEV_RISCV_IMSIC_ALIGN 0x1000
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#define KVM_DEV_RISCV_IMSIC_SIZE 0x1000
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#define KVM_DEV_RISCV_AIA_GRP_CONFIG 0
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#define KVM_DEV_RISCV_AIA_CONFIG_MODE 0
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#define KVM_DEV_RISCV_AIA_CONFIG_IDS 1
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#define KVM_DEV_RISCV_AIA_CONFIG_SRCS 2
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#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_BITS 3
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#define KVM_DEV_RISCV_AIA_CONFIG_GROUP_SHIFT 4
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#define KVM_DEV_RISCV_AIA_CONFIG_HART_BITS 5
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#define KVM_DEV_RISCV_AIA_CONFIG_GUEST_BITS 6
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/*
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* Modes of RISC-V AIA device:
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* 1) EMUL (aka Emulation): Trap-n-emulate IMSIC
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* 2) HWACCEL (aka HW Acceleration): Virtualize IMSIC using IMSIC guest files
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* 3) AUTO (aka Automatic): Virtualize IMSIC using IMSIC guest files whenever
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* available otherwise fallback to trap-n-emulation
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*/
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#define KVM_DEV_RISCV_AIA_MODE_EMUL 0
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#define KVM_DEV_RISCV_AIA_MODE_HWACCEL 1
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#define KVM_DEV_RISCV_AIA_MODE_AUTO 2
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#define KVM_DEV_RISCV_AIA_IDS_MIN 63
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#define KVM_DEV_RISCV_AIA_IDS_MAX 2048
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#define KVM_DEV_RISCV_AIA_SRCS_MAX 1024
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#define KVM_DEV_RISCV_AIA_GROUP_BITS_MAX 8
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#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MIN 24
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#define KVM_DEV_RISCV_AIA_GROUP_SHIFT_MAX 56
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#define KVM_DEV_RISCV_AIA_HART_BITS_MAX 16
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#define KVM_DEV_RISCV_AIA_GUEST_BITS_MAX 8
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#define KVM_DEV_RISCV_AIA_GRP_ADDR 1
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#define KVM_DEV_RISCV_AIA_ADDR_APLIC 0
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#define KVM_DEV_RISCV_AIA_ADDR_IMSIC(__vcpu) (1 + (__vcpu))
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#define KVM_DEV_RISCV_AIA_ADDR_MAX \
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(1 + KVM_DEV_RISCV_APLIC_MAX_HARTS)
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#define KVM_DEV_RISCV_AIA_GRP_CTRL 2
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#define KVM_DEV_RISCV_AIA_CTRL_INIT 0
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/*
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* The device attribute type contains the memory mapped offset of the
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* APLIC register (range 0x0000-0x3FFF) and it must be 4-byte aligned.
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*/
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#define KVM_DEV_RISCV_AIA_GRP_APLIC 3
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/*
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* The lower 12-bits of the device attribute type contains the iselect
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* value of the IMSIC register (range 0x70-0xFF) whereas the higher order
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* bits contains the VCPU id.
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*/
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#define KVM_DEV_RISCV_AIA_GRP_IMSIC 4
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#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS 12
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#define KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK \
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((1U << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) - 1)
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#define KVM_DEV_RISCV_AIA_IMSIC_MKATTR(__vcpu, __isel) \
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(((__vcpu) << KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS) | \
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((__isel) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK))
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#define KVM_DEV_RISCV_AIA_IMSIC_GET_ISEL(__attr) \
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((__attr) & KVM_DEV_RISCV_AIA_IMSIC_ISEL_MASK)
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#define KVM_DEV_RISCV_AIA_IMSIC_GET_VCPU(__attr) \
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((__attr) >> KVM_DEV_RISCV_AIA_IMSIC_ISEL_BITS)
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/* One single KVM irqchip, ie. the AIA */
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#define KVM_NR_IRQCHIPS 1
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#endif
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#endif /* __LINUX_KVM_RISCV_H */
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