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![Mike Rapoport](/assets/img/avatar_default.png)
Patch series "mm: cleanup usage of <asm/pgalloc.h>" Most architectures have very similar versions of pXd_alloc_one() and pXd_free_one() for intermediate levels of page table. These patches add generic versions of these functions in <asm-generic/pgalloc.h> and enable use of the generic functions where appropriate. In addition, functions declared and defined in <asm/pgalloc.h> headers are used mostly by core mm and early mm initialization in arch and there is no actual reason to have the <asm/pgalloc.h> included all over the place. The first patch in this series removes unneeded includes of <asm/pgalloc.h> In the end it didn't work out as neatly as I hoped and moving pXd_alloc_track() definitions to <asm-generic/pgalloc.h> would require unnecessary changes to arches that have custom page table allocations, so I've decided to move lib/ioremap.c to mm/ and make pgalloc-track.h local to mm/. This patch (of 8): In most cases <asm/pgalloc.h> header is required only for allocations of page table memory. Most of the .c files that include that header do not use symbols declared in <asm/pgalloc.h> and do not require that header. As for the other header files that used to include <asm/pgalloc.h>, it is possible to move that include into the .c file that actually uses symbols from <asm/pgalloc.h> and drop the include from the header file. The process was somewhat automated using sed -i -E '/[<"]asm\/pgalloc\.h/d' \ $(grep -L -w -f /tmp/xx \ $(git grep -E -l '[<"]asm/pgalloc\.h')) where /tmp/xx contains all the symbols defined in arch/*/include/asm/pgalloc.h. [rppt@linux.ibm.com: fix powerpc warning] Signed-off-by: Mike Rapoport <rppt@linux.ibm.com> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Reviewed-by: Pekka Enberg <penberg@kernel.org> Acked-by: Geert Uytterhoeven <geert@linux-m68k.org> [m68k] Cc: Abdul Haleem <abdhalee@linux.vnet.ibm.com> Cc: Andy Lutomirski <luto@kernel.org> Cc: Arnd Bergmann <arnd@arndb.de> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Joerg Roedel <joro@8bytes.org> Cc: Max Filippov <jcmvbkbc@gmail.com> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Satheesh Rajendran <sathnaga@linux.vnet.ibm.com> Cc: Stafford Horne <shorne@gmail.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Cc: Steven Rostedt <rostedt@goodmis.org> Cc: Joerg Roedel <jroedel@suse.de> Cc: Matthew Wilcox <willy@infradead.org> Link: http://lkml.kernel.org/r/20200627143453.31835-1-rppt@kernel.org Link: http://lkml.kernel.org/r/20200627143453.31835-2-rppt@kernel.org Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
193 lines
5 KiB
C
193 lines
5 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* linux/arch/m68k/mm/memory.c
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*
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* Copyright (C) 1995 Hamish Macdonald
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*/
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#include <linux/module.h>
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#include <linux/mm.h>
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#include <linux/kernel.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/init.h>
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#include <linux/pagemap.h>
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#include <linux/gfp.h>
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#include <asm/setup.h>
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#include <asm/segment.h>
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#include <asm/page.h>
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#include <asm/traps.h>
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#include <asm/machdep.h>
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/* invalidate page in both caches */
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static inline void clear040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cinvp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* invalidate page in i-cache */
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static inline void cleari040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cinvp %%ic,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* push page in both caches */
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/* RZ: cpush %bc DOES invalidate %ic, regardless of DPI */
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static inline void push040(unsigned long paddr)
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{
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asm volatile (
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"nop\n\t"
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".chip 68040\n\t"
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"cpushp %%bc,(%0)\n\t"
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".chip 68k"
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: : "a" (paddr));
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}
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/* push and invalidate page in both caches, must disable ints
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* to avoid invalidating valid data */
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static inline void pushcl040(unsigned long paddr)
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{
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unsigned long flags;
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local_irq_save(flags);
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push040(paddr);
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if (CPU_IS_060)
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clear040(paddr);
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local_irq_restore(flags);
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}
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/*
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* 040: Hit every page containing an address in the range paddr..paddr+len-1.
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* (Low order bits of the ea of a CINVP/CPUSHP are "don't care"s).
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* Hit every page until there is a page or less to go. Hit the next page,
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* and the one after that if the range hits it.
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*/
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/* ++roman: A little bit more care is required here: The CINVP instruction
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* invalidates cache entries WITHOUT WRITING DIRTY DATA BACK! So the beginning
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* and the end of the region must be treated differently if they are not
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* exactly at the beginning or end of a page boundary. Else, maybe too much
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* data becomes invalidated and thus lost forever. CPUSHP does what we need:
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* it invalidates the page after pushing dirty data to memory. (Thanks to Jes
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* for discovering the problem!)
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*/
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/* ... but on the '060, CPUSH doesn't invalidate (for us, since we have set
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* the DPI bit in the CACR; would it cause problems with temporarily changing
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* this?). So we have to push first and then additionally to invalidate.
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*/
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/*
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* cache_clear() semantics: Clear any cache entries for the area in question,
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* without writing back dirty entries first. This is useful if the data will
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* be overwritten anyway, e.g. by DMA to memory. The range is defined by a
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* _physical_ address.
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*/
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void cache_clear (unsigned long paddr, int len)
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{
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if (CPU_IS_COLDFIRE) {
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clear_cf_bcache(0, DCACHE_MAX_ADDR);
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} else if (CPU_IS_040_OR_060) {
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int tmp;
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/*
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* We need special treatment for the first page, in case it
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* is not page-aligned. Page align the addresses to work
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* around bug I17 in the 68060.
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*/
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if ((tmp = -paddr & (PAGE_SIZE - 1))) {
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pushcl040(paddr & PAGE_MASK);
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if ((len -= tmp) <= 0)
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return;
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paddr += tmp;
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}
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tmp = PAGE_SIZE;
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paddr &= PAGE_MASK;
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while ((len -= tmp) >= 0) {
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clear040(paddr);
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paddr += tmp;
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}
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if ((len += tmp))
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/* a page boundary gets crossed at the end */
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pushcl040(paddr);
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}
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else /* 68030 or 68020 */
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asm volatile ("movec %/cacr,%/d0\n\t"
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"oriw %0,%/d0\n\t"
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"movec %/d0,%/cacr"
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: : "i" (FLUSH_I_AND_D)
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: "d0");
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#ifdef CONFIG_M68K_L2_CACHE
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if(mach_l2_flush)
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mach_l2_flush(0);
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#endif
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}
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EXPORT_SYMBOL(cache_clear);
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/*
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* cache_push() semantics: Write back any dirty cache data in the given area,
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* and invalidate the range in the instruction cache. It needs not (but may)
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* invalidate those entries also in the data cache. The range is defined by a
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* _physical_ address.
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*/
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void cache_push (unsigned long paddr, int len)
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{
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if (CPU_IS_COLDFIRE) {
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flush_cf_bcache(0, DCACHE_MAX_ADDR);
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} else if (CPU_IS_040_OR_060) {
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int tmp = PAGE_SIZE;
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/*
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* on 68040 or 68060, push cache lines for pages in the range;
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* on the '040 this also invalidates the pushed lines, but not on
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* the '060!
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*/
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len += paddr & (PAGE_SIZE - 1);
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/*
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* Work around bug I17 in the 68060 affecting some instruction
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* lines not being invalidated properly.
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*/
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paddr &= PAGE_MASK;
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do {
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push040(paddr);
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paddr += tmp;
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} while ((len -= tmp) > 0);
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}
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/*
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* 68030/68020 have no writeback cache. On the other hand,
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* cache_push is actually a superset of cache_clear (the lines
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* get written back and invalidated), so we should make sure
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* to perform the corresponding actions. After all, this is getting
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* called in places where we've just loaded code, or whatever, so
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* flushing the icache is appropriate; flushing the dcache shouldn't
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* be required.
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*/
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else /* 68030 or 68020 */
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asm volatile ("movec %/cacr,%/d0\n\t"
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"oriw %0,%/d0\n\t"
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"movec %/d0,%/cacr"
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: : "i" (FLUSH_I)
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: "d0");
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#ifdef CONFIG_M68K_L2_CACHE
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if(mach_l2_flush)
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mach_l2_flush(1);
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#endif
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}
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EXPORT_SYMBOL(cache_push);
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