Christoph Hellwig 4f9bbcefa1 riscv: add support for MMIO access to the timer registers ... When running in M-mode we can't use the SBI to set the timer, and don't have access to the time CSR as that usually is emulated by M-mode. Instead provide code that directly accesses the MMIO for the timer. Signed-off-by: Christoph Hellwig <hch@lst.de> Reviewed-by: Anup Patel <anup@brainfault.org> Acked-by: Thomas Gleixner <tglx@linutronix.de> # for drivers/clocksource [paul.walmsley@sifive.com: updated to apply; fixed checkpatch issue; timex.h now includes asm/mmio.h to resolve header file problems] Signed-off-by: Paul Walmsley <paul.walmsley@sifive.com>		2019-11-13 14:10:40 -08:00
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asm	riscv: add support for MMIO access to the timer registers	2019-11-13 14:10:40 -08:00
uapi/asm	riscv: Add support for perf registers sampling	2019-09-05 00:48:58 -07:00