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502a0c775c
pt_regs->event was set with artificial values to identify the low level
system event (syscall trap / breakpoint trap / exceptions / interrupts)
With r8 saving out of the way, the full word can be used to save real
ECR (Exception Cause Register) which helps idenify the event naturally,
including additional info such as cause code, param.
Only for Interrupts, where ECR is not applicable, do we resort to
synthetic non ECR values.
SAVE_ALL_TRAP/EXCEPTIONS can now be merged as they both use ECR with
different runtime values.
The ptrace helpers now use the sub-fields of ECR to distinguish the
events (e.g. vector 0x25 is trap, param 0 is syscall...)
The following benefits will follow:
(1) This centralizes the location of where ECR is saved and will allow
the cleanup of task->thread.cause_code ECR placeholder which is set
in non-uniform way. Then ARC VM code can safely rely on it being
there for purpose of finer grained VM_EXEC dcache flush (based on
exec fault: I-TLB Miss)
(2) Further, ECR being passed around from low level handlers as arg can
be eliminated as it is part of standard reg-file in pt_regs
Signed-off-by: Vineet Gupta <vgupta@synopsys.com>
326 lines
7.8 KiB
C
326 lines
7.8 KiB
C
/*
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* Copyright (C) 2004, 2007-2010, 2011-2012 Synopsys, Inc. (www.synopsys.com)
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*/
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#ifndef _ASM_ARC_ARCREGS_H
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#define _ASM_ARC_ARCREGS_H
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#ifdef __KERNEL__
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/* Build Configuration Registers */
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#define ARC_REG_DCCMBASE_BCR 0x61 /* DCCM Base Addr */
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#define ARC_REG_CRC_BCR 0x62
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#define ARC_REG_DVFB_BCR 0x64
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#define ARC_REG_EXTARITH_BCR 0x65
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#define ARC_REG_VECBASE_BCR 0x68
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#define ARC_REG_PERIBASE_BCR 0x69
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#define ARC_REG_FP_BCR 0x6B /* Single-Precision FPU */
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#define ARC_REG_DPFP_BCR 0x6C /* Dbl Precision FPU */
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#define ARC_REG_DCCM_BCR 0x74 /* DCCM Present + SZ */
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#define ARC_REG_TIMERS_BCR 0x75
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#define ARC_REG_ICCM_BCR 0x78
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#define ARC_REG_XY_MEM_BCR 0x79
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#define ARC_REG_MAC_BCR 0x7a
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#define ARC_REG_MUL_BCR 0x7b
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#define ARC_REG_SWAP_BCR 0x7c
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#define ARC_REG_NORM_BCR 0x7d
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#define ARC_REG_MIXMAX_BCR 0x7e
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#define ARC_REG_BARREL_BCR 0x7f
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#define ARC_REG_D_UNCACH_BCR 0x6A
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/* status32 Bits Positions */
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#define STATUS_AE_BIT 5 /* Exception active */
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#define STATUS_DE_BIT 6 /* PC is in delay slot */
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#define STATUS_U_BIT 7 /* User/Kernel mode */
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#define STATUS_L_BIT 12 /* Loop inhibit */
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/* These masks correspond to the status word(STATUS_32) bits */
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#define STATUS_AE_MASK (1<<STATUS_AE_BIT)
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#define STATUS_DE_MASK (1<<STATUS_DE_BIT)
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#define STATUS_U_MASK (1<<STATUS_U_BIT)
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#define STATUS_L_MASK (1<<STATUS_L_BIT)
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/*
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* ECR: Exception Cause Reg bits-n-pieces
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* [23:16] = Exception Vector
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* [15: 8] = Exception Cause Code
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* [ 7: 0] = Exception Parameters (for certain types only)
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*/
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#define ECR_VEC_MASK 0xff0000
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#define ECR_CODE_MASK 0x00ff00
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#define ECR_PARAM_MASK 0x0000ff
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/* Exception Cause Vector Values */
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#define ECR_V_INSN_ERR 0x02
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#define ECR_V_MACH_CHK 0x20
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#define ECR_V_ITLB_MISS 0x21
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#define ECR_V_DTLB_MISS 0x22
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#define ECR_V_PROTV 0x23
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#define ECR_V_TRAP 0x25
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/* Protection Violation Exception Cause Code Values */
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#define ECR_C_PROTV_INST_FETCH 0x00
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#define ECR_C_PROTV_LOAD 0x01
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#define ECR_C_PROTV_STORE 0x02
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#define ECR_C_PROTV_XCHG 0x03
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#define ECR_C_PROTV_MISALIG_DATA 0x04
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#define ECR_C_BIT_PROTV_MISALIG_DATA 10
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/* Machine Check Cause Code Values */
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#define ECR_C_MCHK_DUP_TLB 0x01
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/* DTLB Miss Exception Cause Code Values */
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#define ECR_C_BIT_DTLB_LD_MISS 8
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#define ECR_C_BIT_DTLB_ST_MISS 9
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/* Dummy ECR values for Interrupts */
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#define event_IRQ1 0x0031abcd
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#define event_IRQ2 0x0032abcd
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/* Auxiliary registers */
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#define AUX_IDENTITY 4
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#define AUX_INTR_VEC_BASE 0x25
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/*
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* Floating Pt Registers
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* Status regs are read-only (build-time) so need not be saved/restored
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*/
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#define ARC_AUX_FP_STAT 0x300
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#define ARC_AUX_DPFP_1L 0x301
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#define ARC_AUX_DPFP_1H 0x302
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#define ARC_AUX_DPFP_2L 0x303
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#define ARC_AUX_DPFP_2H 0x304
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#define ARC_AUX_DPFP_STAT 0x305
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#ifndef __ASSEMBLY__
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/*
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******************************************************************
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* Inline ASM macros to read/write AUX Regs
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* Essentially invocation of lr/sr insns from "C"
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*/
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#if 1
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#define read_aux_reg(reg) __builtin_arc_lr(reg)
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/* gcc builtin sr needs reg param to be long immediate */
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#define write_aux_reg(reg_immed, val) \
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__builtin_arc_sr((unsigned int)val, reg_immed)
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#else
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#define read_aux_reg(reg) \
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({ \
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unsigned int __ret; \
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__asm__ __volatile__( \
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" lr %0, [%1]" \
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: "=r"(__ret) \
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: "i"(reg)); \
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__ret; \
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})
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/*
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* Aux Reg address is specified as long immediate by caller
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* e.g.
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* write_aux_reg(0x69, some_val);
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* This generates tightest code.
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*/
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#define write_aux_reg(reg_imm, val) \
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({ \
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__asm__ __volatile__( \
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" sr %0, [%1] \n" \
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: \
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: "ir"(val), "i"(reg_imm)); \
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})
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/*
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* Aux Reg address is specified in a variable
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* * e.g.
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* reg_num = 0x69
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* write_aux_reg2(reg_num, some_val);
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* This has to generate glue code to load the reg num from
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* memory to a reg hence not recommended.
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*/
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#define write_aux_reg2(reg_in_var, val) \
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({ \
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unsigned int tmp; \
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\
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__asm__ __volatile__( \
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" ld %0, [%2] \n\t" \
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" sr %1, [%0] \n\t" \
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: "=&r"(tmp) \
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: "r"(val), "memory"(®_in_var)); \
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})
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#endif
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#define READ_BCR(reg, into) \
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{ \
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unsigned int tmp; \
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tmp = read_aux_reg(reg); \
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if (sizeof(tmp) == sizeof(into)) { \
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into = *((typeof(into) *)&tmp); \
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} else { \
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extern void bogus_undefined(void); \
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bogus_undefined(); \
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} \
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}
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#define WRITE_BCR(reg, into) \
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{ \
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unsigned int tmp; \
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if (sizeof(tmp) == sizeof(into)) { \
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tmp = (*(unsigned int *)(into)); \
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write_aux_reg(reg, tmp); \
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} else { \
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extern void bogus_undefined(void); \
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bogus_undefined(); \
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} \
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}
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/* Helpers */
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#define TO_KB(bytes) ((bytes) >> 10)
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#define TO_MB(bytes) (TO_KB(bytes) >> 10)
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#define PAGES_TO_KB(n_pages) ((n_pages) << (PAGE_SHIFT - 10))
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#define PAGES_TO_MB(n_pages) (PAGES_TO_KB(n_pages) >> 10)
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#ifdef CONFIG_ARC_FPU_SAVE_RESTORE
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/* These DPFP regs need to be saved/restored across ctx-sw */
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struct arc_fpu {
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struct {
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unsigned int l, h;
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} aux_dpfp[2];
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};
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#endif
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/*
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***************************************************************
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* Build Configuration Registers, with encoded hardware config
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*/
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struct bcr_identity {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int chip_id:16, cpu_id:8, family:8;
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#else
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unsigned int family:8, cpu_id:8, chip_id:16;
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#endif
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};
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#define EXTN_SWAP_VALID 0x1
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#define EXTN_NORM_VALID 0x2
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#define EXTN_MINMAX_VALID 0x2
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#define EXTN_BARREL_VALID 0x2
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struct bcr_extn {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:20, crc:1, ext_arith:2, mul:2, barrel:2, minmax:2,
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norm:2, swap:1;
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#else
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unsigned int swap:1, norm:2, minmax:2, barrel:2, mul:2, ext_arith:2,
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crc:1, pad:20;
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#endif
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};
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/* DSP Options Ref Manual */
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struct bcr_extn_mac_mul {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int pad:16, type:8, ver:8;
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#else
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unsigned int ver:8, type:8, pad:16;
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#endif
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};
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struct bcr_extn_xymem {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int ram_org:2, num_banks:4, bank_sz:4, ver:8;
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#else
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unsigned int ver:8, bank_sz:4, num_banks:4, ram_org:2;
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#endif
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};
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struct bcr_perip {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int start:8, pad2:8, sz:8, pad:8;
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#else
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unsigned int pad:8, sz:8, pad2:8, start:8;
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#endif
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};
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struct bcr_iccm {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int base:16, pad:5, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, pad:5, base:16;
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#endif
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};
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/* DCCM Base Address Register: ARC_REG_DCCMBASE_BCR */
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struct bcr_dccm_base {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int addr:24, ver:8;
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#else
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unsigned int ver:8, addr:24;
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#endif
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};
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/* DCCM RAM Configuration Register: ARC_REG_DCCM_BCR */
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struct bcr_dccm {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int res:21, sz:3, ver:8;
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#else
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unsigned int ver:8, sz:3, res:21;
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#endif
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};
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/* Both SP and DP FPU BCRs have same format */
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struct bcr_fp {
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#ifdef CONFIG_CPU_BIG_ENDIAN
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unsigned int fast:1, ver:8;
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#else
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unsigned int ver:8, fast:1;
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#endif
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};
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/*
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*******************************************************************
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* Generic structures to hold build configuration used at runtime
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*/
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struct cpuinfo_arc_mmu {
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unsigned int ver, pg_sz, sets, ways, u_dtlb, u_itlb, num_tlb;
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};
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struct cpuinfo_arc_cache {
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unsigned int sz, line_len, assoc, ver;
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};
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struct cpuinfo_arc_ccm {
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unsigned int base_addr, sz;
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};
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struct cpuinfo_arc {
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struct cpuinfo_arc_cache icache, dcache;
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struct cpuinfo_arc_mmu mmu;
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struct bcr_identity core;
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unsigned int timers;
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unsigned int vec_base;
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unsigned int uncached_base;
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struct cpuinfo_arc_ccm iccm, dccm;
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struct bcr_extn extn;
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struct bcr_extn_xymem extn_xymem;
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struct bcr_extn_mac_mul extn_mac_mul;
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struct bcr_fp fp, dpfp;
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};
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extern struct cpuinfo_arc cpuinfo_arc700[];
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#endif /* __ASEMBLY__ */
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#endif /* __KERNEL__ */
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#endif /* _ASM_ARC_ARCREGS_H */
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