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When a TLB Invalidate is required for the Logical Partition, the following sequence has to be performed: 1. Load MMIO ATSD AVA register with the necessary value, if required. 2. Write the MMIO ATSD launch register to initiate the TLB Invalidate command. 3. Poll the MMIO ATSD status register to determine when the TLB Invalidate has been completed. Signed-off-by: Christophe Lombard <clombard@linux.vnet.ibm.com> Acked-by: Frederic Barrat <fbarrat@linux.ibm.com> Signed-off-by: Michael Ellerman <mpe@ellerman.id.au> Link: https://lore.kernel.org/r/20201125155013.39955-3-clombard@linux.vnet.ibm.com
85 lines
3 KiB
C
85 lines
3 KiB
C
/* SPDX-License-Identifier: GPL-2.0+ */
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// Copyright 2017 IBM Corp.
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#ifndef _ASM_PNV_OCXL_H
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#define _ASM_PNV_OCXL_H
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#include <linux/bitfield.h>
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#include <linux/pci.h>
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#define PNV_OCXL_TL_MAX_TEMPLATE 63
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#define PNV_OCXL_TL_BITS_PER_RATE 4
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#define PNV_OCXL_TL_RATE_BUF_SIZE ((PNV_OCXL_TL_MAX_TEMPLATE+1) * PNV_OCXL_TL_BITS_PER_RATE / 8)
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#define PNV_OCXL_ATSD_TIMEOUT 1
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/* TLB Management Instructions */
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#define PNV_OCXL_ATSD_LNCH 0x00
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/* Radix Invalidate */
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#define PNV_OCXL_ATSD_LNCH_R PPC_BIT(0)
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/* Radix Invalidation Control
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* 0b00 Just invalidate TLB.
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* 0b01 Invalidate just Page Walk Cache.
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* 0b10 Invalidate TLB, Page Walk Cache, and any
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* caching of Partition and Process Table Entries.
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*/
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#define PNV_OCXL_ATSD_LNCH_RIC PPC_BITMASK(1, 2)
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/* Number and Page Size of translations to be invalidated */
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#define PNV_OCXL_ATSD_LNCH_LP PPC_BITMASK(3, 10)
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/* Invalidation Criteria
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* 0b00 Invalidate just the target VA.
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* 0b01 Invalidate matching PID.
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*/
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#define PNV_OCXL_ATSD_LNCH_IS PPC_BITMASK(11, 12)
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/* 0b1: Process Scope, 0b0: Partition Scope */
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#define PNV_OCXL_ATSD_LNCH_PRS PPC_BIT(13)
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/* Invalidation Flag */
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#define PNV_OCXL_ATSD_LNCH_B PPC_BIT(14)
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/* Actual Page Size to be invalidated
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* 000 4KB
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* 101 64KB
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* 001 2MB
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* 010 1GB
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*/
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#define PNV_OCXL_ATSD_LNCH_AP PPC_BITMASK(15, 17)
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/* Defines the large page select
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* L=0b0 for 4KB pages
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* L=0b1 for large pages)
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*/
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#define PNV_OCXL_ATSD_LNCH_L PPC_BIT(18)
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/* Process ID */
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#define PNV_OCXL_ATSD_LNCH_PID PPC_BITMASK(19, 38)
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/* NoFlush – Assumed to be 0b0 */
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#define PNV_OCXL_ATSD_LNCH_F PPC_BIT(39)
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#define PNV_OCXL_ATSD_LNCH_OCAPI_SLBI PPC_BIT(40)
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#define PNV_OCXL_ATSD_LNCH_OCAPI_SINGLETON PPC_BIT(41)
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#define PNV_OCXL_ATSD_AVA 0x08
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#define PNV_OCXL_ATSD_AVA_AVA PPC_BITMASK(0, 51)
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#define PNV_OCXL_ATSD_STAT 0x10
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int pnv_ocxl_get_actag(struct pci_dev *dev, u16 *base, u16 *enabled, u16 *supported);
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int pnv_ocxl_get_pasid_count(struct pci_dev *dev, int *count);
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int pnv_ocxl_get_tl_cap(struct pci_dev *dev, long *cap,
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char *rate_buf, int rate_buf_size);
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int pnv_ocxl_set_tl_conf(struct pci_dev *dev, long cap,
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uint64_t rate_buf_phys, int rate_buf_size);
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int pnv_ocxl_get_xsl_irq(struct pci_dev *dev, int *hwirq);
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void pnv_ocxl_unmap_xsl_regs(void __iomem *dsisr, void __iomem *dar,
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void __iomem *tfc, void __iomem *pe_handle);
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int pnv_ocxl_map_xsl_regs(struct pci_dev *dev, void __iomem **dsisr,
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void __iomem **dar, void __iomem **tfc,
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void __iomem **pe_handle);
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int pnv_ocxl_spa_setup(struct pci_dev *dev, void *spa_mem, int PE_mask, void **platform_data);
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void pnv_ocxl_spa_release(void *platform_data);
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int pnv_ocxl_spa_remove_pe_from_cache(void *platform_data, int pe_handle);
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int pnv_ocxl_map_lpar(struct pci_dev *dev, uint64_t lparid,
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uint64_t lpcr, void __iomem **arva);
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void pnv_ocxl_unmap_lpar(void __iomem *arva);
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void pnv_ocxl_tlb_invalidate(void __iomem *arva,
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unsigned long pid,
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unsigned long addr,
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unsigned long page_size);
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#endif /* _ASM_PNV_OCXL_H */
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