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9eaa82935d
We'd like all architectures to convert to ARCH_ATOMIC, as once all
architectures are converted it will be possible to make significant
cleanups to the atomics headers, and this will make it much easier to
generically enable atomic functionality (e.g. debug logic in the
instrumented wrappers).
As a step towards that, this patch migrates powerpc to ARCH_ATOMIC. The
arch code provides arch_{atomic,atomic64,xchg,cmpxchg}*(), and common
code wraps these with optional instrumentation to provide the regular
functions.
While atomic_try_cmpxchg_lock() is not part of the common atomic API, it
is given an `arch_` prefix for consistency.
Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Boqun Feng <boqun.feng@gmail.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Will Deacon <will@kernel.org>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Link: https://lore.kernel.org/r/20210525140232.53872-28-mark.rutland@arm.com
84 lines
2 KiB
C
84 lines
2 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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#ifndef _ASM_POWERPC_QSPINLOCK_H
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#define _ASM_POWERPC_QSPINLOCK_H
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#include <asm-generic/qspinlock_types.h>
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#include <asm/paravirt.h>
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#define _Q_PENDING_LOOPS (1 << 9) /* not tuned */
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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extern void native_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
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extern void __pv_queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
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extern void __pv_queued_spin_unlock(struct qspinlock *lock);
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static __always_inline void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val)
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{
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if (!is_shared_processor())
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native_queued_spin_lock_slowpath(lock, val);
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else
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__pv_queued_spin_lock_slowpath(lock, val);
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}
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#define queued_spin_unlock queued_spin_unlock
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static inline void queued_spin_unlock(struct qspinlock *lock)
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{
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if (!is_shared_processor())
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smp_store_release(&lock->locked, 0);
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else
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__pv_queued_spin_unlock(lock);
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}
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#else
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extern void queued_spin_lock_slowpath(struct qspinlock *lock, u32 val);
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#endif
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static __always_inline void queued_spin_lock(struct qspinlock *lock)
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{
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u32 val = 0;
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if (likely(arch_atomic_try_cmpxchg_lock(&lock->val, &val, _Q_LOCKED_VAL)))
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return;
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queued_spin_lock_slowpath(lock, val);
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}
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#define queued_spin_lock queued_spin_lock
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#ifdef CONFIG_PARAVIRT_SPINLOCKS
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#define SPIN_THRESHOLD (1<<15) /* not tuned */
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static __always_inline void pv_wait(u8 *ptr, u8 val)
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{
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if (*ptr != val)
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return;
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yield_to_any();
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/*
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* We could pass in a CPU here if waiting in the queue and yield to
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* the previous CPU in the queue.
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*/
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}
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static __always_inline void pv_kick(int cpu)
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{
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prod_cpu(cpu);
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}
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extern void __pv_init_lock_hash(void);
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static inline void pv_spinlocks_init(void)
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{
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__pv_init_lock_hash();
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}
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#endif
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/*
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* Queued spinlocks rely heavily on smp_cond_load_relaxed() to busy-wait,
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* which was found to have performance problems if implemented with
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* the preferred spin_begin()/spin_end() SMT priority pattern. Use the
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* generic version instead.
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*/
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#include <asm-generic/qspinlock.h>
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#endif /* _ASM_POWERPC_QSPINLOCK_H */
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