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3bbda69c48
Patch series "Speedup mremap on ppc64", v8. This patchset enables MOVE_PMD/MOVE_PUD support on power. This requires the platform to support updating higher-level page tables without updating page table entries. This also needs to invalidate the Page Walk Cache on architecture supporting the same. This patch (of 3): Architectures like ppc64 support faster mremap only with radix translation. Hence allow a runtime check w.r.t support for fast mremap. Link: https://lkml.kernel.org/r/20210616045735.374532-1-aneesh.kumar@linux.ibm.com Link: https://lkml.kernel.org/r/20210616045735.374532-2-aneesh.kumar@linux.ibm.com Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.ibm.com> Cc: Michael Ellerman <mpe@ellerman.id.au> Cc: Kalesh Singh <kaleshsingh@google.com> Cc: Nicholas Piggin <npiggin@gmail.com> Cc: Joel Fernandes <joel@joelfernandes.org> Cc: Christophe Leroy <christophe.leroy@csgroup.eu> Cc: Kirill A. Shutemov <kirill@shutemov.name> Cc: "Aneesh Kumar K . V" <aneesh.kumar@linux.ibm.com> Cc: Hugh Dickins <hughd@google.com> Cc: Kirill A. Shutemov <kirill.shutemov@linux.intel.com> Cc: Stephen Rothwell <sfr@canb.auug.org.au> Signed-off-by: Andrew Morton <akpm@linux-foundation.org> Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
93 lines
2.3 KiB
C
93 lines
2.3 KiB
C
/* SPDX-License-Identifier: GPL-2.0-or-later */
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/*
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* TLB shootdown specifics for powerpc
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*
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* Copyright (C) 2002 Anton Blanchard, IBM Corp.
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* Copyright (C) 2002 Paul Mackerras, IBM Corp.
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*/
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#ifndef _ASM_POWERPC_TLB_H
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#define _ASM_POWERPC_TLB_H
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#ifdef __KERNEL__
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#ifndef __powerpc64__
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#include <linux/pgtable.h>
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#endif
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#ifndef __powerpc64__
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#include <asm/page.h>
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#include <asm/mmu.h>
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#endif
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#include <linux/pagemap.h>
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#define tlb_start_vma(tlb, vma) do { } while (0)
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#define tlb_end_vma(tlb, vma) do { } while (0)
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#define __tlb_remove_tlb_entry __tlb_remove_tlb_entry
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#define tlb_flush tlb_flush
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extern void tlb_flush(struct mmu_gather *tlb);
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/*
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* book3s:
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* Hash does not use the linux page-tables, so we can avoid
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* the TLB invalidate for page-table freeing, Radix otoh does use the
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* page-tables and needs the TLBI.
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*
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* nohash:
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* We still do TLB invalidate in the __pte_free_tlb routine before we
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* add the page table pages to mmu gather table batch.
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*/
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#define tlb_needs_table_invalidate() radix_enabled()
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/* Get the generic bits... */
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#include <asm-generic/tlb.h>
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static inline void __tlb_remove_tlb_entry(struct mmu_gather *tlb, pte_t *ptep,
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unsigned long address)
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{
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#ifdef CONFIG_PPC_BOOK3S_32
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if (pte_val(*ptep) & _PAGE_HASHPTE)
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flush_hash_entry(tlb->mm, ptep, address);
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#endif
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}
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#ifdef CONFIG_SMP
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static inline int mm_is_core_local(struct mm_struct *mm)
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{
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return cpumask_subset(mm_cpumask(mm),
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topology_sibling_cpumask(smp_processor_id()));
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}
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#ifdef CONFIG_PPC_BOOK3S_64
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static inline int mm_is_thread_local(struct mm_struct *mm)
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{
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if (atomic_read(&mm->context.active_cpus) > 1)
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return false;
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return cpumask_test_cpu(smp_processor_id(), mm_cpumask(mm));
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}
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#else /* CONFIG_PPC_BOOK3S_64 */
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static inline int mm_is_thread_local(struct mm_struct *mm)
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{
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return cpumask_equal(mm_cpumask(mm),
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cpumask_of(smp_processor_id()));
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}
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#endif /* !CONFIG_PPC_BOOK3S_64 */
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#else /* CONFIG_SMP */
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static inline int mm_is_core_local(struct mm_struct *mm)
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{
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return 1;
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}
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static inline int mm_is_thread_local(struct mm_struct *mm)
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{
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return 1;
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}
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#endif
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#define arch_supports_page_table_move arch_supports_page_table_move
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static inline bool arch_supports_page_table_move(void)
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{
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return radix_enabled();
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}
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#endif /* __KERNEL__ */
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#endif /* __ASM_POWERPC_TLB_H */
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