Vladimir Oltean 528d3f190c net: mscc: ocelot: drop the use of the "lags" array ... We can now simplify the implementation by always using ocelot_get_bond_mask to look up the other ports that are offloading the same bonding interface as us. In ocelot_set_aggr_pgids, the code had a way to uniquely iterate through LAGs. We need to achieve the same behavior by marking each LAG as visited, which we do now by using a temporary 32-bit "visited" bitmask. This is ok and we do not need dynamic memory allocation, because we know that this switch architecture will not have more than 32 ports (the PGID port masks are 32-bit anyway). Signed-off-by: Vladimir Oltean <vladimir.oltean@nxp.com> Signed-off-by: Jakub Kicinski <kuba@kernel.org>		2021-02-06 14:51:50 -08:00
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arc	include/: replace HTTP links with HTTPS ones	2020-08-12 10:57:59 -07:00
at91	ARM: at91: add atmel tcb capabilities	2020-07-11 18:57:03 +02:00
bcm2835	Revert "firmware: raspberrypi: Introduce vl805 init routine"	2020-08-18 13:01:11 +02:00
brcmstb	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
fsl	ethernet: ucc_geth: remove bd_mem_part and all associated code	2021-01-21 12:19:56 -08:00
imx	ARM: imx: move cpu definitions into a header	2020-05-20 23:03:47 +08:00
mediatek	iommu/mediatek: Clean up struct mtk_smi_iommu	2019-08-30 15:57:27 +02:00
mscc	net: mscc: ocelot: drop the use of the "lags" array	2021-02-06 14:51:50 -08:00
qcom	It looks like a smaller batch of clk updates this time around. In the core	2020-08-07 13:35:51 -07:00
rockchip	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 288	2019-06-05 17:36:37 +02:00
sa1100	treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500	2019-06-19 17:09:55 +02:00
sifive	riscv: move sifive_l2_cache.h to include/soc	2020-01-12 10:12:44 -08:00
tegra	memory: tegra: Correct stub of devm_tegra_memory_controller_get()	2020-11-26 18:50:36 +01:00