mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-09-18 08:35:03 +00:00
00ecc6e6d4
Add support for DRM_FORMAT_{A,X}BGR8888 in amdgpu with amd dc disabled
(v2) Crossbar registers are defined and used to swap red and blue channels,
keeping the existing coding style in each of the dce modules.
After setting crossbar bits in fb_swap, use bitwise OR for big endian
where required in DCE6 and DCE8 which do not rely on REG_SET_FIELD()
Signed-off-by: Mauro Rossi <issor.oruam@gmail.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
292 lines
13 KiB
C
292 lines
13 KiB
C
/*
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* Copyright 2016 Advanced Micro Devices, Inc.
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*
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* Permission is hereby granted, free of charge, to any person obtaining a
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* copy of this software and associated documentation files (the "Software"),
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* to deal in the Software without restriction, including without limitation
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* the rights to use, copy, modify, merge, publish, distribute, sublicense,
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* and/or sell copies of the Software, and to permit persons to whom the
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* Software is furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR
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* OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
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* ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
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* OTHER DEALINGS IN THE SOFTWARE.
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*
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*/
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#ifndef SI_ENUMS_H
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#define SI_ENUMS_H
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#define VBLANK_INT_MASK (1 << 0)
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#define DC_HPDx_INT_EN (1 << 16)
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#define VBLANK_ACK (1 << 4)
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#define VLINE_ACK (1 << 4)
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#define CURSOR_WIDTH 64
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#define CURSOR_HEIGHT 64
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#define VGA_VSTATUS_CNTL 0xFFFCFFFF
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#define PRIORITY_MARK_MASK 0x7fff
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#define PRIORITY_OFF (1 << 16)
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#define PRIORITY_ALWAYS_ON (1 << 20)
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#define INTERLEAVE_EN (1 << 0)
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#define LATENCY_WATERMARK_MASK(x) ((x) << 16)
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#define DC_LB_MEMORY_CONFIG(x) ((x) << 20)
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#define ICON_DEGAMMA_MODE(x) (((x) & 0x3) << 8)
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#define GRPH_ENDIAN_SWAP(x) (((x) & 0x3) << 0)
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#define GRPH_ENDIAN_NONE 0
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#define GRPH_ENDIAN_8IN16 1
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#define GRPH_ENDIAN_8IN32 2
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#define GRPH_ENDIAN_8IN64 3
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#define GRPH_RED_CROSSBAR(x) (((x) & 0x3) << 4)
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#define GRPH_RED_SEL_R 0
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#define GRPH_RED_SEL_G 1
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#define GRPH_RED_SEL_B 2
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#define GRPH_RED_SEL_A 3
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#define GRPH_GREEN_CROSSBAR(x) (((x) & 0x3) << 6)
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#define GRPH_GREEN_SEL_G 0
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#define GRPH_GREEN_SEL_B 1
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#define GRPH_GREEN_SEL_A 2
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#define GRPH_GREEN_SEL_R 3
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#define GRPH_BLUE_CROSSBAR(x) (((x) & 0x3) << 8)
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#define GRPH_BLUE_SEL_B 0
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#define GRPH_BLUE_SEL_A 1
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#define GRPH_BLUE_SEL_R 2
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#define GRPH_BLUE_SEL_G 3
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#define GRPH_ALPHA_CROSSBAR(x) (((x) & 0x3) << 10)
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#define GRPH_ALPHA_SEL_A 0
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#define GRPH_ALPHA_SEL_R 1
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#define GRPH_ALPHA_SEL_G 2
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#define GRPH_ALPHA_SEL_B 3
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#define GRPH_DEPTH(x) (((x) & 0x3) << 0)
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#define GRPH_DEPTH_8BPP 0
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#define GRPH_DEPTH_16BPP 1
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#define GRPH_DEPTH_32BPP 2
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#define GRPH_FORMAT(x) (((x) & 0x7) << 8)
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#define GRPH_FORMAT_INDEXED 0
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#define GRPH_FORMAT_ARGB1555 0
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#define GRPH_FORMAT_ARGB565 1
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#define GRPH_FORMAT_ARGB4444 2
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#define GRPH_FORMAT_AI88 3
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#define GRPH_FORMAT_MONO16 4
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#define GRPH_FORMAT_BGRA5551 5
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#define GRPH_FORMAT_ARGB8888 0
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#define GRPH_FORMAT_ARGB2101010 1
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#define GRPH_FORMAT_32BPP_DIG 2
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#define GRPH_FORMAT_8B_ARGB2101010 3
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#define GRPH_FORMAT_BGRA1010102 4
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#define GRPH_FORMAT_8B_BGRA1010102 5
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#define GRPH_FORMAT_RGB111110 6
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#define GRPH_FORMAT_BGR101111 7
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#define GRPH_NUM_BANKS(x) (((x) & 0x3) << 2)
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#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
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#define GRPH_ARRAY_LINEAR_GENERAL 0
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#define GRPH_ARRAY_LINEAR_ALIGNED 1
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#define GRPH_ARRAY_1D_TILED_THIN1 2
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#define GRPH_ARRAY_2D_TILED_THIN1 4
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#define GRPH_TILE_SPLIT(x) (((x) & 0x7) << 13)
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#define GRPH_BANK_WIDTH(x) (((x) & 0x3) << 6)
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#define GRPH_BANK_HEIGHT(x) (((x) & 0x3) << 11)
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#define GRPH_MACRO_TILE_ASPECT(x) (((x) & 0x3) << 18)
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#define GRPH_ARRAY_MODE(x) (((x) & 0x7) << 20)
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#define GRPH_PIPE_CONFIG(x) (((x) & 0x1f) << 24)
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#define CURSOR_EN (1 << 0)
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#define CURSOR_MODE(x) (((x) & 0x3) << 8)
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#define CURSOR_MONO 0
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#define CURSOR_24_1 1
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#define CURSOR_24_8_PRE_MULT 2
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#define CURSOR_24_8_UNPRE_MULT 3
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#define CURSOR_2X_MAGNIFY (1 << 16)
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#define CURSOR_FORCE_MC_ON (1 << 20)
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#define CURSOR_URGENT_CONTROL(x) (((x) & 0x7) << 24)
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#define CURSOR_URGENT_ALWAYS 0
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#define CURSOR_URGENT_1_8 1
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#define CURSOR_URGENT_1_4 2
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#define CURSOR_URGENT_3_8 3
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#define CURSOR_URGENT_1_2 4
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#define CURSOR_UPDATE_PENDING (1 << 0)
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#define CURSOR_UPDATE_TAKEN (1 << 1)
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#define CURSOR_UPDATE_LOCK (1 << 16)
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#define CURSOR_DISABLE_MULTIPLE_UPDATE (1 << 24)
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#define AMDGPU_NUM_OF_VMIDS 8
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#define SI_CRTC0_REGISTER_OFFSET 0
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#define SI_CRTC1_REGISTER_OFFSET 0x300
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#define SI_CRTC2_REGISTER_OFFSET 0x2600
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#define SI_CRTC3_REGISTER_OFFSET 0x2900
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#define SI_CRTC4_REGISTER_OFFSET 0x2c00
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#define SI_CRTC5_REGISTER_OFFSET 0x2f00
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#define DMA0_REGISTER_OFFSET 0x000
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#define DMA1_REGISTER_OFFSET 0x200
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#define ES_AND_GS_AUTO 3
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#define RADEON_PACKET_TYPE3 3
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#define CE_PARTITION_BASE 3
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#define BUF_SWAP_32BIT (2 << 16)
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#define GFX_POWER_STATUS (1 << 1)
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#define GFX_CLOCK_STATUS (1 << 2)
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#define GFX_LS_STATUS (1 << 3)
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#define RLC_BUSY_STATUS (1 << 0)
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#define RLC_PUD(x) ((x) << 0)
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#define RLC_PUD_MASK (0xff << 0)
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#define RLC_PDD(x) ((x) << 8)
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#define RLC_PDD_MASK (0xff << 8)
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#define RLC_TTPD(x) ((x) << 16)
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#define RLC_TTPD_MASK (0xff << 16)
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#define RLC_MSD(x) ((x) << 24)
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#define RLC_MSD_MASK (0xff << 24)
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#define WRITE_DATA_ENGINE_SEL(x) ((x) << 30)
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#define WRITE_DATA_DST_SEL(x) ((x) << 8)
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#define EVENT_TYPE(x) ((x) << 0)
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#define EVENT_INDEX(x) ((x) << 8)
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#define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4)
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#define WAIT_REG_MEM_FUNCTION(x) ((x) << 0)
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#define WAIT_REG_MEM_ENGINE(x) ((x) << 8)
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#define GFX6_NUM_GFX_RINGS 1
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#define GFX6_NUM_COMPUTE_RINGS 2
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#define RLC_SAVE_AND_RESTORE_STARTING_OFFSET 0x90
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#define RLC_CLEAR_STATE_DESCRIPTOR_OFFSET 0x3D
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#define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003
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#define VERDE_GB_ADDR_CONFIG_GOLDEN 0x02010002
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#define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02011003
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#define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \
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(((op) & 0xFF) << 8) | \
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((n) & 0x3FFF) << 16)
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#define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1)
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#define PACKET3_NOP 0x10
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#define PACKET3_SET_BASE 0x11
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#define PACKET3_BASE_INDEX(x) ((x) << 0)
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#define PACKET3_CLEAR_STATE 0x12
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#define PACKET3_INDEX_BUFFER_SIZE 0x13
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#define PACKET3_DISPATCH_DIRECT 0x15
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#define PACKET3_DISPATCH_INDIRECT 0x16
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#define PACKET3_ALLOC_GDS 0x1B
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#define PACKET3_WRITE_GDS_RAM 0x1C
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#define PACKET3_ATOMIC_GDS 0x1D
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#define PACKET3_ATOMIC 0x1E
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#define PACKET3_OCCLUSION_QUERY 0x1F
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#define PACKET3_SET_PREDICATION 0x20
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#define PACKET3_REG_RMW 0x21
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#define PACKET3_COND_EXEC 0x22
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#define PACKET3_PRED_EXEC 0x23
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#define PACKET3_DRAW_INDIRECT 0x24
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#define PACKET3_DRAW_INDEX_INDIRECT 0x25
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#define PACKET3_INDEX_BASE 0x26
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#define PACKET3_DRAW_INDEX_2 0x27
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#define PACKET3_CONTEXT_CONTROL 0x28
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#define PACKET3_INDEX_TYPE 0x2A
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#define PACKET3_DRAW_INDIRECT_MULTI 0x2C
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#define PACKET3_DRAW_INDEX_AUTO 0x2D
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#define PACKET3_DRAW_INDEX_IMMD 0x2E
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#define PACKET3_NUM_INSTANCES 0x2F
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#define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30
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#define PACKET3_INDIRECT_BUFFER_CONST 0x31
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#define PACKET3_INDIRECT_BUFFER 0x3F
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#define PACKET3_STRMOUT_BUFFER_UPDATE 0x34
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#define PACKET3_DRAW_INDEX_OFFSET_2 0x35
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#define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36
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#define PACKET3_WRITE_DATA 0x37
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#define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38
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#define PACKET3_MEM_SEMAPHORE 0x39
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#define PACKET3_MPEG_INDEX 0x3A
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#define PACKET3_COPY_DW 0x3B
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#define PACKET3_WAIT_REG_MEM 0x3C
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#define PACKET3_MEM_WRITE 0x3D
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#define PACKET3_COPY_DATA 0x40
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#define PACKET3_CP_DMA 0x41
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# define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20)
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# define PACKET3_CP_DMA_ENGINE(x) ((x) << 27)
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# define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29)
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# define PACKET3_CP_DMA_CP_SYNC (1 << 31)
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# define PACKET3_CP_DMA_DIS_WC (1 << 21)
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# define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22)
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# define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24)
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# define PACKET3_CP_DMA_CMD_SAS (1 << 26)
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# define PACKET3_CP_DMA_CMD_DAS (1 << 27)
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# define PACKET3_CP_DMA_CMD_SAIC (1 << 28)
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# define PACKET3_CP_DMA_CMD_DAIC (1 << 29)
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# define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30)
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#define PACKET3_PFP_SYNC_ME 0x42
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#define PACKET3_SURFACE_SYNC 0x43
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# define PACKET3_DEST_BASE_0_ENA (1 << 0)
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# define PACKET3_DEST_BASE_1_ENA (1 << 1)
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# define PACKET3_CB0_DEST_BASE_ENA (1 << 6)
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# define PACKET3_CB1_DEST_BASE_ENA (1 << 7)
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# define PACKET3_CB2_DEST_BASE_ENA (1 << 8)
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# define PACKET3_CB3_DEST_BASE_ENA (1 << 9)
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# define PACKET3_CB4_DEST_BASE_ENA (1 << 10)
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# define PACKET3_CB5_DEST_BASE_ENA (1 << 11)
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# define PACKET3_CB6_DEST_BASE_ENA (1 << 12)
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# define PACKET3_CB7_DEST_BASE_ENA (1 << 13)
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# define PACKET3_DB_DEST_BASE_ENA (1 << 14)
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# define PACKET3_DEST_BASE_2_ENA (1 << 19)
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# define PACKET3_DEST_BASE_3_ENA (1 << 21)
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# define PACKET3_TCL1_ACTION_ENA (1 << 22)
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# define PACKET3_TC_ACTION_ENA (1 << 23)
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# define PACKET3_CB_ACTION_ENA (1 << 25)
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# define PACKET3_DB_ACTION_ENA (1 << 26)
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# define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27)
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# define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29)
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#define PACKET3_ME_INITIALIZE 0x44
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#define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16)
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#define PACKET3_COND_WRITE 0x45
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#define PACKET3_EVENT_WRITE 0x46
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#define PACKET3_EVENT_WRITE_EOP 0x47
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#define PACKET3_EVENT_WRITE_EOS 0x48
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#define PACKET3_PREAMBLE_CNTL 0x4A
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# define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28)
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# define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28)
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#define PACKET3_ONE_REG_WRITE 0x57
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#define PACKET3_LOAD_CONFIG_REG 0x5F
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#define PACKET3_LOAD_CONTEXT_REG 0x60
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#define PACKET3_LOAD_SH_REG 0x61
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#define PACKET3_SET_CONFIG_REG 0x68
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#define PACKET3_SET_CONFIG_REG_START 0x00002000
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#define PACKET3_SET_CONFIG_REG_END 0x00002c00
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#define PACKET3_SET_CONTEXT_REG 0x69
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#define PACKET3_SET_CONTEXT_REG_START 0x000a000
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#define PACKET3_SET_CONTEXT_REG_END 0x000a400
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#define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73
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#define PACKET3_SET_RESOURCE_INDIRECT 0x74
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#define PACKET3_SET_SH_REG 0x76
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#define PACKET3_SET_SH_REG_START 0x00002c00
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#define PACKET3_SET_SH_REG_END 0x00003000
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#define PACKET3_SET_SH_REG_OFFSET 0x77
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#define PACKET3_ME_WRITE 0x7A
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#define PACKET3_SCRATCH_RAM_WRITE 0x7D
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#define PACKET3_SCRATCH_RAM_READ 0x7E
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#define PACKET3_CE_WRITE 0x7F
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#define PACKET3_LOAD_CONST_RAM 0x80
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#define PACKET3_WRITE_CONST_RAM 0x81
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#define PACKET3_WRITE_CONST_RAM_OFFSET 0x82
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#define PACKET3_DUMP_CONST_RAM 0x83
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#define PACKET3_INCREMENT_CE_COUNTER 0x84
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#define PACKET3_INCREMENT_DE_COUNTER 0x85
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#define PACKET3_WAIT_ON_CE_COUNTER 0x86
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#define PACKET3_WAIT_ON_DE_COUNTER 0x87
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#define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88
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#define PACKET3_SET_CE_DE_COUNTERS 0x89
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#define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A
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#define PACKET3_SWITCH_BUFFER 0x8B
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#define PACKET3_SEM_WAIT_ON_SIGNAL (0x1 << 12)
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#define PACKET3_SEM_SEL_SIGNAL (0x6 << 29)
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#define PACKET3_SEM_SEL_WAIT (0x7 << 29)
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#endif
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