mirror of
https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git
synced 2024-08-26 19:00:25 +00:00
83ccf69d8f
Adds a new cpu type for the JZ4740 to the Linux MIPS architecture code. It also adds the iomem addresses for the different components found on a JZ4740 SoC. Signed-off-by: Lars-Peter Clausen <lars@metafoo.de> Cc: linux-mips@linux-mips.org Cc: linux-kernel@vger.kernel.org Patchwork: https://patchwork.linux-mips.org/patch/1464/ Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
25 lines
809 B
C
25 lines
809 B
C
/*
|
|
* This file is subject to the terms and conditions of the GNU General Public
|
|
* License. See the file "COPYING" in the main directory of this archive
|
|
* for more details.
|
|
*
|
|
* Copyright (C) 2002, 2004, 2007 by Ralf Baechle <ralf@linux-mips.org>
|
|
*/
|
|
#ifndef __ASM_MIPS_MACH_JZ4740_WAR_H
|
|
#define __ASM_MIPS_MACH_JZ4740_WAR_H
|
|
|
|
#define R4600_V1_INDEX_ICACHEOP_WAR 0
|
|
#define R4600_V1_HIT_CACHEOP_WAR 0
|
|
#define R4600_V2_HIT_CACHEOP_WAR 0
|
|
#define R5432_CP0_INTERRUPT_WAR 0
|
|
#define BCM1250_M3_WAR 0
|
|
#define SIBYTE_1956_WAR 0
|
|
#define MIPS4K_ICACHE_REFILL_WAR 0
|
|
#define MIPS_CACHE_SYNC_WAR 0
|
|
#define TX49XX_ICACHE_INDEX_INV_WAR 0
|
|
#define RM9000_CDEX_SMP_WAR 0
|
|
#define ICACHE_REFILLS_WORKAROUND_WAR 0
|
|
#define R10000_LLSC_WAR 0
|
|
#define MIPS34K_MISSED_ITLB_WAR 0
|
|
|
|
#endif /* __ASM_MIPS_MACH_JZ4740_WAR_H */
|