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54104ee023
This adds Generic Clock Controller driver for lan966x SoC. Lan966x clock controller contains 3 PLLs - cpu_clk, ddr_clk and sys_clk. It generates and supplies clock to various peripherals within SoC. Register settings required to provide GCK clocking to a peripheral is as below: GCK_SRC_SEL = Select clock source. GCK_PRESCALER = Set divider value. GCK_ENA = 1 - Enable GCK clock. Signed-off-by: Kavyasree Kotagiri <kavyasree.kotagiri@microchip.com> Co-developed-by: Horatiu Vultur <horatiu.vultur@microchip.com> Signed-off-by: Horatiu Vultur <horatiu.vultur@microchip.com> Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com> Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com> Link: https://lore.kernel.org/r/20211103061935.25677-4-kavyasree.kotagiri@microchip.com |
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| clk | ||
| clocksource | ||
| comedi | ||
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| counter | ||
| cpufreq | ||
| cpuidle | ||
| crypto | ||
| cxl | ||
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| devfreq | ||
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| Kconfig | ||
| Makefile | ||