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![Zhang Changzhong](/assets/img/avatar_default.png)
In m_can_pci_remove() and error handling path of m_can_pci_probe(),
m_can_class_free_dev() should be called to free resource allocated by
m_can_class_allocate_dev(), otherwise there will be memleak.
Fixes: cab7ffc032
("can: m_can: add PCI glue driver for Intel Elkhart Lake")
Signed-off-by: Zhang Changzhong <zhangchangzhong@huawei.com>
Reviewed-by: Jarkko Nikula <jarkko.nikula@linux.intel.com>
Link: https://lore.kernel.org/all/1668168684-6390-1-git-send-email-zhangchangzhong@huawei.com
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
206 lines
4.7 KiB
C
206 lines
4.7 KiB
C
// SPDX-License-Identifier: GPL-2.0
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/*
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* PCI Specific M_CAN Glue
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*
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* Copyright (C) 2018-2020 Intel Corporation
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* Author: Felipe Balbi (Intel)
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* Author: Jarkko Nikula <jarkko.nikula@linux.intel.com>
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* Author: Raymond Tan <raymond.tan@intel.com>
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*/
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#include <linux/kernel.h>
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#include <linux/module.h>
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#include <linux/netdevice.h>
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#include <linux/pci.h>
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#include <linux/pm_runtime.h>
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#include "m_can.h"
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#define M_CAN_PCI_MMIO_BAR 0
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#define M_CAN_CLOCK_FREQ_EHL 200000000
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#define CTL_CSR_INT_CTL_OFFSET 0x508
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struct m_can_pci_priv {
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struct m_can_classdev cdev;
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void __iomem *base;
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};
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static inline struct m_can_pci_priv *cdev_to_priv(struct m_can_classdev *cdev)
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{
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return container_of(cdev, struct m_can_pci_priv, cdev);
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}
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static u32 iomap_read_reg(struct m_can_classdev *cdev, int reg)
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{
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struct m_can_pci_priv *priv = cdev_to_priv(cdev);
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return readl(priv->base + reg);
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}
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static int iomap_read_fifo(struct m_can_classdev *cdev, int offset, void *val, size_t val_count)
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{
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struct m_can_pci_priv *priv = cdev_to_priv(cdev);
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void __iomem *src = priv->base + offset;
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while (val_count--) {
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*(unsigned int *)val = ioread32(src);
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val += 4;
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src += 4;
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}
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return 0;
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}
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static int iomap_write_reg(struct m_can_classdev *cdev, int reg, int val)
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{
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struct m_can_pci_priv *priv = cdev_to_priv(cdev);
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writel(val, priv->base + reg);
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return 0;
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}
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static int iomap_write_fifo(struct m_can_classdev *cdev, int offset,
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const void *val, size_t val_count)
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{
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struct m_can_pci_priv *priv = cdev_to_priv(cdev);
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void __iomem *dst = priv->base + offset;
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while (val_count--) {
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iowrite32(*(unsigned int *)val, dst);
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val += 4;
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dst += 4;
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}
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return 0;
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}
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static struct m_can_ops m_can_pci_ops = {
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.read_reg = iomap_read_reg,
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.write_reg = iomap_write_reg,
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.write_fifo = iomap_write_fifo,
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.read_fifo = iomap_read_fifo,
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};
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static int m_can_pci_probe(struct pci_dev *pci, const struct pci_device_id *id)
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{
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struct device *dev = &pci->dev;
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struct m_can_classdev *mcan_class;
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struct m_can_pci_priv *priv;
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void __iomem *base;
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int ret;
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ret = pcim_enable_device(pci);
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if (ret)
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return ret;
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pci_set_master(pci);
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ret = pcim_iomap_regions(pci, BIT(M_CAN_PCI_MMIO_BAR), pci_name(pci));
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if (ret)
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return ret;
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base = pcim_iomap_table(pci)[M_CAN_PCI_MMIO_BAR];
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if (!base) {
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dev_err(dev, "failed to map BARs\n");
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return -ENOMEM;
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}
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mcan_class = m_can_class_allocate_dev(&pci->dev,
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sizeof(struct m_can_pci_priv));
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if (!mcan_class)
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return -ENOMEM;
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priv = cdev_to_priv(mcan_class);
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priv->base = base;
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ret = pci_alloc_irq_vectors(pci, 1, 1, PCI_IRQ_ALL_TYPES);
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if (ret < 0)
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goto err_free_dev;
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mcan_class->dev = &pci->dev;
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mcan_class->net->irq = pci_irq_vector(pci, 0);
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mcan_class->pm_clock_support = 1;
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mcan_class->can.clock.freq = id->driver_data;
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mcan_class->ops = &m_can_pci_ops;
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pci_set_drvdata(pci, mcan_class);
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ret = m_can_class_register(mcan_class);
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if (ret)
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goto err_free_irq;
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/* Enable interrupt control at CAN wrapper IP */
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writel(0x1, base + CTL_CSR_INT_CTL_OFFSET);
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pm_runtime_set_autosuspend_delay(dev, 1000);
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pm_runtime_use_autosuspend(dev);
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pm_runtime_put_noidle(dev);
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pm_runtime_allow(dev);
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return 0;
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err_free_irq:
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pci_free_irq_vectors(pci);
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err_free_dev:
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m_can_class_free_dev(mcan_class->net);
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return ret;
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}
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static void m_can_pci_remove(struct pci_dev *pci)
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{
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struct m_can_classdev *mcan_class = pci_get_drvdata(pci);
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struct m_can_pci_priv *priv = cdev_to_priv(mcan_class);
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pm_runtime_forbid(&pci->dev);
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pm_runtime_get_noresume(&pci->dev);
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/* Disable interrupt control at CAN wrapper IP */
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writel(0x0, priv->base + CTL_CSR_INT_CTL_OFFSET);
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m_can_class_unregister(mcan_class);
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m_can_class_free_dev(mcan_class->net);
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pci_free_irq_vectors(pci);
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}
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static __maybe_unused int m_can_pci_suspend(struct device *dev)
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{
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return m_can_class_suspend(dev);
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}
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static __maybe_unused int m_can_pci_resume(struct device *dev)
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{
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return m_can_class_resume(dev);
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}
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static SIMPLE_DEV_PM_OPS(m_can_pci_pm_ops,
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m_can_pci_suspend, m_can_pci_resume);
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static const struct pci_device_id m_can_pci_id_table[] = {
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{ PCI_VDEVICE(INTEL, 0x4bc1), M_CAN_CLOCK_FREQ_EHL, },
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{ PCI_VDEVICE(INTEL, 0x4bc2), M_CAN_CLOCK_FREQ_EHL, },
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{ } /* Terminating Entry */
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};
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MODULE_DEVICE_TABLE(pci, m_can_pci_id_table);
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static struct pci_driver m_can_pci_driver = {
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.name = "m_can_pci",
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.probe = m_can_pci_probe,
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.remove = m_can_pci_remove,
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.id_table = m_can_pci_id_table,
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.driver = {
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.pm = &m_can_pci_pm_ops,
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},
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};
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module_pci_driver(m_can_pci_driver);
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MODULE_AUTHOR("Felipe Balbi (Intel)");
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MODULE_AUTHOR("Jarkko Nikula <jarkko.nikula@linux.intel.com>");
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MODULE_AUTHOR("Raymond Tan <raymond.tan@intel.com>");
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MODULE_LICENSE("GPL");
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MODULE_DESCRIPTION("CAN bus driver for Bosch M_CAN controller on PCI bus");
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