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ded2ee3631
This patch adds required definitions to allow for PCI buses on OpenRISC.
This is being tested on the OpenRISC QEMU virt platform which is in
development.
OpenRISC does not have IO ports so we keep the definition of
IO_SPACE_LIMIT and PIO_RESERVED to be 0.
Note, since commit 66bcd06099 ("parport_pc: Also enable driver for PCI
systems") all platforms that support PCI also need to support parallel
port. We add a generic header to support compiling parallel port
drivers, though they generally will not work as they require IO ports.
Signed-off-by: Stafford Horne <shorne@gmail.com>
246 lines
6.2 KiB
Text
246 lines
6.2 KiB
Text
# SPDX-License-Identifier: GPL-2.0
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#
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# For a description of the syntax of this configuration file,
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# see Documentation/kbuild/kconfig-language.rst.
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#
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config OPENRISC
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def_bool y
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select ARCH_32BIT_OFF_T
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select ARCH_HAS_DMA_SET_UNCACHED
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select ARCH_HAS_DMA_CLEAR_UNCACHED
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select ARCH_HAS_SYNC_DMA_FOR_DEVICE
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select COMMON_CLK
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select OF
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select OF_EARLY_FLATTREE
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select IRQ_DOMAIN
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select GPIOLIB
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select HAVE_ARCH_TRACEHOOK
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select SPARSE_IRQ
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select GENERIC_IRQ_CHIP
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select GENERIC_IRQ_PROBE
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select GENERIC_IRQ_SHOW
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select GENERIC_PCI_IOMAP
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select GENERIC_CPU_DEVICES
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select HAVE_PCI
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select HAVE_UID16
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select GENERIC_ATOMIC64
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select GENERIC_CLOCKEVENTS_BROADCAST
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select GENERIC_SMP_IDLE_THREAD
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select MODULES_USE_ELF_RELA
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select HAVE_DEBUG_STACKOVERFLOW
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select OR1K_PIC
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select CPU_NO_EFFICIENT_FFS if !OPENRISC_HAVE_INST_FF1
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select ARCH_USE_QUEUED_RWLOCKS
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select OMPIC if SMP
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select PCI_DOMAINS_GENERIC if PCI
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select PCI_MSI if PCI
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select ARCH_WANT_FRAME_POINTERS
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select GENERIC_IRQ_MULTI_HANDLER
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select MMU_GATHER_NO_RANGE if MMU
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select TRACE_IRQFLAGS_SUPPORT
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config CPU_BIG_ENDIAN
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def_bool y
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config MMU
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def_bool y
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config GENERIC_HWEIGHT
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def_bool y
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config NO_IOPORT_MAP
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def_bool y
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# For now, use generic checksum functions
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#These can be reimplemented in assembly later if so inclined
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config GENERIC_CSUM
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def_bool y
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config STACKTRACE_SUPPORT
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def_bool y
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config LOCKDEP_SUPPORT
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def_bool y
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menu "Processor type and features"
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choice
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prompt "Subarchitecture"
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default OR1K_1200
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config OR1K_1200
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bool "OR1200"
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help
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Generic OpenRISC 1200 architecture
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endchoice
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config DCACHE_WRITETHROUGH
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bool "Have write through data caches"
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default n
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help
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Select this if your implementation features write through data caches.
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Selecting 'N' here will allow the kernel to force flushing of data
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caches at relevant times. Most OpenRISC implementations support write-
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through data caches.
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If unsure say N here
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config OPENRISC_BUILTIN_DTB
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string "Builtin DTB"
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default ""
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menu "Class II Instructions"
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config OPENRISC_HAVE_INST_FF1
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bool "Have instruction l.ff1"
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default y
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help
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Select this if your implementation has the Class II instruction l.ff1
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config OPENRISC_HAVE_INST_FL1
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bool "Have instruction l.fl1"
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default y
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help
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Select this if your implementation has the Class II instruction l.fl1
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config OPENRISC_HAVE_INST_MUL
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bool "Have instruction l.mul for hardware multiply"
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default y
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help
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Select this if your implementation has a hardware multiply instruction
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config OPENRISC_HAVE_INST_DIV
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bool "Have instruction l.div for hardware divide"
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default y
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help
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Select this if your implementation has a hardware divide instruction
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config OPENRISC_HAVE_INST_CMOV
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bool "Have instruction l.cmov for conditional move"
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default n
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help
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This config enables gcc to generate l.cmov instructions when compiling
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the kernel which in general will improve performance and reduce the
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binary size.
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Select this if your implementation has support for the Class II
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l.cmov conistional move instruction.
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Say N if you are unsure.
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config OPENRISC_HAVE_INST_ROR
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bool "Have instruction l.ror for rotate right"
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default n
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help
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This config enables gcc to generate l.ror instructions when compiling
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the kernel which in general will improve performance and reduce the
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binary size.
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Select this if your implementation has support for the Class II
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l.ror rotate right instruction.
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Say N if you are unsure.
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config OPENRISC_HAVE_INST_RORI
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bool "Have instruction l.rori for rotate right with immediate"
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default n
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help
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This config enables gcc to generate l.rori instructions when compiling
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the kernel which in general will improve performance and reduce the
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binary size.
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Select this if your implementation has support for the Class II
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l.rori rotate right with immediate instruction.
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Say N if you are unsure.
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config OPENRISC_HAVE_INST_SEXT
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bool "Have instructions l.ext* for sign extension"
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default n
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help
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This config enables gcc to generate l.ext* instructions when compiling
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the kernel which in general will improve performance and reduce the
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binary size.
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Select this if your implementation has support for the Class II
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l.exths, l.extbs, l.exthz and l.extbz size extend instructions.
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Say N if you are unsure.
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endmenu
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config NR_CPUS
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int "Maximum number of CPUs (2-32)"
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range 2 32
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depends on SMP
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default "2"
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config SMP
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bool "Symmetric Multi-Processing support"
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help
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This enables support for systems with more than one CPU. If you have
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a system with only one CPU, say N. If you have a system with more
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than one CPU, say Y.
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If you don't know what to do here, say N.
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source "kernel/Kconfig.hz"
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config OPENRISC_NO_SPR_SR_DSX
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bool "use SPR_SR_DSX software emulation" if OR1K_1200
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default y
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help
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SPR_SR_DSX bit is status register bit indicating whether
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the last exception has happened in delay slot.
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OpenRISC architecture makes it optional to have it implemented
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in hardware and the OR1200 does not have it.
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Say N here if you know that your OpenRISC processor has
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SPR_SR_DSX bit implemented. Say Y if you are unsure.
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config OPENRISC_HAVE_SHADOW_GPRS
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bool "Support for shadow gpr files" if !SMP
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default y if SMP
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help
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Say Y here if your OpenRISC processor features shadowed
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register files. They will in such case be used as a
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scratch reg storage on exception entry.
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On SMP systems, this feature is mandatory.
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On a unicore system it's safe to say N here if you are unsure.
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config CMDLINE
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string "Default kernel command string"
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default ""
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help
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On some architectures there is currently no way for the boot loader
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to pass arguments to the kernel. For these architectures, you should
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supply some command-line options at build time by entering them
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here.
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menu "Debugging options"
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config JUMP_UPON_UNHANDLED_EXCEPTION
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bool "Try to die gracefully"
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default y
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help
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Now this puts kernel into infinite loop after first oops. Till
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your kernel crashes this doesn't have any influence.
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Say Y if you are unsure.
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config OPENRISC_ESR_EXCEPTION_BUG_CHECK
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bool "Check for possible ESR exception bug"
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default n
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help
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This option enables some checks that might expose some problems
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in kernel.
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Say N if you are unsure.
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endmenu
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endmenu
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